Integrated Circuit (e.g., Single Chip Semiconductor Device) Patents (Class 345/519)
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Patent number: 12216150Abstract: A method includes mapping an aging measurement circuit (AMC) into the core fabric of an FPGA and operating the AMC for a select time period. During the select period of time, the AMC counts transition of a signal propagating through the AMC. Timing information based on the counted transitions is stored in a timing model in a memory. The timing information represents an aging characteristic of the core fabric at a time that the AMC is operated. An EDA toolchain uses the timing information in the timing model to generate a timing guard-band for the configurable IC die. The AMC is removed from the core fabric and another circuit device is mapped and fitted into the core fabric using the generated timing guard-band models. The circuit device is operated in the configurable IC die based on the timing guard-band models.Type: GrantFiled: December 21, 2022Date of Patent: February 4, 2025Assignee: Altera CorporationInventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, Mahesh A. Iyer, Dhananjay Raghavan
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Patent number: 12131185Abstract: A method for managing general-purpose graphical processing units (GPGPUs) in a data center system is described. The method includes receiving, by a proxy agent, a GPGPU request from an application; selecting a GPGPU from a set of GPGPUs for processing a workload of the application based on one or more of available resources of the set of GPGPUs and requirements of the workload as indicated by the GPGPU request; establishing a session between an application agent located on a compute node on which the application is located and the proxy agent, and a second session between the GPGPU and the proxy agent in response to selecting the GPGPU to allow the GPGPU to process the workload, including subsequent GPGPU requests associated with the workload; and collecting a performance profile to describe usage of resources of the GPGPU by the workload.Type: GrantFiled: May 8, 2019Date of Patent: October 29, 2024Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Martin Julien, Ganapathy Raman Madanagopal
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Patent number: 12106443Abstract: Techniques for responsive video canvas generation are described to impart three-dimensional effects based on scene geometry to two-dimensional digital objects in a two-dimensional design environment. A responsive video canvas, for instance, is generated from input data including a digital video and scene data. The scene data describes a three-dimensional representation of an environment and includes a plurality of planes. A visual transform is generated and associated with each plane to enable digital objects to interact with the underlying scene geometry. In the responsive video canvas, an edit positioning a two-dimensional digital object with respect to a particular plane of the responsive video canvas is received. A visual transform associated with the particular plane is applied to the digital object and is operable to align the digital object to the depth and orientation of the particular plane. Accordingly, the digital object includes visual features based on the three-dimensional representation.Type: GrantFiled: February 23, 2022Date of Patent: October 1, 2024Assignee: Adobe Inc.Inventors: Cuong D. Nguyen, Valerie Lina Head, Talin Chris Wadsworth, Stephen Joseph DiVerdi, Paul John Asente
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Patent number: 12099378Abstract: Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.Type: GrantFiled: October 10, 2022Date of Patent: September 24, 2024Assignee: QUALCOMM IncorporatedInventors: Edwin Jose, Ravi Jenkal, Donghyun Kim
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Patent number: 12020620Abstract: Embodiments of this application disclose a display method, an electronic device, and a computer storage medium. The method includes: An electronic device obtains a first parameter, where the first parameter includes ambient light brightness and/or screen brightness. The electronic device determines, based on the first parameter, whether to enable a software scanning rate adjustment function, where the software scanning rate adjustment function is a function of separately adjusting a software scanning rate and a hardware scanning rate. The electronic device receives a first operation, where the first operation is a touch operation received by the electronic device when the software scanning rate adjustment function is enabled.Type: GrantFiled: January 11, 2022Date of Patent: June 25, 2024Assignee: Honor Device Co., Ltd.Inventors: Lifeng Cai, Hongyan Du
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Patent number: 11989563Abstract: Systems, apparatuses and methods may provide for technology that detects a low battery condition in a computing system including an integrated graphics processor and a discrete graphics processor, wherein the low battery condition is detected during a pre-boot stage of the computing system. The technology may also disable a root port associated with the discrete graphics processor in response to the low battery condition, conduct an initialization of an integrated display while the root port is disabled, and enable the root port in response to a successful negotiation of increased power by a verified read write code of an embedded controller of the computing system.Type: GrantFiled: December 4, 2020Date of Patent: May 21, 2024Assignee: Intel CorporationInventors: Subrata Banik, Rajaram Regupathy, Kalyan Kondapally
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Patent number: 11914540Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.Type: GrantFiled: May 5, 2022Date of Patent: February 27, 2024Assignee: Lemon Inc.Inventors: Yimin Chen, Shan Lu, Chuang Zhang, Junmou Zhang, Yuanlin Cheng, Jian Wang
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Patent number: 11842423Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.Type: GrantFiled: December 15, 2020Date of Patent: December 12, 2023Assignee: Intel CorporationInventors: Abhishek Appu, Subramaniam Maiyuran, Mike Macpherson, Fangwen Fu, Jiasheng Chen, Varghese George, Vasanth Ranganathan, Ashutosh Garg, Joydeep Ray
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Patent number: 11837195Abstract: A method implemented by a computing device comprises determining, by an original thread executing at a computing device, a command used to render a frame of a graphics application, the command being a call to a graphics interface, constructing, by the original thread executing at the computing device, a command stream based on the command, the command stream comprising a plurality of commands used to render the frame, and executing, by a command stream thread executing at the computing device, the command stream to render the frame of the graphics application.Type: GrantFiled: November 11, 2020Date of Patent: December 5, 2023Assignee: Huawei Technologies Co., Ltd.Inventors: Fan Zhang, Xiaoxing Zhu, Arturo Caballero, Gustavo Nunes, Aurelien Chanot
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Patent number: 11822491Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.Type: GrantFiled: October 20, 2021Date of Patent: November 21, 2023Assignee: NVIDIA CorporationInventors: John Feehrer, Denis Foley, Mark Hummel, Vyas Venkataraman, Ram Gummadi, Samuel H. Duncan, Glenn Dearth, Brian Kelleher
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Patent number: 11797346Abstract: An electronic device and a method of operating an electronic device are provided.Type: GrantFiled: November 30, 2020Date of Patent: October 24, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jinshik Bae, Hongcheol Sim, Kiljae Kim, Jaeho Kim, Hyunchul Seok, Youngcheol Sin, Wonseo Choi
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Patent number: 11763416Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.Type: GrantFiled: October 13, 2021Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker, Josh Mastronarde, Iqbal Rajwani, Lakshminarayanan Striramassarma, Melaku Teshome, Vikranth Vemulapalli, Binoj Xavier
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Patent number: 11756150Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.Type: GrantFiled: February 17, 2022Date of Patent: September 12, 2023Assignee: Intel CorporationInventors: Naveen Matam, Lance Cheney, Eric Finley, Varghese George, Sanjeev Jahagirdar, Altug Koker, Josh Mastronarde, Iqbal Rajwani, Lakshminarayanan Striramassarma, Melaku Teshome, Vikranth Vemulapalli, Binoj Xavier
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Patent number: 11604752Abstract: A data processing system comprising a plurality of processing units. Each processing unit comprises a set of plural functional units and an internal communications network that routes communications between the functional units in a particular sequence order of the functional units. Each processing unit is connected to at least one other processing unit via a communications bridge that has at least two connections, a first connection that routes communications between a first pair of network nodes of the pair of processing units, and a separate, second connection that routes communications between a second, different pair of network nodes of the pair of processing units. Each connected pair of network nodes comprises network nodes having different positions in the internal communications network sequence order of the network nodes and/or network nodes associated with functional units of different types.Type: GrantFiled: January 29, 2021Date of Patent: March 14, 2023Assignee: Arm LimitedInventors: Akshay Vijayashekar, Jussi Tuomas Pennala, Sebastian Marc Blasius
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Patent number: 11602010Abstract: An ‘open control network’ is described, wherein the control plane functions within the Radio Access Network (such as eNodeB and gNodeB) and Core Network (such as MME, AMF and SMF) provide an interface towards the operator and 3rd party control applications. Applications are allowed to securely register to signaling protocols within the control plane, specifically to the RAN or the Core Network control functions to view, intercept and intervene certain types of control messages or procedures. Innovative applications can be developed to view and modify control plane behavior utilizing both traditional methods as well as upcoming Machine Learning and Artificial Intelligence algorithms to provide services that are not part of standard operator offerings.Type: GrantFiled: July 19, 2021Date of Patent: March 7, 2023Assignee: Netsia, Inc.Inventors: Arda Akman, Burcu Yargicoglu
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Patent number: 11586580Abstract: A parallel processor system for machine learning includes an arithmetic unit (ALU) array including several ALUs and a controller to provide instructions for the ALUs. The system further includes a direct-access memory (DMA) block containing multiple DMA engines to access an external memory to retrieve data. An input-stream buffer decouples the DMA block from the ALU array and provides aligning and reordering of the retrieved data. The DMA engines operate in parallel and include rasterization logic capable of performing a three-dimensional (3-D) rasterization.Type: GrantFiled: July 8, 2021Date of Patent: February 21, 2023Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDInventor: Friederich Jean-Baptiste Mombers
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Patent number: 11403067Abstract: Systems, apparatuses, and methods related to a memory array data structure for posit operations are described. Universal number (unum) bit strings, such as posit bit string operands and posit bit strings representing results of arithmetic and/or logical operations performed using the posit bit string operands may be stored in a memory array. Circuitry deployed in a memory device may access the memory array to retrieve the unum bit string operands and/or the results of the arithmetic and/or logical operations performed using the unum bit string operands from the memory array. For instance, an arithmetic operation and/or a logical operation may be performed using a first unum bit string stored in the memory array and a second unum bit string stored in the memory array. The result of the arithmetic operation and/or the logical operation may be stored in the memory array and subsequently retrieved.Type: GrantFiled: March 20, 2019Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventor: Vijay S. Ramesh
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Patent number: 11275993Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.Type: GrantFiled: August 28, 2018Date of Patent: March 15, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takahiko Ishizu, Takayuki Ikeda, Atsuo Isobe, Atsushi Miyaguchi, Shunpei Yamazaki
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Patent number: 11244632Abstract: A display driving integrated circuit includes a timing controller, a first source driver including a first inverting input, a first non-inverting input, and a first output, a second source driver including a second inverting input, a second non-inverting input, and a second output, and a switching circuit connected with the display panel through a first and second pads. Under control of the timing controller, the switching circuit performs one of a first switching operation of connecting the first inverting input and the first output with the first pad, connecting the second inverting input and the second output with the second pad, and applying first and second decoding voltages to the non-inverting inputs, respectively; and a second switching operation of applying a sensing reference voltage to the non-inverting inputs, and connecting the output terminals with an output node, and connecting the inverting inputs with one pad.Type: GrantFiled: September 21, 2020Date of Patent: February 8, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jeeyeon Eom, Soonchan Kwon, Kyungjik Min, Yeongshin Jang, Jeonghoon Choi, Siwoo Kim, Jaeyoun Lee
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Patent number: 11150723Abstract: An electronic circuit includes a converter and a controller. The converter outputs a first voltage for a first cluster and a second voltage for a second cluster. When a first power to be provided to the first cluster based on the first voltage is lower than a first available power of the first cluster and a second power to be provided to the second cluster based on the second voltage is higher than a second available power of the second cluster, the controller outputs a first interrupt signal such that a level of the second voltage is adjusted based on a sum of the first power and the second power and a first threshold value determined based on the first available power and the second available power.Type: GrantFiled: August 27, 2019Date of Patent: October 19, 2021Assignee: Samsung Electronics Co., Ltd.Inventor: Donghee Han
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Patent number: 11114146Abstract: An erasable magnetoresistive random-access memory (MRAM) structure and a method of making the same includes an MRAM cell disposed between bit line and word line circuit elements, and a vertical-cavity surface-emitting laser (VCSEL) element disposed above the MRAM cell. A laser output of the VCSEL is directed toward the MRAM cell.Type: GrantFiled: November 25, 2019Date of Patent: September 7, 2021Assignee: International Business Machines CorporationInventors: Alexander Reznicek, Eric Raymond Evarts, Virat Vasav Mehta, Bahman Hekmatshoartabari
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Patent number: 11047907Abstract: A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.Type: GrantFiled: October 17, 2019Date of Patent: June 29, 2021Assignee: International Business Machines CorporationInventors: Sameh W. Asaad, Mohit Kapur
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Patent number: 11010953Abstract: Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.Type: GrantFiled: April 21, 2017Date of Patent: May 18, 2021Assignee: Intel CorporationInventors: Abhishek R. Appu, Prasoonkumar Surti, Srivallaba Mysore, Subhajit Dasgupta, Hiroshi Akiba, Eric J. Hoekstra, Linda L. Hurd, Travis T. Schluessler, Daren J. Schmidt
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Patent number: 10992494Abstract: A round-robin system having a suspend mechanism. The system may solve a synchronization issue relative to wireless communication with several hosts. With round-robin, a gateway device may permit user communication with one host at a time. The suspend mechanism, during a round-robin sequence, may enable a user with a request via an internet cloud, or the like, to interrupt the sequence and go to one specific host.Type: GrantFiled: September 15, 2012Date of Patent: April 27, 2021Assignee: Ademco Inc.Inventors: Zeng Huapeng, Patrick R. Lemire, Cherry Lv
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Patent number: 10846815Abstract: Virtual reality systems and methods are described. For example, one embodiment of an apparatus comprises: a communications interface to provide frame data of a virtual reality scene to a head mounted display (HMD); at least one performance monitor coupled to at least one component of the apparatus the at least one performance monitor to monitor performance of the at least one component and to send an alert based on the performance of the at least one component; a processor to process the frame data; a controller to receive the alert based on the performance of the at least one component and to offload processing of the frame data from the processor to the HMD for processing; and a display to show the rendered view of the scene.Type: GrantFiled: October 4, 2019Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Paul S. Diefenbaugh, Karthik Veeramani, Deepak S. Vembar, Rajneesh Chowdhury, Atsuo Kuwahara
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Patent number: 10824357Abstract: A process of updating data for a block of an array of data elements stored in an allocated memory region for the block comprises reading in data for a first group of the data elements, updating the data for the first group, and then writing back the updated data to memory. The process can avoid overwriting data for a second group of the data elements that is yet to be read in from the memory region by writing back the updated data for the first group starting at a selected memory address, for example other than the start address of the memory region. The data for the second group of data elements can then be read in and updated, and the updated data can be written back to memory. The process can reduce the amount of memory bandwidth and local cache that needs to be used.Type: GrantFiled: October 30, 2017Date of Patent: November 3, 2020Assignee: Arm LimitedInventors: Lars Oskar Flordal, Jian Wang, Jakob Axel Fries
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Patent number: 10726515Abstract: Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency.Type: GrantFiled: July 2, 2018Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: Kangyuan Shu, Junyong Ding, Yongnian Le, Weiliang Lion Lin, Xuefeng Deng, Yaojie Yan
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Patent number: 10613881Abstract: A host system includes a host device, a host buffer memory, and storage device. The host device includes a plurality of cores. The host buffer memory is configured to store a first command queue and a first map table, wherein each of the first command queue and the first map table corresponds to a first core of the cores. The storage device is configured to perform an input/output virtualization operation using the first core as a virtual core. The storage device uses the first command queue and the first map table during the input/output virtualization operation using the first core.Type: GrantFiled: January 15, 2016Date of Patent: April 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: TaeHack Lee, Je-Hyuck Song
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Patent number: 10613995Abstract: System and method for training and performing operations (e.g., read and write operations) on a double buffered memory topology. In some embodiments, eight DIMMs are coupled to a single channel. The training and operations schemes are configured with timing and signaling to allow training and operations with the double buffered memory topology. In some embodiments, the double buffered memory topology includes one or more buffers on a system board (e.g., motherboard).Type: GrantFiled: March 15, 2016Date of Patent: April 7, 2020Assignee: Rambus Inc.Inventors: Chi-Ming Yeung, Yoshie Nakabayashi, Thomas Giovannini, Henry Stracovsky
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Patent number: 10534422Abstract: A drive circuit applicable to a display device includes a first signal path and a second signal path. The first signal path, configured to receive and transmit image data, includes a compression unit configured to perform a compression procedure on the image data to generate compression data; a storage unit configured to store the compression data; and a de-compression unit configured to perform a de-compression procedure on the compression data to recover the image data. The second signal path is configured to transmit the image data to the storage unit so as to bypass the compression unit, and transmit the image data received from the storage unit to a display unit so as to bypass the de-compression unit when the image data is not transmitted by the first signal path. The received image data is passed through the first signal path or the second signal path depending upon its characteristics.Type: GrantFiled: June 28, 2018Date of Patent: January 14, 2020Assignee: NOVATEK Microelectronics Corp.Inventors: Kuei-Chung Chang, Feng-Jung Kuo, Hsi-Chi Ho
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Patent number: 10453168Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: August 17, 2018Date of Patent: October 22, 2019Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Patent number: 10432557Abstract: A network device may include a first forwarding board, a second forwarding board and an interface board. The interface board may include a control apparatus and a network interface chip. The control apparatus may form a first upstream packet flow which is sent to the first forwarding board via a first I/O bus and a second upstream packet flow which is sent to the second forwarding board via a second I/O bus using data packets received through the network interface chip from the exterior of the network device.Type: GrantFiled: August 25, 2016Date of Patent: October 1, 2019Assignee: NEW H3C TECHNOLOGIES CO., LTDInventor: Zhiyu Zhao
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Patent number: 10282809Abstract: A parallel data processing method based on multiple graphic processing units (GPUs) is provided, including: creating, in a central processing unit (CPU), a plurality of worker threads for controlling a plurality of worker groups respectively, the worker groups including one or more GPUs; binding each worker thread to a corresponding GPU; loading a plurality of batches of training data from a nonvolatile memory to GPU video memories in the plurality of worker groups; and controlling the plurality of GPUs to perform data processing in parallel through the worker threads. The method can enhance efficiency of multi-GPU parallel data processing. In addition, a parallel data processing apparatus is further provided.Type: GrantFiled: July 14, 2016Date of Patent: May 7, 2019Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Xing Jin, Yi Li, Yongqiang Zou, Zhimao Guo, Eryu Wang, Wei Xue, Bo Chen, Yong Li, Chunjian Bao, Lei Xiao
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Patent number: 10283083Abstract: A layer selection module for a graphics display component, and method therefor. The layer selection module is arranged to identify a set M of active layers to be blended for a pixel, configure a display controller to generate composite pixel data for the pixel based on a subset N of up to n layers from the set M, determine whether a number m of active layers in the set M exceeds n, and output an indication of which active layers within the set M were excluded from the subset N, if it is determined that the number m of layers in the set M exceeds n.Type: GrantFiled: May 9, 2017Date of Patent: May 7, 2019Assignee: NXP USA, Inc.Inventors: Michael Andreas Staudenmaier, Kshitij Bajaj, Chanpreet Singh, Vincent Aubineau
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Patent number: 10271091Abstract: A system that incorporates teachings of the present disclosure may include, for example, a communication device having a controller to determine a directive associated with an incoming communication session initiated by another communication device, providing an option that directs the media device to modify the media content being presented by a media device, providing a first instruction to the media device to modify the media presentation according to the directive responsive to a selection of the option, and providing a second instruction to the media device to resume the media presentation responsive to detecting a termination of the incoming communication session. Other embodiments are disclosed.Type: GrantFiled: October 2, 2017Date of Patent: April 23, 2019Assignee: AT&T Intellectual Property I, L.P.Inventors: William Stanley Robbins, R. Tyler Wallis, Anup D Karnalkar
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Patent number: 10181175Abstract: Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., an SRAM) are described. The pixel data may derive from a color camera or a depth camera in which individual pixel values are not a multiple of eight bits. In some cases, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one embodiment, the DMA engine may be configured to determine whether one or more pixels corresponding with the pixel data may be invalidated or skipped based on a minimum pixel value threshold and a maximum pixel value threshold and to embed pixel skipping information within unused bits of the pixel data.Type: GrantFiled: December 17, 2014Date of Patent: January 15, 2019Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Ryan Scott Haraden, Matthew Ray Tubbs, Adam James Muff, Robert Allen Shearer
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Patent number: 10147157Abstract: System on chip comprising a general purpose processing element, a graphics processing unit and a display interface, supporting graphics visualization on mobile computing devices and on embedded systems.Type: GrantFiled: May 19, 2014Date of Patent: December 4, 2018Assignee: Google LLCInventor: Reuven Bakalash
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Patent number: 10127040Abstract: The present application discloses a processor and a method for executing an instruction on a processor. A specific implementation of the processor includes: a host interaction device, an instruction control device, an off-chip memory, an on-chip cache and an array processing device, wherein the host interaction device is configured to exchange data and instructions with a host connected with the processor, wherein the exchanged data has a granularity of a matrix; the off-chip memory is configured to store a matrix received from the host, on which a matrix operation is to be performed; and the instruction control device is configured to convert an external instruction received from the host to a series of memory access instructions and a series of computing instructions and execute the converted instructions. The implementation can improve the execution efficiency of a deep learning algorithm.Type: GrantFiled: September 28, 2016Date of Patent: November 13, 2018Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.Inventors: Wei Qi, Jian Ouyang, Yong Wang
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Patent number: 10079004Abstract: A display controller includes a scaler which is configured to receive a frame image, scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device, and output the frame image or the high resolution frame image to the display device for display. A method of controlling image display includes: receiving a frame image; determining whether to scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device; scaling up the frame image according to a result of the determining; and outputting the frame image or the high resolution frame image for display at the display device.Type: GrantFiled: November 19, 2014Date of Patent: September 18, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Chul Yoon, Jong-Ho Roh, Jae-Sop Kong
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Patent number: 10055806Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: October 27, 2015Date of Patent: August 21, 2018Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Patent number: 10032245Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: October 27, 2015Date of Patent: July 24, 2018Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Patent number: 10019776Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.Type: GrantFiled: October 27, 2015Date of Patent: July 10, 2018Assignee: NVIDIA CORPORATIONInventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
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Patent number: 10002402Abstract: Convolution neural networks are able to be trained using a GPU and a CPU. To efficiently utilize a device's resources, the HetNet and HybNet approaches have been developed. The HetNet approach separates batches into partitions such that the GPU and CPU process separate batches. The HybNet approach separates the layers of a convolution neural network for the GPU and CPU.Type: GrantFiled: July 22, 2016Date of Patent: June 19, 2018Assignee: Sony CorporationInventors: Ming-Chang Liu, Xun Xu, Da Li
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Patent number: 9983833Abstract: A method of updating a file in a solid state drive (SSD) and an SSD configured to update a file in the SSD is disclosed. In one embodiment, the method includes performing one or more writes to a holding file in an auxiliary memory, the one or more writes corresponding to an update for a target file in the auxiliary memory. The method further includes applying the update to the target file in the auxiliary memory when each of the one or more writes has been successfully written to the holding file, and resetting the holding file when less than all of the one or more writes have been successfully written to the holding file. In one embodiment, a flash controller in communication with the auxiliary memory performs the update.Type: GrantFiled: December 23, 2015Date of Patent: May 29, 2018Assignee: Toshiba Memory CorporationInventors: Gordon W. Waidhofer, Ali Aiouaz, Christopher S. Delaney, Leland W. Thompson
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Patent number: 9978117Abstract: A semiconductor apparatus pertaining to one embodiment has: a first processor that operates by a first program and reads pixel data from a storage unit; a second processor that operates by a second program, performs processing to the pixel data, and writes the processed pixel data back to the storage unit; and a buffer circuit that transfers the pixel data from the first processor to the second processor.Type: GrantFiled: January 26, 2014Date of Patent: May 22, 2018Assignee: Renesas Electronics CorporationInventors: Manabu Koike, Akihiro Yamamoto, Atsushi Nakamura, Hideaki Kido
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Patent number: 9965824Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors.Type: GrantFiled: April 23, 2015Date of Patent: May 8, 2018Assignee: Google LLCInventors: Qiuling Zhu, Ofer Shacham, Albert Meixner, Jason Rupert Redgrave, Daniel Frederic Finchelstein, David Patterson, Neeti Desai, Donald Stark, Edward T. Chang, William R. Mark
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Patent number: 9913399Abstract: An information handling system, includes a server rack including a first communication device. The server rack has a mounting flange with a plurality of mounting holes. The information handling system also includes a server installed in the server rack and secured to the mounting flange via a first mounting hole of the plurality of mounting holes. The server includes a second communication device, that is coupled to the first communication device via a second mounting hole of the plurality of mounting holes.Type: GrantFiled: February 9, 2015Date of Patent: March 6, 2018Assignee: DELL PRODUCTS, LPInventors: Jinsaku Masuyama, Sajjad S. Ahmed, John R. Palmer
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Patent number: 9905193Abstract: A display driver integrated circuit (DDI) for driving a display of image data on a display panel, an application processor (AP), a system including the DDI and the AP, and methods of operating the same are provided. The application processor includes: a controller configured to obtain a frequency of a data transmission timing control received from a display driver integrated circuit (DDI), and to generate, based on the obtained frequency, a frequency control signal for adjusting a frequency related to an operating clock signal for the DDI; a transmitter configured to transmit the generated frequency control signal to the DDI; and a frequency calculation circuit including: a detector configured to receive the data transmission timing control signal from the DDI, and a frequency calculator configured to calculate a frequency of the received data transmission timing control signal.Type: GrantFiled: July 11, 2014Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee Tae Oh, Dong Hwy Kim, Do Kyung Kim
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Patent number: 9858889Abstract: A color compensation circuit comprises an acquisition unit for acquiring, from a video signal, gray image of a frame to be displayed and chrominance image of any color; wherein a chrominance value in the video signal, corresponding to at least a portion of pixels within the chrominance image, is absent; a processing unit for smoothly processing the chrominance value in the chrominance image according to the change trend of gray value in the gray image to obtain a chrominance image with color compensated. The present disclosure can solve the problem that compression and decompression of a video signal during transmission will significantly decrease the frame display effect, and thereby helping improve the frame display effect in a transmission scenario with the loss of chrominance value of the video signal.Type: GrantFiled: April 8, 2016Date of Patent: January 2, 2018Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Tianyue Zhao, Lijie Zhang, Xitong Ma, Yanfu Li
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Patent number: 9860139Abstract: In one embodiment, a client device configured to remotely access a desktop hosted by a server system determines an event related to a user input for a desktop operation directed to the desktop. The client device receives a plurality of updates to a desktop graphical user interface (GUI) from the desktop hosted by the server system. Then, the client device correlates the event to an update in the plurality of updates to the desktop GUI based on a rule in a set of rules correlating events to updates. A metric is monitored for the update and information measured for the metric is stored.Type: GrantFiled: March 6, 2013Date of Patent: January 2, 2018Assignee: VMware, Inc.Inventors: Lawrence Spracklen, Banit Agrawal, Rishi Bidarkar, Vikram Makhija