Integrated Circuit (e.g., Single Chip Semiconductor Device) Patents (Class 345/519)
  • Patent number: 10282809
    Abstract: A parallel data processing method based on multiple graphic processing units (GPUs) is provided, including: creating, in a central processing unit (CPU), a plurality of worker threads for controlling a plurality of worker groups respectively, the worker groups including one or more GPUs; binding each worker thread to a corresponding GPU; loading a plurality of batches of training data from a nonvolatile memory to GPU video memories in the plurality of worker groups; and controlling the plurality of GPUs to perform data processing in parallel through the worker threads. The method can enhance efficiency of multi-GPU parallel data processing. In addition, a parallel data processing apparatus is further provided.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: May 7, 2019
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Xing Jin, Yi Li, Yongqiang Zou, Zhimao Guo, Eryu Wang, Wei Xue, Bo Chen, Yong Li, Chunjian Bao, Lei Xiao
  • Patent number: 10283083
    Abstract: A layer selection module for a graphics display component, and method therefor. The layer selection module is arranged to identify a set M of active layers to be blended for a pixel, configure a display controller to generate composite pixel data for the pixel based on a subset N of up to n layers from the set M, determine whether a number m of active layers in the set M exceeds n, and output an indication of which active layers within the set M were excluded from the subset N, if it is determined that the number m of layers in the set M exceeds n.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: May 7, 2019
    Assignee: NXP USA, Inc.
    Inventors: Michael Andreas Staudenmaier, Kshitij Bajaj, Chanpreet Singh, Vincent Aubineau
  • Patent number: 10271091
    Abstract: A system that incorporates teachings of the present disclosure may include, for example, a communication device having a controller to determine a directive associated with an incoming communication session initiated by another communication device, providing an option that directs the media device to modify the media content being presented by a media device, providing a first instruction to the media device to modify the media presentation according to the directive responsive to a selection of the option, and providing a second instruction to the media device to resume the media presentation responsive to detecting a termination of the incoming communication session. Other embodiments are disclosed.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 23, 2019
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: William Stanley Robbins, R. Tyler Wallis, Anup D Karnalkar
  • Patent number: 10181175
    Abstract: Methods for preprocessing pixel data using a Direct Memory Access (DMA) engine during a data transfer of the pixel data from a first memory (e.g., a DRAM) to a second memory (e.g., an SRAM) are described. The pixel data may derive from a color camera or a depth camera in which individual pixel values are not a multiple of eight bits. In some cases, the DMA engine may perform a variety of image processing operations on the pixel data prior to the pixel data being written into the second memory. In one embodiment, the DMA engine may be configured to determine whether one or more pixels corresponding with the pixel data may be invalidated or skipped based on a minimum pixel value threshold and a maximum pixel value threshold and to embed pixel skipping information within unused bits of the pixel data.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: January 15, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Ryan Scott Haraden, Matthew Ray Tubbs, Adam James Muff, Robert Allen Shearer
  • Patent number: 10147157
    Abstract: System on chip comprising a general purpose processing element, a graphics processing unit and a display interface, supporting graphics visualization on mobile computing devices and on embedded systems.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: December 4, 2018
    Assignee: Google LLC
    Inventor: Reuven Bakalash
  • Patent number: 10127040
    Abstract: The present application discloses a processor and a method for executing an instruction on a processor. A specific implementation of the processor includes: a host interaction device, an instruction control device, an off-chip memory, an on-chip cache and an array processing device, wherein the host interaction device is configured to exchange data and instructions with a host connected with the processor, wherein the exchanged data has a granularity of a matrix; the off-chip memory is configured to store a matrix received from the host, on which a matrix operation is to be performed; and the instruction control device is configured to convert an external instruction received from the host to a series of memory access instructions and a series of computing instructions and execute the converted instructions. The implementation can improve the execution efficiency of a deep learning algorithm.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: November 13, 2018
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
    Inventors: Wei Qi, Jian Ouyang, Yong Wang
  • Patent number: 10079004
    Abstract: A display controller includes a scaler which is configured to receive a frame image, scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device, and output the frame image or the high resolution frame image to the display device for display. A method of controlling image display includes: receiving a frame image; determining whether to scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device; scaling up the frame image according to a result of the determining; and outputting the frame image or the high resolution frame image for display at the display device.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: September 18, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Chul Yoon, Jong-Ho Roh, Jae-Sop Kong
  • Patent number: 10055806
    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: August 21, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
  • Patent number: 10032245
    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: July 24, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
  • Patent number: 10019776
    Abstract: A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: July 10, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Ziyad Hakura, Eric Lum, Dale Kirkland, Jack Choquette, Patrick R. Brown, Yury Y. Uralsky, Jeffrey Bolz
  • Patent number: 10002402
    Abstract: Convolution neural networks are able to be trained using a GPU and a CPU. To efficiently utilize a device's resources, the HetNet and HybNet approaches have been developed. The HetNet approach separates batches into partitions such that the GPU and CPU process separate batches. The HybNet approach separates the layers of a convolution neural network for the GPU and CPU.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: June 19, 2018
    Assignee: Sony Corporation
    Inventors: Ming-Chang Liu, Xun Xu, Da Li
  • Patent number: 9983833
    Abstract: A method of updating a file in a solid state drive (SSD) and an SSD configured to update a file in the SSD is disclosed. In one embodiment, the method includes performing one or more writes to a holding file in an auxiliary memory, the one or more writes corresponding to an update for a target file in the auxiliary memory. The method further includes applying the update to the target file in the auxiliary memory when each of the one or more writes has been successfully written to the holding file, and resetting the holding file when less than all of the one or more writes have been successfully written to the holding file. In one embodiment, a flash controller in communication with the auxiliary memory performs the update.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: May 29, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Gordon W. Waidhofer, Ali Aiouaz, Christopher S. Delaney, Leland W. Thompson
  • Patent number: 9978117
    Abstract: A semiconductor apparatus pertaining to one embodiment has: a first processor that operates by a first program and reads pixel data from a storage unit; a second processor that operates by a second program, performs processing to the pixel data, and writes the processed pixel data back to the storage unit; and a buffer circuit that transfers the pixel data from the first processor to the second processor.
    Type: Grant
    Filed: January 26, 2014
    Date of Patent: May 22, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Manabu Koike, Akihiro Yamamoto, Atsushi Nakamura, Hideaki Kido
  • Patent number: 9965824
    Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: May 8, 2018
    Assignee: Google LLC
    Inventors: Qiuling Zhu, Ofer Shacham, Albert Meixner, Jason Rupert Redgrave, Daniel Frederic Finchelstein, David Patterson, Neeti Desai, Donald Stark, Edward T. Chang, William R. Mark
  • Patent number: 9913399
    Abstract: An information handling system, includes a server rack including a first communication device. The server rack has a mounting flange with a plurality of mounting holes. The information handling system also includes a server installed in the server rack and secured to the mounting flange via a first mounting hole of the plurality of mounting holes. The server includes a second communication device, that is coupled to the first communication device via a second mounting hole of the plurality of mounting holes.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: March 6, 2018
    Assignee: DELL PRODUCTS, LP
    Inventors: Jinsaku Masuyama, Sajjad S. Ahmed, John R. Palmer
  • Patent number: 9905193
    Abstract: A display driver integrated circuit (DDI) for driving a display of image data on a display panel, an application processor (AP), a system including the DDI and the AP, and methods of operating the same are provided. The application processor includes: a controller configured to obtain a frequency of a data transmission timing control received from a display driver integrated circuit (DDI), and to generate, based on the obtained frequency, a frequency control signal for adjusting a frequency related to an operating clock signal for the DDI; a transmitter configured to transmit the generated frequency control signal to the DDI; and a frequency calculation circuit including: a detector configured to receive the data transmission timing control signal from the DDI, and a frequency calculator configured to calculate a frequency of the received data transmission timing control signal.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee Tae Oh, Dong Hwy Kim, Do Kyung Kim
  • Patent number: 9860139
    Abstract: In one embodiment, a client device configured to remotely access a desktop hosted by a server system determines an event related to a user input for a desktop operation directed to the desktop. The client device receives a plurality of updates to a desktop graphical user interface (GUI) from the desktop hosted by the server system. Then, the client device correlates the event to an update in the plurality of updates to the desktop GUI based on a rule in a set of rules correlating events to updates. A metric is monitored for the update and information measured for the metric is stored.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: January 2, 2018
    Assignee: VMware, Inc.
    Inventors: Lawrence Spracklen, Banit Agrawal, Rishi Bidarkar, Vikram Makhija
  • Patent number: 9858889
    Abstract: A color compensation circuit comprises an acquisition unit for acquiring, from a video signal, gray image of a frame to be displayed and chrominance image of any color; wherein a chrominance value in the video signal, corresponding to at least a portion of pixels within the chrominance image, is absent; a processing unit for smoothly processing the chrominance value in the chrominance image according to the change trend of gray value in the gray image to obtain a chrominance image with color compensated. The present disclosure can solve the problem that compression and decompression of a video signal during transmission will significantly decrease the frame display effect, and thereby helping improve the frame display effect in a transmission scenario with the loss of chrominance value of the video signal.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: January 2, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tianyue Zhao, Lijie Zhang, Xitong Ma, Yanfu Li
  • Patent number: 9779555
    Abstract: A virtual reality system is provided. The virtual reality system includes a host device and a head mounted display apparatus to be worn by a user. The head mounted display apparatus includes a first wireless module, a second wireless module, a multimedia module, a multi-sensing module, and a peripheral hub. The multimedia module receives multimedia content from the host device through the first wireless module. The multi-sensing module obtains sensing information regarding the head mounted display apparatus and the user. The peripheral hub receives communication data from the host device through the second wireless module, and provides the sensing information to the host device through the second wireless module.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: October 3, 2017
    Assignee: HTC Corporation
    Inventors: Wei-Chih Chang, Mong-Yu Tseng
  • Patent number: 9778937
    Abstract: Certain aspects direct to a computing device, which include a processor, a microcontroller, a random access memory (RAM) having a frame buffer, a video controller configured to read video data from the frame buffer, and a non-volatile memory. The processor, the microcontroller, the RAM, the video controller, and the non-volatile memory are in communication with each other. The non-volatile memory stores an operating system, a media player, and first video data. The processor is configured to load the operating system to the RAM and execute the operating system. While the processor is loading the operating system, the microcontroller is configured to load and execute the media player into the RAM. The media player, when executed by the microcontroller, is configured to read the first video data from the non-volatile memory, and write second video data representing the first video data to the frame buffer.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: October 3, 2017
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventor: Clas Gerhard Sivertsen
  • Patent number: 9740553
    Abstract: Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: August 22, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Bruce Holmer, Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Ross Segelken, Darrell D. Boggs, Magnus Ekman
  • Patent number: 9712918
    Abstract: An audio processor has a number of ports that are configurable as input or output ports. Each port includes a jack, an input audio circuit and an output audio circuit. A switch is controllable to selectively connect an output of the output audio circuit to the jack when the port is configured as an output port. In one embodiment, the switch is bypassed with resistor and the output of the output audio circuit is coupled through the resistor to the jack when the port is configured as an input port.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: July 18, 2017
    Assignee: QSC, LLC
    Inventor: David Dean Kessner
  • Patent number: 9691438
    Abstract: A semiconductor device includes: first and second memory cell regions disposed adjacent to each other in a first direction, and suitable for sharing a sub-word line driving signal, and a first sub-word line driving unit disposed in a crossing area that is disposed between the first and second memory cell regions in a diagonal direction. The first sub-word line driving unit includes a first sub-word line driver for driving the first memory cell regions, a second sub-word line driver for driving the second memory cell regions, and an interconnection for transmitting the sub-word line driving signal, which extends in the first direction.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: June 27, 2017
    Assignee: SK Hynix Inc.
    Inventor: Seol Hee Lee
  • Patent number: 9645828
    Abstract: A method includes comparing, in units of a first bit length, a first bit sequence of the first bit length included in a search character bit sequence to a second bit sequence of a second bit length included in a target character bit sequence; when a third bit sequence of the first bit length following the first bit sequence in the search character bit sequence matches a fourth bit sequence of the first bit length following a location matching the first bit sequence in the second bit sequence, creating a fifth bit sequence of the second bit length starting from a location matching the first bit sequence in the target character bit sequence; comparing, in units of the first bit length, the fifth bit sequence to a sixth bit sequence of the second bit length starting from the first bit sequence in the search character bit sequence; and determining.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: May 9, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kokichi Sugiyama, Takayuki Sano, Naohiro Itou, Mikio Yoshida, Toshiyuki Kurokawa, Motonori Yoshinaga
  • Patent number: 9613389
    Abstract: A method for hiding texture latency in a multi-thread virtual pipeline (MVP) processor including the steps of: allowing the MVP processor to start running a main rendering program; segmenting registers of various MVP kernel instances in the MVP processor according to the length set, acquiring a plurality of register sets with the same length, binding the register sets to chipsets of the processor at the beginning of the running of the kernel instance; allowing a shader thread to give up a processing time slot occupied by the shader thread after sending a texture detail request, and setting a Program Counter (PC) value in the case of return; and returning texture detail and allowing the shader thread to restart running.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 4, 2017
    Assignee: SHENZHEN ZHONGWEIDIAN TECHNOLOGY LIMITED
    Inventors: Simon Moy, Shihao Wang, Zhengqian Qiu
  • Patent number: 9519384
    Abstract: A control system for a capacitive touch screen is provided. The control system comprises a touch detecting circuit, touch hard instruction, a storage module and a controller. The touch detecting circuit detects a capacitance variance to generate touch data. The touch hard instruction executes a touch computing function on the touch data. The storage module is connected to the touch detecting circuit and the at least one touch hard instruction, and records the touch data generated by the touch detecting circuit and the touch data computed by the touch hard instruction. The controller is connected to the touch detecting circuit, the at least one touch hard instruction, and the storage module, and assigns at least one touch task of a touch algorithm to the at least one touch hard instruction, so as to execute a corresponding touch computing function of the touch algorithm.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: December 13, 2016
    Assignee: FocalTech Systems Co., Ltd.
    Inventors: Chien-Ying Huang, Hsin-Mao Huang
  • Patent number: 9519527
    Abstract: Certain aspects direct to systems and methods for performing internal system interface-based communications between Intelligent Platform Management Interface (IPMI) stack and management services in management controllers. The system includes a server management device, which has an IPMI stack and at least one management service module. The management service module, when executed, provides a corresponding management service. In operation, the server management device defines an internal system interface, and configures the internal system interface to establish an inter-process communication (IPC) channel between the IPMI stack and the management service using the internal system interface. Thus, an internal communication between the IPMI stack and the management service may be performed through the IPC channel.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: December 13, 2016
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Anurag Bhatia, Samvinesh Christopher, Winston Thangapandian
  • Patent number: 9513927
    Abstract: Certain aspects direct to a computing device, which include a processor, a random access memory (RAM) having a frame buffer, a video controller configured to read video data from the frame buffer, and a non-volatile memory. The non-volatile memory stores an operating system, a media player, and first video data. The processor is configured to load the boot program to the RAM and execute the boot program. The boot program is configured to, when executed at the processor, boot the operating system in a first process or thread of the boot program, and load the media player and execute the media player in a second process or thread separate from a first process or thread. The media player is configured to, when executed by the processor, read the first video data from the non-volatile memory, and write second video data representing the first video data to the frame buffer.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: December 6, 2016
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventor: Clas Gerhard Sivertsen
  • Patent number: 9514365
    Abstract: An integrated circuit has an image sensor to receive at least one image comprising a plurality of pixels from a camera comprising a lens, a buffer communicatively connected to the image sensor for storing values associated with the plurality of pixels, and a comparator communicately connected to the buffer to locate and identify the iris of a subject, in which locating and identifying the iris of the subject is based on a location of each pixel in a brightest pixel set. A method for locating and identifying an iris in an image includes capturing at least one image of an illuminated subject, determining a brightness value for each of the plurality of pixels, determining a location corresponding to each pixel in a brightest pixel set, and identifying the iris in the at least one image based on the location of each pixel in the brightest pixel set.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: December 6, 2016
    Assignee: Princeton Identity, Inc.
    Inventors: Michael Tinker, David Alan Ackerman, Raymond Kolczynski, James Bergen
  • Patent number: 9424622
    Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 23, 2016
    Assignee: ATI Technologies ULC
    Inventors: Grigori Temkine, Gordon Caruk, Oleg Drapkin
  • Patent number: 9367889
    Abstract: A system and method for propagating scene information to a renderer. In one embodiment, the system includes: (1) an update request receiver operable to receive an update request from the renderer and determine a point from which the renderer is to be updated and (2) an update propagator associated with the update request receiver and operable to employ a graph containing scene information to construct a change list corresponding to the update request and transmit the change list toward the renderer.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: June 14, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Julia Flötotto, Stefan Radig
  • Patent number: 9363503
    Abstract: An image access method applicable to an image access device is provided. The method includes: providing a plurality of codes that respectively represent a plurality of image sources; determining a plurality of sets of access settings according to a pixel format arrangement, each set of access setting corresponding to a code arrangement combination composed of the codes; and sequentially accessing data of the image sources by the image access apparatus according to the code arrangement combinations corresponding to the access settings.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: June 7, 2016
    Assignee: MStar Semiconductor, Inc.
    Inventors: Chih-Hao Chang, Huan-Chun Tseng, Cheng-Yu Hsieh
  • Patent number: 9338817
    Abstract: There is provided a system for reducing the risk of data corruption occurring in wireless systems, by reducing the risk of an un-expected disconnection occurring between a client device (20; 52, 54, 56) and a host device (20; 50). The client device monitors its own power supply, and when the client device determines that its power supply capacity is almost exhausted, the client device sends a low power notification (5; 55) to the host device. The host device receives the low power notification, and in response closes the wireless connection to the client device, thereby preventing an unexpected disconnection from occurring when the clients power supply is finally exhausted.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: May 10, 2016
    Assignee: NXP B.V.
    Inventors: Yuxi Sun, Bart Vertenten
  • Patent number: 9280362
    Abstract: A system and apparatus is disclosed for sharing a host computer. The system discloses: a set of USB cables; a set of virtualization devices, a set of USB ports on the host computer, an operating system; and a virtualization module. The apparatus discloses: a hub controller; a graphics display module; and an audio controller.
    Type: Grant
    Filed: November 15, 2009
    Date of Patent: March 8, 2016
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Thomas Flynn
  • Patent number: 9269120
    Abstract: According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Nikos Kaburlasos, Eric C. Samson, Altug Koker
  • Patent number: 9262795
    Abstract: Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Kangyuan Shu, Junyong Ding, Yongnian Le, Weiliang Lion Lin, Xuefeng Deng, Yaojie Yan
  • Patent number: 9256914
    Abstract: A graphics card is provided. The graphics card comprises: a Graphics Processing Units (GPU) for data computing; and a wireless controller for wirelessly receiving data from other graphic cards or sending data to the other graphics cards, and communicating with the GPU by bus. The graphic card able provided by the present invention can provide a low-cost solution with more powerful computing capabilities to meet the demands for computing complex problems in the fields of commerce, industry, and science.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: February 9, 2016
    Assignee: NVIDIA Corporation
    Inventors: Yu Zhang, Hao Zhu, Shuanghu Yan
  • Patent number: 9250692
    Abstract: A method includes providing, in a data processing device including a Central Processing Unit (CPU) and a Graphics Processing Unit (GPU), a capability to interface a microprocessor with the GPU, and communicatively interfacing a sensor with the microprocessor. The method also includes obtaining data related to an operating environment external to the data processing device through the sensor, and determining, through the microprocessor, personalization required of a computing environment of the data processing device with respect to a user thereof based on the data related to the operating environment external to the data processing device. Further, the method includes utilizing the GPU solely to effect the personalization required of the computing environment of the data processing device with respect to the user determined through the microprocessor to reduce power consumption through the data processing device.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: February 2, 2016
    Assignee: NVIDIA Corporation
    Inventor: Vivek Potpallewar
  • Patent number: 9223737
    Abstract: Methods and systems are provided routing access requests produced by a function to a physical sharing machine on a computer interconnect fabric. Access requests are routed through a switch that includes an NTB, the NTB using an address-lookup table to ensure that access requests made by multiple physical sharing machines are appropriately isolated from one another.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 29, 2015
    Assignee: Google Inc.
    Inventor: Benjamin C. Serebrin
  • Patent number: 9111370
    Abstract: Buffer display techniques are described. In one or more implementations, at least part of an off-screen buffer is rasterized by an application to generate an item for display by the computing device. One or more communications are formed that describe the part of the off-screen buffer which contains the item that is to be copied to update an onscreen buffer.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: August 18, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Leonardo E. Blanco, Daniel N. Wood, Max McMullen, Allison W. Klein, Brian T. Klamik, Michael I. Borysenko, Keith D. Melmon, Michael P. Crider, Silvana Patricia Moncayo
  • Patent number: 9088771
    Abstract: A mobile terminal as disclosed and broadly embodied herein may include a 3D display configured to display an object that includes a first and second images and a controller configured to change a magnification of the object that includes a first scaled image and a second scaled image and to correct a binocular disparity between the first and second scaled images. The controller may be configured to determine a binocular disparity between the first and second scaled images, determine whether the binocular disparity is within a prescribed range of disparity, reposition at least one of the first or second magnified images based on the determined binocular disparity, and control the display to display the corrected first and second scaled images.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: July 21, 2015
    Assignee: LG ELECTRONICS INC.
    Inventors: Hayang Jung, Seungmin Seen, Shinhae Lee, Jinsool Lee, Dongok Kim, Taeyun Kim, Seunghyun Woo
  • Patent number: 9070333
    Abstract: An information processing apparatus includes a first graphics chip, a second graphics chip, a detection unit, and a display unit. The first graphics chip has a first drawing processing capacity. The second graphics chip has a second drawing processing capacity different from the first drawing processing capacity. The detection unit detects a request to change over from an execution of the first graphics chip to an execution of the second graphics chip. The display unit displays a first window prompting to close an application in execution, in a case where the detection unit detects the request to change over from the execution of the first graphics chip to the execution of the second graphics chip.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: June 30, 2015
    Assignee: Sony Corporation
    Inventors: Masaru Kawata, Keiichi Nakayama, Asako Doi
  • Patent number: 9019285
    Abstract: A semiconductor integrated circuit device of the present invention connected to a memory in which display data for a display device is stored, and is adapted to read out the display data from the memory to transfer the same to the display device, the semiconductor integrated circuit device comprising: a display data buffer for holding the display data; a memory controller for prefetching the display data in page-size units of the memory to cause the same to be held by the display data buffer and, upon completing prefetching of one page, closing the page to cause the memory to shift into a power saving mode; and a display device controller for transferring the display data held in the display data buffer to the display device.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: April 28, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Shoji Kawahara
  • Patent number: 8988645
    Abstract: A display device includes a panel including pixels defined by data lines and gate lines, a housing chassis covering a sidewall and an edge of the panel, a printed circuit board under the panel, the printed circuit board including circuit elements configured to generate at least one of a data signal, a gate signal, and a control signal, a chip on film connecting the printed circuit board to the panel, the chip on film between the housing chassis and the sidewall of the panel, a driver integrated circuit mounted on the chip on film and configured to respond to the control signal and drive at least one of the data signal and the gate signal applied to the data lines and the gate lines, and a connection unit attaching the chip on film to the housing chassis and dissipating heat generated by the driver integrated circuit to the housing chassis.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jichul Kim, Young-Deuk Kim, Eunseok Cho, Mi-Na Choi
  • Patent number: 8937673
    Abstract: An image-displaying device includes a first storage section, an image data generation section, a timing information acquisition section and a display control section. The image data generation section is configured to output the image data to the first storage section with the image data being composed of a plurality of predetermined data units. The timing information acquisition section is configured to acquire timing information indicative of a timing related to generation and output of the image data to the first storage section with respect to each of the predetermined data units. The display control section is configured to control a display section to read and display an Nth one of the predetermined data units after output of an (N+i)th one of the predetermined data units to the first storage section is completed according to the timing information, where N is a natural number and i is a nonnegative integer.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: January 20, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Ryuichi Shiohara, Masahiro Kitano, Toshiyuki Yamamoto
  • Publication number: 20150015591
    Abstract: A display driver integrated circuit (DDI) for driving a display of image data on a display panel, an application processor (AP), a system including the DDI and the AP, and methods of operating the same are provided. The application processor includes: a controller configured to obtain a frequency of a data transmission timing control received from a display driver integrated circuit (DDI), and to generate, based on the obtained frequency, a frequency control signal for adjusting a frequency related to an operating clock signal for the DDI; a transmitter configured to transmit the generated frequency control signal to the DDI; and a frequency calculation circuit including: a detector configured to receive the data transmission timing control signal from the DDI, and a frequency calculator configured to calculate a frequency of the received data transmission timing control signal.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 15, 2015
    Inventors: Hee Tae OH, Dong Hwy KIM, Do Kyung KIM
  • Patent number: 8935623
    Abstract: A method of generating an application programming interface (API) for an electronic circuit. A graphical user interface is displayed through which a user can initiate generation of the API. A component is selected from a plurality of components for placement in said electronic circuit. The component represents an implementable function in the electronic circuit. The component is configured using the graphical user interface. The data pertaining to the selected component and the configuration of the component is stored. The graphical user interface is utilized to access the stored data. The interface is initiated to invoke a processing of said data which causes a generation of the application programming interface. The application interface is for controlling the function of the component in said electronic circuit.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: January 13, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kenneth Y. Ogami, Matthew A. Pleis
  • Patent number: 8933945
    Abstract: A graphics processing circuit includes at least two pipelines operative to process data in a corresponding set of tiles of a repeating tile pattern, a respective one of the at least two pipelines operative to process data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically repeating pattern of square regions. A graphics processing method includes receiving vertex data for a primitive to be rendered; generating pixel data in response to the vertex data; determining the pixels within a set of tiles of a repeating tile pattern to be processed by a corresponding one of at least two graphics pipelines in response to the pixel data, the repeating tile pattern including a horizontally and vertically repeating pattern of square regions; and performing pixel operations on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: January 13, 2015
    Assignee: ATI Technologies ULC
    Inventors: Mark M. Leather, Eric Demers
  • Patent number: 8913069
    Abstract: In one embodiment there is provided, a display driver system, comprising, at least one display driver; a magnetic random access memory (MRAM) macro; and a display driver interface coupling the MRAM macro and the at least one display driver.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: December 16, 2014
    Assignee: III Holdings 1, LLC
    Inventors: Krishnakumar Mani, Jay Kamdar
  • Patent number: 8902239
    Abstract: A video-processing chip capable of saving power is disclosed. The video-processing chip includes a microprocessor, a scalar, a first memory, and a second memory. The microprocessor is used for executing program codes. The scalar is used for adjusting a size of a received image. The first memory is coupled to the microprocessor and to the scalar for providing memory space to the scalar for image processing. The second memory is coupled to the microprocessor for storing the program codes of the microprocessor for controlling a power switch. Wherein a size of the first memory is greater than a size of the second memory.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: December 2, 2014
    Assignee: Princeton Technology Corporation
    Inventors: Meng-Fu Lin, Ying-Yuan Tang, Wei-Chih Huang