Abstract: A novel graphics system including workload detection software is disclosed. The novel graphics system increases the voltage and frequency of the graphics hardware in an integrated graphics chipset, depending on operations performed by the hardware, for either a performance advantage or a power savings advantage.

Abstract: A method for storing a first frame into a system, wherein the system includes i) a first chip, ii) a display controller, and iii) a copy device, and wherein the first chip includes a first memory. The method includes: reading, using the display controller, a first frame from a second memory, wherein the second memory is external to the first chip; and while the first frame is being read from the second memory by the display controller, using the copy device to copy the first frame from the second memory to the first memory. Subsequent to the copy device copying the first frame from the second memory to the first memory, the first frame is stored in both the first memory and the second memory.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A power supplying unit for a liquid crystal display device includes: a power integrated circuit for generating a source voltage and a compensation voltage, the compensation voltage linearly varying according to an ambient temperature; and a charge pumping part for generating a gate high voltage using the source voltage and the compensation voltage, the gate high voltage linearly varying when the ambient temperature is lower than a reference temperature.

Abstract: A system, method, and computer program product are provided for changing a refresh rate of a display system. In use, an aspect of hardware of a display system is identified. To this end, a refresh rate of the display system may be changed based on the identified aspect.

Abstract: An embodiment of a circuit includes an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.

Abstract: Embodiments of the invention provide assigning two different class identifiers to a device to allow loading to an operating system as different devices. The device may be a graphics device. The graphics device may be integrated in various configurations, including but not limited to a central processing unit, chipset and so forth. The processor or chipset may be associated with a first identifier associated with a graphics processor and a second device identifier that enables the processor or chipset as a co-processor.

Abstract: A system, method, and computer program product are provided for adjusting at least one aspect of a programmable graphics and/or audio processor. In use, at least one input parameter and at least one output parameter of a programmable graphics and/or audio processor are identified. Thereafter, at least one aspect of the programmable graphics and/or audio processor may thus be dynamically adjusted. Such adjustment is performed as a function of both the at least one input parameter and the at least one output parameter.

Abstract: A graphics processing method and apparatus described herein is capable of converting graphics processing of a window system into a vector-based application program interface (API) format usable in the GPU and performing the converted graphics processing in the GPU. For example, the vector-based API may be based on an OpenVG standard or an EGL standard.

Abstract: Some embodiments provide a method of performing several shading operations for a graphic object in a scene that is displayed on a device. The device includes several processing units. The method receives a set of criteria that can define a set of parameters that relate to the shading operations. The method determines an allocation of the shading operations to the processing units based on the received criteria. The method allocates the shading operations to the processing units based on the determined allocations. The method renders the graphic object based on several instructions that comprise the shading operations. In some embodiments, the set of criteria is received during execution of the operations.

Abstract: A system on chip (Soc) includes a system bus, a plurality of sub-systems, an image processing logic block, an image memory interface and an image processing memory block. The sub-systems are respectively connected to the system bus. The image processing logic block is connected to the system bus. The image processing logic block performs an image processing. The image processing logic block is included in a first power domain. The image memory interface is connected to the system bus and the image processing logic block. The image processing memory block is connected to the image memory interface. The image processing memory block is used for the image processing. The image memory interface and the image processing memory block are included in a second power domain different from the first power domain.

Abstract: In accordance with some embodiments, a graphics process frame generation frame rate may be monitored in combination with a utilization or work load metric for the graphics process in order to allocate performance resources to the graphics process and in some cases, between the graphics process and a central processing unit.

Abstract: A data processing apparatus including a first graphic controller configured to process a first image, the first image being one of a first still, moving and three dimensional (3D) image; a second graphic controller configured to process a second image, the second image being one of a second still, moving and three dimensional (3D) image, the first and second graphic controllers being integrated into one chip; and a controller operatively connected to the first and second graphic controllers and configured to determine whether to enable the second graphic controller, and change the second graphic controller from an inactive state to an enabled state. Further, though the second graphic controller is changed from the inactive state to the enabled state, the first graphic controller is maintained in an enabled state.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: According to one embodiment, a graphics processing unit detects characteristics of video data by analyzing frames of the video data by using at least one first processing core of a plurality of processing cores, and applies a process, which is associated with the detected characteristics of the video data, to audio data on a memory, by using at least one second processing core of the plurality of processing cores. The graphics processing unit includes an audio signal output interface and outputs an audio signal corresponding to the audio data, to which the process has been applied, to a sound device.

Abstract: A method of processing data relating to geometrical primitives is disclosed. Each of the primitives has a plurality of vertices. The method uses a plurality of processing elements in parallel with one another, and comprises assigning respective vertex data to the processing elements, on each processing element, and in parallel with one another, performing at least one processing step on vertex data to produce processed vertex data, and transferring processed vertex data between processing elements so as to assemble primitive data.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: A processing pipeline employs one or more bypass caches to allow a transaction that is dependent on the results of a prior transaction to be processed before the prior transaction has completed processing. Each bypass cache is coupled to the input and the output of one of the sections of the processing pipeline so that results of a transaction from that section can be written into or read from the bypass cache as soon as that transaction has been completely processed through that section. With such a configuration, more transactions can be processed by the processing pipeline in a shorter amount of time. This is especially true for very deep pipelines.

Abstract: An interface device having a video BIOS component. The device includes a substrate for implementing a mother board connection and implementing a GPU (graphics processor unit) connection. A video BIOS component is mounted on the substrate for providing video BIOS functions for the computer system.

Abstract: The present invention intends to realize a narrow frame of a system on panel. In addition to this, a system mounted on a panel is intended to make higher and more versatile in the functionality. In the invention, on a panel on which a pixel portion (including a liquid crystal element, a light-emitting element) and a driving circuit are formed, integrated circuits that have so far constituted an external circuit are laminated and formed. Specifically, of the pixel portion and the driving circuit on the panel, on a position that overlaps with the driving circuit, any one kind or a plurality of kinds of the integrated circuits is formed by laminating according to a transcription technique.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.

Abstract: A system, method, and computer program product are provided for validating a graphics processor design. In operation, a test image is identified. Additionally, a reference image is automatically selected from a set of reference images. Furthermore, a graphics processor design is validated using the test image and the selected reference image.

Abstract: An integrated video clock signal generator in which a master phase-locked loop (PLL) control circuit uses an off-chip voltage-controlled oscillator (VCO) to produce an on-chip oscillator signal in synchronization with a horizontal reference signal related to a horizontal video synchronization signal. This on-chip oscillator signal drives one or more slave PLL circuits which provide respective one or more on-chip PLL signals synchronized with the on-chip oscillator signal. In accordance with a preferred embodiment, each on-chip PLL signal is a pixel clock signal with a plurality of clock signal pulses which is synchronized with a vertical reference signal related to a vertical video synchronization signal.

Abstract: A system and method for adjusting pictures minimizes the impact on graphics processing performance of a discrete processor. A hybrid system configuration includes the discrete processor and an integrated processor, where the discrete processor typically consumes more power and provides greater processing performance compared with the integrated processor. A picture is produced by a video or graphics engine of a discrete processor within a hybrid system. Each picture is then transferred to a back buffer in the host processing memory. The picture is analyzed to produce picture analysis results that are used to generate adjustment settings. The back buffer is swapped to become the front buffer and the adjustment settings are applied to the picture by an integrated processor to display an adjusted picture. The adjustment may be used in conjunction with power saving techniques to maintain the image quality when display backlighting is reduced.

Abstract: One embodiment of the present invention sets forth a protocol for packing and transferring pixel data between integrated circuits. The data transfer protocol may be used between a graphics processing unit and a video output encoder unit. The data transfers may include up to 20 pixels per arbitration cycle. By packing pixel data for transfer over a bus with a relatively small set of output pins, overall package pin count is reduced, while maintaining sufficient bandwidth to carry the pixel data the output pins. By moving the analog circuitry to a separate device, linked to the GPU via the bus, noise from the GPU may be effectively mitigate through physical separation.

Abstract: A liquid crystal display device including a liquid crystal panel, a gate driver configured to drive a plurality of gate lines on the panel, a data driver configured to drive a plurality of data lines on the panel in response to the pixel data stream, a timing controller configured to control the gate driver and the data driver, and a single-chip drive voltage generating section configured to supply voltages used by the common electrode on the liquid crystal panel, the gate driver, the data driver, and the timing controller using an external input voltage.

Abstract: A data processor that includes a central processing unit, a graphic controller, a display controller, an image recognizing module, a memory controller and image data input units is disclosed. The components can be formed on a single semiconductor substrate. The display controller can perform display control on image data. The image data input unit stores the image data into a first area in the external memory. The image recognizing module or central processing unit executes an image process on the image data in the first area or image data in a second area, and stores a result of the process in a third area of the external memory.

Abstract: Apparatus are provided including assets defining 3D models, including 3D icons and scenes, and animations of the 3D models. An offline optimization engine is provided to process data to be acted upon by a graphics engine of a target embedded device. A graphics engine simulator is provided to simulate, on a computer platform other than a target embedded device, select functions of a target embedded device running a graphics engine including API calls that directly calls API functions of a hardware level API of the target embedded device.

Abstract: A system including a first chip, a display controller and a copy device. The first chip includes a first memory. The display controller is configured to read a first frame from a second memory external to the first chip. The copy device is configured to copy the first frame from the second memory to the first memory while the display controller reads the first frame from the second memory. Subsequent to the copy device copying the first frame from the second memory to the first memory, the first frame is stored in both the first memory and the second memory.

Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.

Abstract: Graphics rendering on a network on chip (‘NOC’) including receiving, in the geometry processor, a representation of an object to be rendered; converting, by the geometry processor, the representation of the object to two dimensional primitives; sending, by the geometry processor, the primitives to the plurality of scan converters; converting, by the scan converters, the primitives to fragments, each fragment comprising one or more portions of a pixel; for each fragment: selecting, by the scan converter for the fragment in dependence upon sorting rules, a pixel processor to process the fragment; sending, by the scan converter to the pixel processor, the fragment; and processing, by the pixel processor, the fragment to produce pixels for an image.

Abstract: A method and system for flexibly supplying power to a high-end graphics card is described. The graphics system includes the high-end graphics card and also a configurable power supply module, which is physically separated to the graphics card and connected to a power source external to the graphics system. The configurable power supply module converts a first voltage from the power source to a second voltage for the graphics card, wherein the second voltage satisfies a set of power supply specifications required by the graphics card.

Abstract: A method of manufacturing a solid state imaging device having a photo-electric conversion portion array and a transfer electrode array, these arrays being provided in parallel to each other, upper surfaces and side wall surfaces of the transfer electrode array being covered with a light-shielding layer, and a transparent layer showing an oxidizing property at the time of film formation, the transparent layer being formed on the photo-electric conversion parts and the light-shielding layer.

Abstract: To provide an image processing technique for easy initial settings when a video image feature is used as an input interface. This is an image processor having an image combining section 106 for combining a mirrored video image feature that includes an image of an operator as a portion thereof and an object image of an object that is associated with a predetermined event, to generate a combined image, and being adapted to provide production of the combined image on a display device. This image processor has a detection section 109 for detecting the position of an image of an operator included in the mirrored video image feature. The image combining section 106 is adapted to combine the object image and the mirrored video image feature in such a manner that the object image is displayed in a range that an image of a hand of the operator can reach, depending on the position of the image of the operator detected by the detection section 109.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system for performing graphics processing is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors can perform graphics processing on a first set of graphics data to generate a second set of graphics data, and another of the second processors can perform graphics processing on the second set to generate a third set of graphics data.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in an efficient manner. One such texture circuit can provide a configurable number of texel quads for a configurable number of pixels. For bilinear filtering, texels for a comparatively greater number of pixels can be retrieved. For trilinear filtering, texels in a first LOD are retrieved for a number of pixels during a first clock cycle, during a second clock cycle, texels in a second LOD are retrieved. When aniso filtering is needed, a greater number of texels can be retrieved for a comparatively lower number of pixels.

Abstract: Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.

Abstract: An image processor by way of a transistor array in which a plurality of transistors are formed on a substrate comprising a plurality of polysilicon thin-film transistors using a first semiconductor layer composed of polysilicon formed on the substrate and functional devices having a plurality of amorphous silicon thin-film transistors using a second semiconductor layer composed of amorphous silicon which are formed in an upper layer more superior than the first semiconductor layer. The polysilicon thin-film transistors and functional devices include a plurality of electrode layers composed of a conductor layer, for instance, the functional devices at least of any one of the electrode layers are formed in the same layer as any one the electrode layers of the polysilicon thin-film transistors.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: An integrated circuit is a baseboard management controller that is a fully integrated system-on-a-chip microprocessor incorporating function blocks and interfaces that provide remote management solution. The integrated circuit uses a microprocessor, a media co-processor to accelerate video processing, and a set of system and peripheral functions that are useful in a variety of remote management applications. It further includes an integrated USB high-speed device and an OTG interface to support keyboard, mouse and mass storage emulation without additional external components, and two integrated MII LAN interfaces and one FSB interface, a memory controller to support a variety of static and dynamic memory components, an encryption controller to ensure secure remote management sessions and IPMI2.0-compliant BMC interfaces. The integrated circuit is based on structured ASIC technology, which enables easy customization of function blocks according to customer demands or new industry standards.

Abstract: A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level of memory. In response, the variable clock control information generator produces graphics engine clock control information and memory clock control information with respect to each other, such that a relative difference between the graphics engine activity data and the memory activity data is within balance threshold data. Accordingly, the variable clock control information generator adapts to the varying levels of graphics engine activity and memory activity and adjusts the frequency of the graphics engine clock signal and the frequency of the memory clock signal to achieve a balanced relative activity level.

Abstract: An information processor for information registration, capturing means captures a graphics processing command, and database registering means registers, as information about completed work in the database, information about a series of graphics processing commands concerning completed works out of the captured graphics processing commands. In an information processor for information retrieval, proceeding work detecting means detects a work in progress as a proceeding work based on the captured graphics processing command, and information acquiring means searches a database for the information about the work in progress which has been done before based on the graphics processing command concerning the proceeding work and acquires the information about the work in progress which has been done before.

Abstract: A system-on-a-chip (SoC) to process digital audio-video content includes one or more input/output (I/O) interfaces to transmit the digital audio-video content to corresponding I/O devices coupled to the SoC and to receive the digital audio-video content from the corresponding I/O devices. The SoC also includes a cryptographic engine to encrypt the digital audio-video content being transmitted via the I/O interfaces to the corresponding I/O devices and to decrypt the digital audio-video content received via the I/O interfaces from the corresponding I/O devices.

Abstract: To provide an image data processing circuit with high productivity and a color image forming apparatus using the same by enabling sharing of the image data processing circuit between a four-rotation machine and a quadruple tandem machine, and reduction of registers for four colors arranged for the four-rotation machine to a single register for one color. There is provided an image forming apparatus in which a first image processing unit out of first and second image processing units provided in an image data processing circuit executes a first image processing for an image read by a scanner unit, stores an image signal in a page memory, the second image processing unit reads the image signal from the page memory according to a synchronous signal generated in an engine unit to execute a second image processing, and the engine unit forms the image on the basis of the results therefrom.

Abstract: An exemplary ultrasonic image processing system includes an ultrasonic transmitting apparatus, an ultrasonic receiving apparatus, a front-end processing circuit and a computer. The front-end processing circuit is electrically coupled to an ultrasonic probe through the ultrasonic transmitting apparatus and the ultrasonic receiving apparatus respectively. The computer is electrically coupled to the front-end processing circuit. The computer includes a central processing unit (CPU) and a graphics processing unit (GPU). The system employs the CPU to control the operations of the ultrasonic transmitting apparatus and the ultrasonic receiving apparatus through the front-end processing circuit, so as to acquire ultrasound scanning data. The system further employs the GPU to perform an image reconstruction process on the acquired ultrasound scanning data by way of multi-thread process, so as to generate an image display data. Moreover, a corresponding ultrasonic image processing method is also disclosed.

Abstract: An electrical device supporting switchable graphics function, electrically connected with a display unit, includes a first graphic chip, a second graphic chip, a peripheral, an Embedded Controller (EC) and a processing unit. Information of a present graphic chip is stored in an EC RAM of the EC, wherein the present graphic chip is one of the first graphic chip and the second graphic chip. A control unit of the EC obtains the information of the present graphic chip from the EC RAM and controls operation status of the peripheral according to the obtained information of the present graphic chip. The processing unit obtains the information of the present graphic chip from the EC RAM. The processing unit drives the present graphic chip to process an image signal and transmit the processed image signal to the display unit for display according to the obtained information of the present graphic chip.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: An integrated circuit includes at least two different types of processors. At least one operation is supported by both types of processors, which permits a commonly supported operation to be scheduled on either processor.