Abstract: A method for hiding texture latency in a multi-thread virtual pipeline (MVP) processor including the steps of: allowing the MVP processor to start running a main rendering program; segmenting registers of various MVP kernel instances in the MVP processor according to the length set, acquiring a plurality of register sets with the same length, binding the register sets to chipsets of the processor at the beginning of the running of the kernel instance; allowing a shader thread to give up a processing time slot occupied by the shader thread after sending a texture detail request, and setting a Program Counter (PC) value in the case of return; and returning texture detail and allowing the shader thread to restart running.

Abstract: Certain aspects direct to systems and methods for performing internal system interface-based communications between Intelligent Platform Management Interface (IPMI) stack and management services in management controllers. The system includes a server management device, which has an IPMI stack and at least one management service module. The management service module, when executed, provides a corresponding management service. In operation, the server management device defines an internal system interface, and configures the internal system interface to establish an inter-process communication (IPC) channel between the IPMI stack and the management service using the internal system interface. Thus, an internal communication between the IPMI stack and the management service may be performed through the IPC channel.

Abstract: A control system for a capacitive touch screen is provided. The control system comprises a touch detecting circuit, touch hard instruction, a storage module and a controller. The touch detecting circuit detects a capacitance variance to generate touch data. The touch hard instruction executes a touch computing function on the touch data. The storage module is connected to the touch detecting circuit and the at least one touch hard instruction, and records the touch data generated by the touch detecting circuit and the touch data computed by the touch hard instruction. The controller is connected to the touch detecting circuit, the at least one touch hard instruction, and the storage module, and assigns at least one touch task of a touch algorithm to the at least one touch hard instruction, so as to execute a corresponding touch computing function of the touch algorithm.

Abstract: An integrated circuit has an image sensor to receive at least one image comprising a plurality of pixels from a camera comprising a lens, a buffer communicatively connected to the image sensor for storing values associated with the plurality of pixels, and a comparator communicately connected to the buffer to locate and identify the iris of a subject, in which locating and identifying the iris of the subject is based on a location of each pixel in a brightest pixel set. A method for locating and identifying an iris in an image includes capturing at least one image of an illuminated subject, determining a brightness value for each of the plurality of pixels, determining a location corresponding to each pixel in a brightest pixel set, and identifying the iris in the at least one image based on the location of each pixel in the brightest pixel set.

Abstract: Certain aspects direct to a computing device, which include a processor, a random access memory (RAM) having a frame buffer, a video controller configured to read video data from the frame buffer, and a non-volatile memory. The non-volatile memory stores an operating system, a media player, and first video data. The processor is configured to load the boot program to the RAM and execute the boot program. The boot program is configured to, when executed at the processor, boot the operating system in a first process or thread of the boot program, and load the media player and execute the media player in a second process or thread separate from a first process or thread. The media player is configured to, when executed by the processor, read the first video data from the non-volatile memory, and write second video data representing the first video data to the frame buffer.

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Abstract: A system and method for propagating scene information to a renderer. In one embodiment, the system includes: (1) an update request receiver operable to receive an update request from the renderer and determine a point from which the renderer is to be updated and (2) an update propagator associated with the update request receiver and operable to employ a graph containing scene information to construct a change list corresponding to the update request and transmit the change list toward the renderer.

Abstract: An image access method applicable to an image access device is provided. The method includes: providing a plurality of codes that respectively represent a plurality of image sources; determining a plurality of sets of access settings according to a pixel format arrangement, each set of access setting corresponding to a code arrangement combination composed of the codes; and sequentially accessing data of the image sources by the image access apparatus according to the code arrangement combinations corresponding to the access settings.

Abstract: There is provided a system for reducing the risk of data corruption occurring in wireless systems, by reducing the risk of an un-expected disconnection occurring between a client device (20; 52, 54, 56) and a host device (20; 50). The client device monitors its own power supply, and when the client device determines that its power supply capacity is almost exhausted, the client device sends a low power notification (5; 55) to the host device. The host device receives the low power notification, and in response closes the wireless connection to the client device, thereby preventing an unexpected disconnection from occurring when the clients power supply is finally exhausted.

Abstract: A system and apparatus is disclosed for sharing a host computer. The system discloses: a set of USB cables; a set of virtualization devices, a set of USB ports on the host computer, an operating system; and a virtualization module. The apparatus discloses: a hub controller; a graphics display module; and an audio controller.

Abstract: According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically rebalancing workloads among the resources, with the goal of removing the current performance bottleneck, while at the same time maintaining power dissipation within a currently allocated power budget. In some embodiments this may be achieved by defining a separate clock domain for each of the plurality of graphics processor resources whose performance may then be rebalanced.

Abstract: Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments, a graphical element in a frame, application, or web page, which is to be presented to a user via a web browser, is rendered either by a first processor or a second processor based on indications of whether the first or the second processor is equipped or configured to provide faster rendering. A rendering engine may utilize either processor based on historical or anticipated rendering performance, and may dynamically switch between the hardware decoder and general purpose processor to achieve rendering time performance improvement. Switches between processors may be limited to a fixed number switches or switching frequency.

Abstract: A graphics card is provided. The graphics card comprises: a Graphics Processing Units (GPU) for data computing; and a wireless controller for wirelessly receiving data from other graphic cards or sending data to the other graphics cards, and communicating with the GPU by bus. The graphic card able provided by the present invention can provide a low-cost solution with more powerful computing capabilities to meet the demands for computing complex problems in the fields of commerce, industry, and science.

Abstract: A method includes providing, in a data processing device including a Central Processing Unit (CPU) and a Graphics Processing Unit (GPU), a capability to interface a microprocessor with the GPU, and communicatively interfacing a sensor with the microprocessor. The method also includes obtaining data related to an operating environment external to the data processing device through the sensor, and determining, through the microprocessor, personalization required of a computing environment of the data processing device with respect to a user thereof based on the data related to the operating environment external to the data processing device. Further, the method includes utilizing the GPU solely to effect the personalization required of the computing environment of the data processing device with respect to the user determined through the microprocessor to reduce power consumption through the data processing device.

Abstract: Methods and systems are provided routing access requests produced by a function to a physical sharing machine on a computer interconnect fabric. Access requests are routed through a switch that includes an NTB, the NTB using an address-lookup table to ensure that access requests made by multiple physical sharing machines are appropriately isolated from one another.

Abstract: Buffer display techniques are described. In one or more implementations, at least part of an off-screen buffer is rasterized by an application to generate an item for display by the computing device. One or more communications are formed that describe the part of the off-screen buffer which contains the item that is to be copied to update an onscreen buffer.

Abstract: A mobile terminal as disclosed and broadly embodied herein may include a 3D display configured to display an object that includes a first and second images and a controller configured to change a magnification of the object that includes a first scaled image and a second scaled image and to correct a binocular disparity between the first and second scaled images. The controller may be configured to determine a binocular disparity between the first and second scaled images, determine whether the binocular disparity is within a prescribed range of disparity, reposition at least one of the first or second magnified images based on the determined binocular disparity, and control the display to display the corrected first and second scaled images.

Abstract: An information processing apparatus includes a first graphics chip, a second graphics chip, a detection unit, and a display unit. The first graphics chip has a first drawing processing capacity. The second graphics chip has a second drawing processing capacity different from the first drawing processing capacity. The detection unit detects a request to change over from an execution of the first graphics chip to an execution of the second graphics chip. The display unit displays a first window prompting to close an application in execution, in a case where the detection unit detects the request to change over from the execution of the first graphics chip to the execution of the second graphics chip.

Abstract: A semiconductor integrated circuit device of the present invention connected to a memory in which display data for a display device is stored, and is adapted to read out the display data from the memory to transfer the same to the display device, the semiconductor integrated circuit device comprising: a display data buffer for holding the display data; a memory controller for prefetching the display data in page-size units of the memory to cause the same to be held by the display data buffer and, upon completing prefetching of one page, closing the page to cause the memory to shift into a power saving mode; and a display device controller for transferring the display data held in the display data buffer to the display device.

Abstract: A display device includes a panel including pixels defined by data lines and gate lines, a housing chassis covering a sidewall and an edge of the panel, a printed circuit board under the panel, the printed circuit board including circuit elements configured to generate at least one of a data signal, a gate signal, and a control signal, a chip on film connecting the printed circuit board to the panel, the chip on film between the housing chassis and the sidewall of the panel, a driver integrated circuit mounted on the chip on film and configured to respond to the control signal and drive at least one of the data signal and the gate signal applied to the data lines and the gate lines, and a connection unit attaching the chip on film to the housing chassis and dissipating heat generated by the driver integrated circuit to the housing chassis.

Abstract: An image-displaying device includes a first storage section, an image data generation section, a timing information acquisition section and a display control section. The image data generation section is configured to output the image data to the first storage section with the image data being composed of a plurality of predetermined data units. The timing information acquisition section is configured to acquire timing information indicative of a timing related to generation and output of the image data to the first storage section with respect to each of the predetermined data units. The display control section is configured to control a display section to read and display an Nth one of the predetermined data units after output of an (N+i)th one of the predetermined data units to the first storage section is completed according to the timing information, where N is a natural number and i is a nonnegative integer.

Abstract: A display driver integrated circuit (DDI) for driving a display of image data on a display panel, an application processor (AP), a system including the DDI and the AP, and methods of operating the same are provided. The application processor includes: a controller configured to obtain a frequency of a data transmission timing control received from a display driver integrated circuit (DDI), and to generate, based on the obtained frequency, a frequency control signal for adjusting a frequency related to an operating clock signal for the DDI; a transmitter configured to transmit the generated frequency control signal to the DDI; and a frequency calculation circuit including: a detector configured to receive the data transmission timing control signal from the DDI, and a frequency calculator configured to calculate a frequency of the received data transmission timing control signal.

Abstract: A method of generating an application programming interface (API) for an electronic circuit. A graphical user interface is displayed through which a user can initiate generation of the API. A component is selected from a plurality of components for placement in said electronic circuit. The component represents an implementable function in the electronic circuit. The component is configured using the graphical user interface. The data pertaining to the selected component and the configuration of the component is stored. The graphical user interface is utilized to access the stored data. The interface is initiated to invoke a processing of said data which causes a generation of the application programming interface. The application interface is for controlling the function of the component in said electronic circuit.

Abstract: A graphics processing circuit includes at least two pipelines operative to process data in a corresponding set of tiles of a repeating tile pattern, a respective one of the at least two pipelines operative to process data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically repeating pattern of square regions. A graphics processing method includes receiving vertex data for a primitive to be rendered; generating pixel data in response to the vertex data; determining the pixels within a set of tiles of a repeating tile pattern to be processed by a corresponding one of at least two graphics pipelines in response to the pixel data, the repeating tile pattern including a horizontally and vertically repeating pattern of square regions; and performing pixel operations on the pixels within the determined set of tiles by the corresponding one of the at least two graphics pipelines.

Abstract: In one embodiment there is provided, a display driver system, comprising, at least one display driver; a magnetic random access memory (MRAM) macro; and a display driver interface coupling the MRAM macro and the at least one display driver.

Abstract: A video-processing chip capable of saving power is disclosed. The video-processing chip includes a microprocessor, a scalar, a first memory, and a second memory. The microprocessor is used for executing program codes. The scalar is used for adjusting a size of a received image. The first memory is coupled to the microprocessor and to the scalar for providing memory space to the scalar for image processing. The second memory is coupled to the microprocessor for storing the program codes of the microprocessor for controlling a power switch. Wherein a size of the first memory is greater than a size of the second memory.

Abstract: In at least some embodiments, an apparatus includes a hardware accelerator subsystem with a pipeline. The hardware accelerator subsystem is configured to perform error recovery operations in response to a bit stream error. The error recovery operations comprise a pipe-down process to completely decode a data block that is already in the pipeline, an overwrite process to overwrite commands in the hardware accelerator subsystem with null operations (NOPs) once the pipe-down process is complete, and a pipe-up process to restart decoding operations of the pipeline at a next synchronization point.

Abstract: A processing system is disclosed. The processing system comprises a first integrated circuit. The first integrated circuit includes a processor core, a display interface and memory controller coupled to a first bus interface. The display interface is adapted to display graphical information generated by a graphics engine. A graphics engine is not on the first integrated circuit. The processing system includes a second bus interface for allowing communication with the first integrated circuit via the first bus interface. The second bus interface is adapted to allow for communication to a graphics engine.

Abstract: To control multiple electronic circuits organized in a series configuration, this document introduces a single-wire power, control, and feedback system. Specifically, individually controlled electronic circuits are arranged in a series configuration that is driven by a control unit located at the head of the series. The head-end control unit provides both electrical power and control signals down a single wire to drive all of the electronic circuits in the series in a manner that allows each electronic circuit to periodically draw power from the single wire and receive control information. Each electronic circuit in the series may communicate back to the head-end control unit by drawing power or not during a specified time slot.

Abstract: A method of reading data for a display drive IC of a panel is provided. The method includes receiving a write format and at least one image packet, generating a synchronization signal according to the write format, and reading data of the at least one image packet according to the synchronization signal such that the panel uses a video mode to display the data of the at least one image packet.

Abstract: A method and apparatus for configuring multiple displays includes determining, in connection with an image or portion thereof to be displayed on the multiple displays at the same time, whether received display preferences can be fulfilled in observance of: configuration properties of the multiple displays and configuration properties of a computing system, such as the capabilities of display controllers. The method and apparatus also determine whether a current configuration of the multiple displays to the computing system can be reconfigured such that the display preferences of the multiple displays can be fulfilled at the same time while maintaining effective configuration of a current configuration when the display preferences cannot be fulfilled, and display the images of a portion thereof on the multiple displays at the same time.

Abstract: Methods and apparatus for adjusting the operation of a display device so as to be at least within prescribed form factor or other constraints. In one embodiment of the invention, various operational parameters for a display element are adjusted based on considerations specific to high density form factor constraints. For example, in one such device, a Low Power DisplayPort (LPDP) device having a LPDP source and sink adjust the data rate of the visual data to minimize power consumption while still properly supporting display panel resolutions. In some embodiments, the LPDP source and sink may adjust the transceiver voltages to minimize power consumption. In an alternate embodiment, an LPDP device adjusts data rates to minimize the effects of platform noise. In another aspect of the invention, various display elements of a device coordinate quiescent (“quiet”) mode operation during periods of inactivity.

Abstract: To realize effective load distribution and improve the performance in image formation processing, an image processing apparatus includes a first image processing unit configured to perform image processing on a drawing area, a second image processing unit configured to be differentiated from the first image processing unit, a load analysis unit configured to analyze a composition processing load of an object in the drawing area, a rotational angle analysis unit configured to analyze a rotational angle of the object in the drawing area, and a load distribution determination unit configured to determine whether to distribute a part of image formation processing to be applied on the drawing area from the first image processing unit to the second image processing unit based on the analyzed composition processing load of the object and the analyzed rotational angle of the object.

Abstract: To power and control multiple different electronic circuit nodes, this document introduces a single-wire multiple-circuit power and control system. Specifically, individually controlled circuit node units are arranged in a series configuration that is driven by a power and control unit located at the head of the series. Each of the individually controlled circuit node units may comprise more than one output circuit that is also individually controllable. The head-end power and control unit provides both electrical power and control signals down a single wire to drive all of the individual circuit node units in the series in a manner that allows each individual circuit node unit to be controlled individually or in assigned groups.

Abstract: An apparatus to provide a fall-back procedure for a PRC imaging device is described. The apparatus includes a PRC controller, a system resource monitor, and a PRC setting calculator. The PRC controller outputs a stream of images at an adjustable temporal rate. The adjustable temporal rate is constrained within a range defined by a first predetermined rate and a second predetermined rate. The system resource monitor obtains a measurement of system resource utilization. The PRC setting calculator determines a setting for the PRC controller in response to the measurement of system resource utilization. Additionally, the PRC controller determines a value for the adjustable temporal rate in response to the setting.

Abstract: A system on chip (SoC) and a method of operating the same are provided. The SoC includes a central processing unit (CPU) controlling a memory operation and a display operation on a current frame of an image based on generation of the image and an interrupt signal; an image generator requesting data of the current frame from a memory according to control of the CPU; a UD unit determining whether the current frame is updated, detecting whether an update region is a partial frame based on virtual addresses included in a request of the image generator, and outputting the interrupt signal corresponding to the update region to the CPU; a memory controller storing the update region in the memory according to the control of the CPU; and a display controller accessing the memory and outputting the update region to a display device according to the control of the CPU.

Abstract: Methods and systems for processing image data on a per tile basis in an image sensor pipeline (ISP) are disclosed and may include communicating, to one or more processing modules via control logic circuits integrated in the ISP, corresponding configuration parameters that are associated with each of a plurality of data tiles comprising an image. The ISP may be integrated in a video processing core. The plurality of data tiles may vary in size. A processing complete signal may be communicated to the control logic circuits when the processing of each of the data tiles is complete prior to configuring a subsequent processing module. The processing may comprise one or more of: lens shading correction, statistics, distortion correction, demosaicing, denoising, defective pixel correction, color correction, and resizing. Each of the data tiles may overlap with adjacent data tiles, and at least a portion of them may be processed concurrently.

Abstract: A display apparatus includes pixels connected to gate lines and data lines, a gate driver configure to drive the gate lines, a data driver including a plurality of data driving parts configured to drive the data lines. The control board includes a processor that outputs an image signal and a control signal and a timing controller that outputs a first control signal to control the gate driver and a second control signal and a data signal to control the data driver in response to the image signal and the control signal.

Abstract: A graphics processing unit (GPU) efficiently performs 3-dimensional (3-D) clipping using processing units used for other graphics functions. The GPU includes first and second hardware units and at least one buffer. The first hardware unit performs 3-D clipping of primitives using a first processing unit used for a first graphics function, e.g., an ALU used for triangle setup, depth gradient setup, etc. The first hardware unit may perform 3-D clipping by (a) computing clip codes for each vertex of each primitive, (b) determining whether to pass, discard or clip each primitive based on the clip codes for all vertices of the primitive, and (c) clipping each primitive to be clipped against clipping planes. The second hardware unit computes attribute component values for new vertices resulting from the 3-D clipping, e.g., using an ALU used for attribute gradient setup, attribute interpolation, etc. The buffer(s) store intermediate results of the 3-D clipping.

Abstract: A system-on-chip (SoC), measures the workload of a graphics processing unit (GPU), compares the frame process speed of the GPU with the frame rate of a display device, and adjusts the operating frequency of the GPU based on the comparison result and the workload of the GPU.

Abstract: Techniques are disclosed for setting a scan rate for an electronic device based on interaction with the user and/or application type.

Abstract: Methods, chips, systems, computer program products and data structures are described for conducting modification of color video signals from a first color format associated with an originating format to a second format compatible with a display media of a display device.

Abstract: A silicon chip of a monolithic construction for use in implementing a multiple core graphics processing and display subsystem in a computing system having a CPU, a system memory, an operating system (OS), a CPU bus, and a display device with a display surface. The computing system supports (i) one or more software applications for issuing graphics commands, (ii) one or more graphics libraries for storing data used to implement said graphics commands. The silicon chip comprises multiple graphic pipeline cores, a partial frame buffer for buffering pixels corresponding to image fragments, a routing center, control unit, and a display interface, for displaying composited images on the display surface of the computing system.

Abstract: The display color of, for example, a button image responsive to a command input into a facility operation display device is controlled by a palette value having a smaller number of bits than an RGB value. When the display color of the button image is changed, the palette value of a drawing object associated with the button image is changed to an RGB value. This eliminates the necessity of incorporating, for example, a high-performance CPU as a central arithmetic unit. In addition, it is not necessary to pre-store images corresponding to several kinds of display colors specified by RGB values, to thereby eliminates the necessity of incorporating, for example, a high-capacity storage medium in the facility operation display device. Accordingly, the device cost can be reduced.

Abstract: A first GPU is provided with a digital video output terminal (Vout terminal) for connection to an external source. A digital video signal output from the Vout terminal is provided to a display device via a HDMI. The first GPU and a second GPU are connected to each other via a data bus for bidirectional data exchange. The second GPU applies a predetermined rendering process on data provided from the first GPU via a data input and output interface. The rendered data is returned to the first GPU via the data input and output interface. The first GPU processes the data returned from the second GPU as necessary and outputs a digital video signal via the Vout terminal and the HDMI.

Abstract: A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.

Abstract: A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by b*x columns of memory locations. Each memory location is adapted to store n-bit image data for one of the pixels of the display device. A memory location remapping circuit is adapted to map image data stored in the b*x columns of memory locations in the memory device to the a*x columns of the display device.

Abstract: Systems and methods for layering multiple graphics planes on top of a compressed video signal are disclosed herein. A processed video stream is received from a video processing path, wherein the processed video stream comprises a stream of video macroblocks. A composite graphics plane is received from a graphics processing path, wherein the composite graphics plane comprises a set of graphics macroblocks. The composite graphics plane comprises a plurality of layered graphics planes. The composite graphics plane is layered on top of the processed video stream to generate an output video stream. Layering comprises blending a video macroblock from the stream of video macroblocks with a graphics macroblock from the set of graphics macroblocks. By layering one macroblock at time, graphics overlay can occur in real time or faster than real time as the compressed input stream is received.

Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.

Abstract: The present invention provides an apparatus that includes a network-enabled graphics processing unit. In one embodiment, the apparatus includes integrated circuit that includes a graphics processing element, a media fragmentation engine, and a network interface controller for conveying packets to or from the integrated circuit. The media fragmentation engine translates between a packet format used by the network interface and a graphics format used by the graphics processing element.