Abstract: Systems and methods are disclosures for scheduling code in a multiprocessor system. Code is portioned into code blocks by a compiler. The compiler schedules execution of code blocks in nodes. The nodes are connected in a directed acyclical graph with a top node, terminal node and a plurality of intermediate nodes. Execution of the top node is initiated by the compiler. After executing at least one instance of the top node, an instruction in the code block indicates to the scheduler to initiate at least one intermediary node. The scheduler schedules a thread for execution of the intermediary node. The data for the nodes resides in a plurality of data buffers; the index to the data buffer is stored in a command buffer.

Abstract: Systems, apparatuses, and methods for using a scoreboard to track updates to configuration state registers are disclosed. A system includes one or more processing nodes, one or more memory devices, a plurality of configuration state registers, and a communication fabric coupled to the processing unit(s) and memory device(s). The system uses a scoreboard to track updates to the configuration state registers during run-time. Prior to a node going into a power-gated state, the system stores only those configuration state registers that have changed. This reduces the amount of data written to memory on each transition into power-gated state, and increases the amount of time the node can spend in the power-gated state. Also, configuration state registers are grouped together to match the memory access granularity, and each group of configuration state registers has a corresponding scoreboard entry.

Abstract: Writing time is shortened even in a memory writing time for each access unit is not constant. A writing time prediction information holding unit holds writing time prediction information for predicting the writing time in a plurality of memory modules for each of a plurality of memory modules. A request selecting unit preferentially selects a write request of which longer writing time is predicted out of a plurality of write requests requiring writing in each of a plurality of memory modules on the basis of the writing time prediction information.

Abstract: Provided are methods and systems for optimizing storage performance on a particular user system based on modeling of the input/output (I/O) primarily encountered by the particular user system. An I/O pattern representative of the primary usage scenario on the user system is obtained and then modeled. The modeling identifies the storage operations involved in the primary storage usage scenario I/O and adjusts values for one or more configurable settings of the storage operations. The adjusted values modify the behavior of the storage operations for prioritized reading, writing, and caching of the primary storage usage scenario I/O over reading, writing, and caching of I/O unrelated to the primary storage usage scenario.

Abstract: Based on a detected data transfer instruction, a computing device within a dispersed storage network (DSN) determines a data transfer synchronization protocol that substantially maintains synchronization of at least the write threshold number of first associated slices (e.g., a first row of encoded data slices) to be transferred from the first set of storage units (SUs) to a second set of SUs based on a substantially same first transfer rate and substantially maintains synchronization of at least the write threshold number of second associated slices (e.g., a second row of encoded data slices) to be transferred from the first set of SUs to the second set of SUs based on a substantially same second transfer rate. The computing device then executes the data transfer synchronization protocol to perform substantially synchronized transfer of respective sets of the plurality of sets of encoded data slices from the first set of SUs to the second set of SUs.

Abstract: A display device communicates using a clock-embedded host interface. The display device includes a panel driving circuit and a host. The panel driving circuit includes at least one timing controller embedded driver (TED), and drives a display panel. The host at least one of transmits and receives video data, additional data, and a hot plug detect (HPD) signal to or from the at least one TED through one port using a clock-embedded host interface.

Abstract: A method of controlling a memory device includes receiving an address value that indicates a range of addresses within the memory device, each address within the range of addresses corresponding to storage locations within each of two distinct storage dice within the memory device. The address value is stored within a programmable register within the memory device.

Abstract: A method of operation in a non-volatile memory system includes starting execution of a first memory operation from a first queue and in conjunction with starting a first timer, set to expire after a first predetermined time interval. The method further includes, in accordance with a determination that the first timer has expired, determining whether a second queue contains at least one memory operation for execution, and if so, suspending the first memory operation, executing a second memory operation from the second queue, and after completing execution of the second memory operation from the second queue, performing one or more subsequent operations (e.g., resuming execution of the first memory operation and restarting the first timer). In addition, the method includes, when the second queue does not contain at least one memory operation for execution, restarting the first timer, and continuing execution of the first memory operation from the first queue.

Abstract: It is determined whether a packet is a multicast packet, and an index to a database is selected from i) a first candidate index determined based on header information of the packet, or ii) a second candidate index determined based on the header information, based on whether the packet is a multicast packet. Information is retrieved from the database using the index, and the header information is compared with information retrieved from the database. Further information retrieved from the database is used to determine one or more ports via which the packet should be transmitted when the header information matches the information retrieved from the database.

Abstract: A packet is received via a port of the network device, and a database lookup is performed using header information of the packet. A priority associated with the packet is determined, and it is determined whether the priority is associated with a particular communication protocol that provides guaranteed delivery, defined latency, and/or defined throughput. When it is determined that the priority is associated with the particular communication protocol, i) it is determined, based on the database lookup, whether a destination address (DA) of the packet is associated with the particular communication protocol, and ii) when it is determined that the DA of the packet is associated with the particular communication protocol, the packet is prevented from egressing from ports of the network device that are operating according to the particular communication protocol with a frame priority indicator corresponding to a value reserved for the particular communication protocol.

Abstract: A packet is received via a first port of the network device, and a priority associated with the packet is determined. A first queue indicator from a plurality of queue indicators is determined based on the priority associated with the packet, wherein the plurality of queue indicators correspond to a plurality of priorities for transmitting the packet. A second queue indicator from the plurality of queue indicators is determined based on the priority associated with the packet. A second port that is to transmit the packet is determined, and a configuration of the second port is determined. One of the first queue indicator or the second queue indicator is selected based on the configuration of the second port, and a queue is selected from a plurality of queues associated with the second port based on the selected one of the first queue indicator or the second queue indicator, wherein the plurality of queues correspond to different priorities.

Abstract: It is determined whether a packet is a management-type packet. When it is determined that the packet is a management-type packet, a queue is selected from a plurality of queues corresponding to different priorities, wherein the selected queue corresponds to a defined throughput and/or a defined latency. The packet is enqueued in the selected queue. The packet is transmitted via a port of the network device.

Abstract: A method of capturing the state of a target program that is running within the environment of an operating system is provided. The method includes identifying threads associated with the target program, suspending threads associated with the target program, preserving data characterizing the threads, and preserving data accessible by the threads when in operation. A method of changing the state of a target program that is running within the environment of an operating system is also provided. This method includes identifying threads associated with the target program, suspending threads associated with the target program, replacing data characterizing the threads with previously preserved data, and replacing data accessible by the threads when in operation with previously preserved data. In either case, the threads are then resumed to allow the target program to continue operation.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for managing a journal. A method may include reordering storage commands based on different storage volumes associated with the storage commands. A method may include reordering storage commands based on different snapshots associated with the storage commands. A method may include adjusting a frequency of writing data from a write buffer based on a rate of write requests. A method may include adjusting a ratio of storage capacity for storing mirrored write data to storage capacity for storing non-mirrored read data.

Abstract: In general, aspects of this disclosure describe example techniques for efficient storage of data of various data types for graphics processing. In some examples, a processing unit may assign first and second contiguous range of addresses for a first and second data type, respectively. The processing unit may store at least one of graphics data of the first or second data type or addresses of the graphics data of the first or second data type within blocks whose addresses are within the first and second contiguous range of addresses, respectively. The processing unit may store, in cache lines of a cache, the graphics data of the first data type, and the graphics data of the second data type.

Abstract: A system and method is disclosed for adapting a continuous presence videoconferencing layout according to interactions between conferees. Using regions of interest found in video images, the arrangement of images of conferees may be dynamically arranged as displayed by endpoints. Arrangements may be responsive to various metrics, including the position of conferees in a room and dominant conferees in the videoconference. Video images may be manipulated as part of the arrangement, including cropping and mirroring the video image. As interactions between conferees change, the layout may be automatically rearranged responsive to the changed interactions.

Abstract: An image data forming apparatus includes a storage unit storing original image data, a buffer unit temporarily storing a part of the original image data, an output unit, a priority setting unit, a control unit, and an analysis unit. The output unit forms image data from the original image data, outputs the image data, and uses, if data needed to form the image data is stored in the buffer unit, the stored needed data. The priority setting unit divides the original image data into a blocks and set priorities for blocks. The control unit performs control so that image data of those blocks having a high priority is stored in the buffer unit by priority. The analysis unit analyzes, if the original image data is accompanied by data of annotations, position information about the annotations. The priority setting unit sets the priorities based on an analysis result.

Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.

Abstract: A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode.

Abstract: According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.

Abstract: In a graphics processing device, a plurality of processors write fragment shading results for order-dependent data to a buffer, according to the order in which the data is received. Fragment shading results for order-neutral data is written to the buffer one batch at a time. The order-dependent data comprises spatially overlapping data. Order-neutral data may not overlap. A scheduler controls the order of reception of one batch of data at a time by the processors. The order for receiving the order-dependent data may be determined. The plurality of processors may process the data in parallel. A writing order for writing results to a buffer from the processing in parallel, may be enforced. A portion of the processors may be instructed to wait before writing results to the buffer in a specified order. Processors signal when writing results to the buffer is complete.

Abstract: The present invention relates to a mobile terminal displaying an instant message and a control method of the same. A mobile terminal according to an aspect of the invention may include: a wireless communication unit sending or receiving an instant message; a display unit including a first region and a second region and displaying the instant message sent or received by the wireless communication unit on the first region; and a controller displaying information corresponding to at least one object included in the instant message on the second region.

Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode.

Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.

Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced page table entries are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can redirect one or more pending page table entry fetch requests to an appropriate coalesced page table entry.

Abstract: The method includes the following steps: monitoring an actual value of a relevant parameter of a display bandwidth of data to be output by the memory; comparing the actual value of the relevant parameter with a threshold to determine whether the actual display bandwidth meets predetermined requirements; and selecting an access arbitration mode for the memory according to whether the predetermined requirements are met. The access controller includes: a monitoring and comparing unit, adapted to monitor an actual value of a relevant parameter of a display bandwidth of data to be output by the memory and compare the actual value of the relevant parameter with a threshold to determine whether the actual display bandwidth meets predetermined requirements; and an arbitration adjusting unit, adapted to select an access arbitration mode for the memory according to whether the predetermined requirements are met.

Abstract: In a communication device with a graphics processor, a graphics asset can be shared with two or more applications. The graphics asset can include a bitmap of a digital image. An asset server can host a texture corresponding to the graphics asset and can share the texture with the graphics processor. The asset server can host multiple textures and can share those textures with the graphics processor for rendering. The graphics processor can use the shared texture to render an instance of the graphics asset for each of the two or more applications. The texture can be generated by copying information about the graphics asset into the asset server.

Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.

Abstract: A method and apparatus for controlling writing of data to a graphic memory is provided. In the method and apparatus, a plurality of consecutively input data pieces are controlled to be not consecutively written to the same memory area in terms of time or space.

Abstract: An image processing apparatus comprises a plurality of processing blocks connected in series, and each respective processing block comprises a processor. In each respective processing block, the processor employs data input into that processing block to perform an image process upon the data. Also, each processing block performs a process upon the processor in response to a command input into the processing block. Each processing block causes an output corresponding to the command that is input after the data to wait until an output of the processor that employed the data input into the processing block prior to the command to perform the process is finished, such that the output of the processor that employed the data to perform the image processing and the output that corresponds to the command is outputted from the processing block in an order whereby the data and the command are input.

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract: A display control device for controlling a display panel includes a contents frame rate detector detecting a contents frame rate of an input image data and outputting a repetitive frame number dependent from a display frame rate of the display panel and the detected contents frame rate; a frame memory for storing a level data of a previous frame; and an emulated level generator in communication with the contents frame rate detector and the frame memory. An output level data to the display panel is generated according to the repetitive frame number from the contents frame rate detector, the previous level data from the frame memory and an input level data of the input image data.

Abstract: An image-processor includes an acquiring unit and a correcting unit. The acquiring unit acquires image data and ambient light data indicating a degree of a first color temperature with respect to a second color temperature. The first color temperature represents a color temperature for a first ambient light. The second color temperature represents a color temperature for a second ambient light. A first image, which corresponds to the image data, is perceived in the first ambient light as an image having one color appearance. The first image is perceived in the second ambient light as an image having another color appearance. The correcting unit corrects the image data such that a color appearance of the first image under the first ambient light are reproduced under the second ambient light.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: A processing system includes a shared resource, an arbitration module, and a requesting device for issuing requests to the arbitration module to access the shared resource to perform transactions on the shared resource. The arbitration module grants access to the requesting device for a fixed time duration. The fixed time duration comprises one of a plurality of time durations including a first and a second time duration; the second longer than the first. The requesting device prioritizes performance of the transactions on the shared resource based upon the fixed time duration and types of transactions to be performed. Transaction type comprises one of a plurality of types including a first type that requires a time duration that can be performed within the first time duration and a second type that requires a time duration that exceeds the first time duration but can be performed within the second time duration.

Abstract: A programmable data processing circuit has a memory for storing pixel values, or more generally data values as a function of position in a signal. The programmable data processing circuit supports instructions that include an indication of a selected parameter value set that indicates how a plurality of data values must be arranged for parallel output from a memory. Instructions that indicate different parameter value sets can be executed intermixed with one another. The programmable data processing circuit responds to instructions of this type by retrieving the selected parameter value sets from a parameter storage circuit (246), and controlling a switching circuit (22) between a memory port (21) of a memory circuit (20) and a data port (26) at least partly dependent on the selected parameter value set.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: Graphics display adapters for driving multiple display monitors have become very popular. Graphics display adapters that drive multiple monitors can be used to provide terminal services to multiple independent terminals or be used to provide multiple displays to a single user. Generating video signals for multiple display systems puts a heavy burden on the video memory system since multiple different video signal generators may read from associated frame buffers in a shared video memory system. In one disclosed embodiment, a plurality of video memory read triggers are provided wherein at least two of which are staggered to reduce the load on the video memory system. In response to each read trigger, display data is read from a frame buffer to an associated video signal generation circuit. Each video signal generation circuit then provides a display signal to an associated display screen in a multi-screen environment.

Abstract: A system on chip (Soc) includes a system bus, a plurality of sub-systems, an image processing logic block, an image memory interface and an image processing memory block. The sub-systems are respectively connected to the system bus. The image processing logic block is connected to the system bus. The image processing logic block performs an image processing. The image processing logic block is included in a first power domain. The image memory interface is connected to the system bus and the image processing logic block. The image processing memory block is connected to the image memory interface. The image processing memory block is used for the image processing. The image memory interface and the image processing memory block are included in a second power domain different from the first power domain.

Abstract: Systems and methods for determining a compression tag state prior to memory client arbitration may reduce the latency for memory accesses. A compression tag is associated with each portion of a surface stored in memory and indicates whether or not the data stored in each portion is compressed or not. A client uses the compression tags to construct memory access requests and the size of each request is based on whether or not the portion of the surface to be accessed is compressed or not. When multiple clients access the same surface the compression tag reads are interlocked with the pending memory access requests to ensure that the compression tags provided to each client are accurate. This mechanism allows for memory bandwidth optimizations including reordering memory access requests for efficient access.

Abstract: A display control circuit capable of performing arbitration with the use of a simple configuration. The display control circuit exchanges, with a plurality of masters, attribute information defining conditions for displaying video on a display, and includes a memory for storing the attribute information, a plurality of channels associated with the respective masters for accepting, from the masters, access requests to access the memory, and an arbitration controller configured by hardware. The arbitration controller arbitrates the access requests accepted via the respective channels and permits a selected one of the access requests to access the memory.

Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. A memory controller performs a wide range of memory control related functions including arbitrating between various competing resources seeking access to main memory, handling memory latency and bandwidth requirements of the resources requesting memory access, buffering writes to reduce bus turn around, refreshing main memory, and protecting main memory using programmable registers. The memory controller minimizes memory read/write switching using a “global” write queue which queues write requests from various diverse competing resources. In this fashion, multiple competing resources for memory writes are combined into one resource from which write requests are obtained.

Abstract: Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.

Abstract: A graphics system stores graphics data in a dynamic-random-access memory (DRAM) and in a faster static random-access memory (SRAM). A refresh controller reads pixel data from a frame buffer that is usually in the faster SRAM, while one or more video overlay engines read graphics objects from the DRAM. However, large frame buffers may be partially stored in the DRAM. Some of the graphics data read by the video overlay engine may reside in the SRAM. A dual-layer arbiter receives requests from the refresh controller and the overlay engines for access to the SRAM and DRAM. When two requestors request the same memory device, the dual-layer arbiter arbitrates access. However, often the requests are to different memory devices and the dual-layer arbiter can pass the requests through without delay, since separate buses to the DRAM and SRAM can be used simultaneously.