Abstract: A system and method for generating a graphical image on a display is disclosed. The graphical image is generated from data describing at least one object. The display includes a plurality of positions. Each of the plurality of positions has an area. The system and method include determining if a portion of the at least one object intersects a current position of the plurality of positions and providing an output if the portion intersects the current position. The method and system further include providing a mask for the portion if it is determined that the portion intersects the current position. The mask indicates an extent to which the at least one portion occupies the area of current position. The method and system further include utilizing the mask to provide antialiasing. The method and system also include repeating the determining, one mask providing, and utilizing steps for each of the plurality of positions.

Abstract: A color display driving apparatus that simultaneously on-screen displays an RGB format color image and a YUV format color image on the same color display unit. A first memory stores YUV data, and a YUV-RGB converter converts YUV data read from the first memory to RGB data. A second memory stores RGB data. An on-screen-display (OSD) controller writes the YUV data and the RGB data in the first and second memories, respectively, mixes the RGB data converted from the YUV data stored in the first memory by the YUV-RGB converter with the RGB data read from in the second memory, and on-screen displays the mixed data.

Abstract: System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and pixel types. Memory space allocated may be of a predetermined size for a thread type. Memory locations within a first memory space may be interleaved with memory locations within a second memory space.

Abstract: A system and method for managing memory data is provided. Data stored within a main memory may be requested by multiple requesters that may include one or more cache memories. When the data is provided by the main memory to a requester, it will be provided in a state that is based on the way the data was recently used by the requesters. For example, if a pattern of read-only usage has been established for the data, the data will be returned to a requester in a shared state. If data that was provided in a shared state must be updated such that the requester is required return to main memory to obtain read/write privileges, the main memory will thereafter provide the data in an exclusive state that allows write operations to be completed. This will continue until a pattern of read-only usage is again established.

Abstract: The present invention provides data processing technology for making two or more processing units cooperate with one another such that output data from respective groups of processing units (GSM) are merged by a respective sub-MG (merger), data from the sub-MGs are merged by a main MG, and the merged output data are displayed on a display unit. Each GSM initiates drawing processing assigned thereto in response to the reception of a drawing enable signal and, after execution of the processing, outputs a drawing end signal. The GSMs to which the drawing enable signal is to be sent, and the GSMs from which the drawing end signal is to be received, are set for each application. A main SYNC sends the drawing enable signal to corresponding GSMs in the order of setting for an application in response to the reception of a processing request from the application, while it receives the drawing end signal from the corresponding GSMs so that the processing results of the GSMs will be displayed on the display unit.

Abstract: A liquid crystal display device employing an overshooting driving method is provided which is capable of reducing memory capacity of a frame memory used to delay input data. The above liquid crystal display device for displaying an image using a liquid crystal panel includes a data converting table to generate output gray-scale data obtained by thinning out input gray-scale data to reduce a number of bits of input gray-scale data, a frame memory to generate second input gray-scale data by delaying output gray-scale data in a data converting table by one frame image display period in a liquid crystal panel and a look-up table to generate an overshooting gray-scale output being in advance stored according to a relation in size between the first input gray-scale data and the second input gray-scale data, wherein image display is performed by an overshooting gray-scale output in a liquid crystal panel.

Abstract: An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.

Abstract: According to one embodiment a chipset is disclosed. The chipset includes a graphics accelerator, a memory controller and a queue mechanism. The queue mechanism includes a first functional unit block (FUB) coupled to the graphics accelerator, and a second FUB coupled to the memory controller.

Abstract: A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first signals that are indicative of an address associated with a write command, decodes the address to provide column select signals that are indicative of a column address in the memory cell array, and uses the column address to perform a column redundancy check. The data communication circuit latches data signals that are associated with the write command in response to a data strobe signal. The control circuit causes the addressing circuit to perform the column redundancy check during a delay to accommodate variations in the timing of the data strobe signal and begins providing the column select signals to the memory cell array after performing the column redundancy check. The memory device may be a double data rate (DDR) synchronous dynamic random access memory (SDRAM), for example.

Abstract: In an embedded system, for instance in a household appliance, in addition to the usual embedded microprocessor/microcontroller there is provided another processor which actually executes a user interface HTML document for accepting user input, for instance from a keypad and controlling the display device, for instance an LCD. The embedded microprocessor hosts the user interface document, responds to requests from the other processor, keeps track of changes in variables shared with the other processor, and executes the control device functionality. The other processor renders the graphical user interface to the display and interacts with the user by executing local functions to operate on the memory and i/o resources of the embedded processor as described by the user interface document served to it.

Abstract: An image producing device includes two or more vector processors for conducting geometry processing for expressing the respective images in parallel to produce graphic element lists, a graphic processor for conducting graphic processing on the basis of the graphic element lists, and an arbitrator. The graphic processor includes two buffers for storing graphic contexts corresponding to the graphic element lists together with identification information on the graphic contexts, and a unit for reading a specific graphic context from the buffers upon inputting the graphic element lists from the arbitrator to conduct the graphic processing. Each of the vector processors produces the graphic element lists having, as their contents, the identification information of the graphic context specified by the geometry processing assigned to each of the vector processors.

Abstract: Method for controlling a memory in a digital system, including the steps of (a) dividing the memory into a plurality of fixed sized memory blocks, (b) defining at least one of the memory blocks as a compression/decompression region, (c) assigning compression priorities to rest of the memory blocks except the memory blocks defined as the compression/decompression region, and (d) making the memory blocks to deal with an external data received according to an external command, and carrying out compression/decompression of data required in the dealing with the external data at the compression/decompression region according to the compression priorities.

Abstract: A method for optimizing a cache memory used for multitexturing in a graphics system is implemented. The graphics system comprises a texture memory, which stores texture data comprised in texture maps, coupled to a texture cache memory. Active texture maps for an individual primitive, for example a triangle, are identified, and the texture cache memory is divided into partitions. In one embodiment, the number of texture cache memory partitions equals the number of active texture maps. Each texture cache memory partition corresponds to a respective single active texture map, and is operated as a direct mapped cache for its corresponding respective single active texture map. In one embodiment, each texture cache memory partition is further operated as an associative cache for the texture data comprised in the partition's corresponding respective single active texture map. The cache memory is dynamically re-configured for each primitive.

Abstract: A FIFO section having a FIFO memory is provided between a memory control section and a CPU_I/F section in a path through which image data outputted from a CPU is written into the video memory. Data necessary for writing the image data is stored into the FIFO section and, based on the data stored in the FIFO section, the image data is stored into the video memory under the control of the memory control section. With this configuration, the CPU can output the image data without a wait time until the FIFO memory becomes full, and thus there is provided a liquid crystal display control device that does not lower the operation efficiency of the CPU.

Abstract: A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm.

Abstract: Disclosed are methods and systems for interfaces between video applications and display screens that allow applications to intelligently use display resources of their host device without tying themselves too closely to operational particulars of that host. A graphics arbiter provides display environment information to the video applications and accesses the applications' output to efficiently present that output to the display screen, possibly transforming the output or allowing another application to transform it in the process. The graphics arbiter tells applications the estimated time when the next frame will be displayed on the screen. Applications tailor their output to the estimated display time, thus improving output quality while decreasing resource waste by avoiding the production of “extra” frames. The graphics arbiter tells an application when its output is fully or partially occluded so that the application need not expend resources to draw portions of frames that are not visible.

Abstract: A communication method apparatus are disclosed, including a common bus; a plurality of multiplexers that communicate with the common bus; a plurality of memories, each in communication with a separate one of the plurality of multiplexers and each having a different storage capacity, that together form a hierarchical storage structure; a bus arbiter that controls access to the common bus; a first interface that communicates information with the common bus; and a second interface that communicates information with the common bus.

Abstract: A graphics system comprising a scheduling network, a sample buffer and a plurality of filtering units. The sample buffer is configured to store sample generated by a rendering engine. The plurality of filtering units are coupled in a linear series. Each filtering unit of the linear series is configured to send a request for a scanline of sample bins to a first filtering unit of the linear series. The first filtering unit is configured to service the scanline requests by sending burst requests to a scheduling network and coordinating the flow of samples forming the bursts from the sample buffer to the filtering units.

Abstract: A graphics system stores graphics data in a dynamic-random-access memory (DRAM) and in a faster static random-access memory (SRAM). A refresh controller reads pixel data from a frame buffer that is usually in the faster SRAM, while one or more video overlay engines read graphics objects from the DRAM. However, large frame buffers may be partially stored in the DRAM. Some of the graphics data read by the video overlay engine may reside in the SRAM. A dual-layer arbiter receives requests from the refresh controller and the overlay engines for access to the SRAM and DRAM. When two requestors request the same memory device, the dual-layer arbiter arbitrates access. However, often the requests are to different memory devices and the dual-layer arbiter can pass the requests through without delay, since separate buses to the DRAM and SRAM can be used simultaneously.

Abstract: A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU throttle control signal and monitoring CPU power and performance states, and making decisions based on the monitored parameters. Bus master memory access break events and memory read and write accesses are also monitored as part of the arbitration process in accordance with certain embodiments of the present invention. An arbitration (ARB) module performs the dynamic arbitration. A CPU throttle control module generates the CPU throttle control signal, indicating when the CPU is idle, and also monitors and outputs the CPU power and performance states. A memory controller (MC) module controls accesses to the memory subsystem based on, at least in part, the dynamic arbitration performed by the dynamic arbitration module.

Abstract: A system and method for assigning operations to multiple pipelines in a graphics system is disclosed. The graphics system may include an arbitration unit coupled to a plurality of calculation pipelines. The arbitration unit is operable to provide graphics operations to selected ones of the calculation pipelines. Each of the calculation pipelines is operable to perform a graphics operation. Each of the calculation pipelines may include digital logic and/or a processing element for performing the graphics operations. An operation may be assigned to a pipeline if the pipeline is performing a low latency operation. A low latency operation may comprise an operation that is performed by one of the calculation pipelines in less time than a pre-determined number of clock cycles.

Abstract: A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of Accelerated Graphics Port (AGP) buses. Each of the plurality of AGP buses have the same logical bus number. The core logic chip set has an arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each AGP device connected to the plurality of AGP physical buses. Each of the plurality of AGP buses has its own read and write queues to provide transaction concurrency of AGP devices on different ones of the plurality of AGP buses when the transaction addresses are not the same or are M byte aligned. Upper and lower memory address range registers store upper and lower memory addresses associated with each AGP device. Whenever a transaction occurs, the transaction address is compared with the stored range of memory addresses. If a match between addresses is found then strong ordering is used. If no match is found then weak ordering may be used to improve transaction latency times.

Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.

Abstract: Disclosed are methods and systems for interfaces between video applications and display screens that allow applications to intelligently use display resources of their host device without tying themselves too closely to operational particulars of that host. Video applications (1) receive information about the display environment from a graphics arbiter, (2) use that information to prepare their video output, and (3) send their output to the graphics arbiter which efficiently presents that output to the display screen. The graphics arbiter tells applications the estimated time when the next frame will be displayed on the screen. Applications tailor their output to the estimated display time, thus improving output quality while decreasing resource waste by avoiding the production of “extra” frames. The graphics arbiter tells an application when its output is fully or partially occluded so that the application need not expend resources to draw portions of frames that are not visible.

Abstract: The rendering performance of a graphic processor is improved by effectively using a data bus. An externally-input graphics command is stored in a work memory via the data bus. A display data generation section receives a graphics command stored in the work memory via the data bus, decodes the received graphics command, and outputs the display data to the data bus. An image display section receives display data stored in the work memory via the data bus, and displays an image on a display device. A bus control section monitors the status of use of the data bus, and controls the right to use the data bus according to the priority of each data transfer operation.

Abstract: A system and method for generating a graphical image on a display is disclosed. The graphical image is generated from data describing at least one object. The display includes a plurality of positions. Each of the plurality of positions has an area. The system and method include determining if a portion of the at least one object intersects a current position of the plurality of positions and providing an output if the portion intersects the current position. The method and system further include providing a mask for the portion if it is determined that the portion intersects the current position. The mask indicates an extent to which the at least one portion occupies the area of current position. The method and system further include utilizing the mask to provide antialiazing. The method and system also include repeating the determining, one mask providing, and utilizing steps for each of the plurality of positions.

Abstract: A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions.

Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.

Abstract: A graphics system may include a frame buffer that includes several sets of one or more memory banks and a cache. The frame buffer may load data from one of the memory banks into the cache in response to receiving a cache fill request. Each set of memory banks is accessible independently of each other set of memory banks. A frame buffer interface coupled to the frame buffer includes a plurality of cache fill request queues. Each cache fill request queue is configured to store one or more cache fill requests targeting a corresponding one of the sets of memory banks. The frame buffer interface is configured to select a cache fill request from one of the cache fill request queues that stores cache fill requests targeting a set of memory banks that is not currently being accessed and to provide the selected cache fill request to the frame buffer.

Abstract: A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller configured to assert a request for display data to provide to a display device. The frame buffer interface may receive the request for display data from the output controller and delay providing the request for display data to the frame buffer if the processing device is currently requesting access to a portion of the frame buffer targeted by the request for display data. For example, if the frame buffer includes several memory banks and the request for display data targets a first bank, the frame buffer interface may delay providing the request for display data to the frame buffer if the processing device is currently requesting access to the first bank.

Abstract: A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.

Abstract: A graphic processor includes first and second buses and a plurality of geometric operation units having an output connected to the second bus, and a circuit to allocate a plurality of ordered data blocks formed of data to be operated upon to the plurality of geometric operation units, and an input of at least one of the plurality of geometric operation units is connected to the first bus. The plurality of geometric operation units include all arbitrating circuit to arbitrate the order of output between an output buffer to store a result of processing by the allocated data blocks and another geometric operation unit, and output data resulting from processing onto the second bus in an order corresponding to the sequence of the plurality of data blocks of data to be operated upon.

Abstract: A memory interface controls read and write accesses to a memory device. The memory device includes a level-one cache, level-two cache and storage cell array. The memory interface includes a data request processor (DRP), a memory control processor (MCP) and a block cleansing unit (BCU). The MCP controls transfers between the storage cell array, the level-two cache and the level-one cache. In response to a read request with associated read clear indication, the DRP controls a read from a level-one cache block, updates bits in a corresponding dirty tag, and sets a mode indicator of the dirty tag to a the read clear mode. The modified dirty tag bits and mode indicator are signals to the BCU that the level-one cache block requires a source clear operation. The BCU commands the transfer of data from a color fill block in the level-one cache to the level-two cache.

Abstract: A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles processing non-expedite requests during the monitoring window.

Abstract: An arbitration mechanism for balancing memory requests issued by parallel texture pipelines in a multiple pipeline texture engine. The mechanism ensures that, as polygon textures are processed by a texture engine, all of the memory requests associated with a portion of a given graphics texture are issued by all texture pipelines before any texture pipeline may issue a memory request for another portion of a graphics texture. Thus, the invention balances graphics texture processing between parallel texture pipelines operating together, thereby improving processing efficiency and preventing deadlock conditions.

Abstract: The present invention, a method of the arbitration of memory request for a computer graphics system, consecutively services the requests having the same type in the same period, thereby increasing the chance of page-hit. In this arbitration method, the length of a fixed period is defined by the 3-D graphics engine in accordance with the amount of memory cycles or the amount of the requests, and is used for controlling the amount of the requests of each type. The length of the period can be the cycles of servicing a block comprising a tile or several tiles. Alternatively, instead of defining a fixed length of the period, the 3-D graphics engine can choose another arbitration method of the present invention. Another arbitration method of the present invention is to mark a message at the end of the drawing block, so that the memory control can decide to rotate the service order to the next type of requests according to the block-end message received.

Abstract: An advanced dot-stretch anti-sparkle technique analyzes the stream of display pixels to determine an optimal time for performing the dot-stretch operation. The system searches the stream of display pixels for a current and previous pixel that are the same color. The system then performs the host access and the dot-stretch during the pixel match. If a pixel match is not detected within a predetermined period of time, the search for two matching pixels is abandoned and the dot-stretch process is implemented.

Abstract: A display FIFO memory management system and method includes a programmable FIFO emulator for emulating a drain and fill time of the display FIFO memory to automatically predict a number of register entries remaining in the display FIFO memory at each predefined clock cycle. A programmable timer/counter has programmable precision to accommodate varying bandwidths of display screen display modes and is used to determine the number of entries remaining so that the emulator can accommodate varying screen display modes. A FIFO controller controls the timing of fetching display data from memory to fill the display FIFO memory based on the prediction of the number of remaining register entries in the display FIFO by the programmable emulator.

Abstract: A throttled data pipeline having a limited data-transfer rate for conserving system resources is disclosed. The throttled data pipeline of the present invention includes a source, a destination and a throttling device. The throttling device of the present invention is interposed between the source and the destination, and is adapted to limit data-transfer rates through the throttled data pipeline in accordance with predetermined criteria. By limiting data-transfer rates through the throttled data pipeline, system resources of the host computer, which would otherwise be wasted, are conserved. The throttled data pipeline of the present invention is configured to allow for fast and efficient transfers of data during low throughput operations when system resources are not significantly taxed.

Abstract: A video capture system and method whereby video frames or images, which are received in one of a plurality of possible formats, are acquired and stored into on-board memory in an image format. The image data can then be transferred into system memory at an optimum rate. The video capture system comprises a host computer, including a video capture board, which is coupled to a video source, such as a video camera. The video source provides digital video data in a first format of a plurality of different possible formats. The video capture board includes a memory controller which receives the digital video data in the first format and selectively provides the digital video data to the buffer memory in an image format. The memory controller includes address generation logic for generating buffer memory addresses for storing the video data to the buffer memory in the image format.

Abstract: A 3-D graphics chip includes independent internal DRAM buffers each having a wide bandwidth access bus for connection to a 3-D texture rendering drawing engine. The 3-D drawing engine takes advantage of a flexible embedded memory interface to reduce the traditional 3-D pipeline delay by a factor of 3. In a specific embodiment, each of three drawing processes—texture, Z, pixel—retrieves and stores information in a separate embedded drawing buffer via separate wide bandwidth access busses. Access to an external memory is provided via a separate external access bus. In another specific embodiment, the 3-D drawing engine accesses the embedded drawing buffers via read and write FIFO's to maximize the drawing process throughput.

Abstract: The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.

Abstract: A graphics system comprising a scheduling network, a sample buffer and a plurality of filtering units. The sample buffer is configured to store sample generated by a rendering engine. The plurality of filtering units are coupled in a linear series. Each filtering unit of the linear series is configured to send a request for a scanline of sample bins to a first filtering unit of the linear series. The first filtering unit is configured to service the scanline requests by sending burst requests to a scheduling network and coordinating the flow of samples forming the bursts from the sample buffer to the filtering units.

Abstract: It is an object to provide a drive unit capable of properly responding to an access request from a microprocessor side and an access request from a display section side, and further of realizing a high-speed operation and a low power consumption operation. When an MPU access request from an MPU side and an LCD access request from an LCD side take place, an arbitration circuit (160) makes arbitration to start an access operation to a RAM (100) according to one of the access requests. Additionally, a memory access monitor signal /BUSY for monitoring an access state to the RAM is outputted to an external terminal to be inputted to a hardware wait control terminal of the MPU. The arbitration circuit starts the access operation on condition that a RAM precharge operation reaches completion. The MPU sets a start address and an end address on a column and a page and issues a writing start command, whereupon display data in a display area is rewritten automatically.

Abstract: A graphics system that may be shared between multiple display channels includes a frame buffer, an arbiter, and two pixel output buffers. The arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer is divided into a first and a second portion. The arbiter alternates display channel requests for data between the first and second portions of the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the output buffers. The arbiter selects which request to forward to the frame buffer based on a relative state of neediness of each of the requesting display channels.

Abstract: A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.

Abstract: An alternate display content controller provides a technique for controlling a video display separately from and in addition to the content displayed on the operating system monitor. Where the display is a computer monitor, the alternate display content controller interacts with the computer utility operating system and hardware drivers to control allocation of display space and create and control one or more parallel graphical user interfaces adjacent the operating system desktop. An alternate display content controller may be incorporated in either hardware or software. As software, an alternate display content controller may be an application running on the computer operating system, or may include an operating system kernel of varying complexity ranging from dependent on the utility operating system for hardware system services to a parallel system independent of the utility operating system and capable of supporting dedicated applications.

Abstract: It is an object to provide a drive unit capable of properly responding to an access request from a microprocessor side and an access request from a display section side, and further of realizing a high-speed operation and a low power consumption operation. When an MPU access request from an MPU side and an LCD access request from an LCD side take place, an arbitration circuit (160) makes arbitration to start an access operation to a RAM (100) according to one of the access requests. Additionally, a memory access monitor signal /BUSY for monitoring an access state to the RAM is outputted to an external terminal to be inputted to a hardware wait control terminal of the MPU. The arbitration circuit starts the access operation on condition that a RAM precharge operation reaches completion. The MPU sets a start address and an end address on a column and a page and issues a writing start command, whereupon display data in a display area is rewritten automatically.

Abstract: A pull-model system and method provides display data over a network to a plurality of display devices having the same or different video format requirements. Utilization of image memory bandwidth is balanced between the plurality of display devices. Based on image memory bandwidth requirements for the plurality of display devices, a bandwidth allocation table is generated to indicate a servicing priority for the display devices. A plurality of requests for pixel data are received and stored in a request buffer. The requests are then serviced in an order indicated by the bandwidth allocation table.