Abstract: An approach is provided for coalescing network commands in a GPU that implements a SIMT architecture. Compatible next network operations from different threads are coalesced into a single network command packet. This reduces the number of network command packets generated and issued by threads, thereby increasing efficiency, and improving throughput. The approach is applicable to any number of threads and any thread organization methodology, such as wavefronts, warps, etc.

Abstract: The present application is directed to signal delay control and related apparatuses, systems, and methods. An apparatus includes delay elements and control circuitry electrically connected to the delay elements. The delay elements are configured to receive skewed data signals and delay codes indicating delay quantities. The delay elements are also configured to provide delayed data signals delayed relative to the skewed data signals by the delay quantities. The control circuitry is configured to provide the delay codes, which are selected to reduce a timing skew of the delayed data signals relative to a timing skew of the skewed data signals. A system includes a first device, a second device including the apparatus, and transmission lines electrically connected between the first device and the second device. A method includes calibrating the delay codes.

Abstract: Techniques are disclosed for reordering operations of a neural network to improve runtime efficiency. In some examples, a compiler receives a description of the neural network comprising a plurality of operations. The compiler may determine which execution engine of a plurality of execution engines is to perform each of the plurality of operations. The compiler may determine an order of performance associated with the plurality of operations. The compiler may identify a runtime inefficiency based on the order of performance and a hardware usage for each of the plurality of operations. An operation may be reordered to reduce the runtime inefficiency. Instructions may be compiled based on the plurality of operations, which include the reordered operation.

Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.

Abstract: A post processing system, method and computer program product content-adaptively transforms MPEG on-demand media streams, including a video optimizer software development kit (SDK); an application layer controlling the SDK interfacing with a mobile device operating and file system. Raw pixel frame buffers are parsed and structured. The buffers are normalizes for processing. Source content is analyzed in an uncompressed format for video patterns and characteristics and parameters are selected in a video codec output format. Estimated are parameters for portions and/or segments of the content. The content is recompressed and optimized in a content-adaptive manner to generate optimized content written into persistent storage of the mobile device, and segments of which are combined with an audio stream and/or a metadata stream information to generate a playable media stream in an ISO base media file format and/or a media file application specific format.

Abstract: An interactive mixed reality simulator is provided that includes a virtual 3D model of internal or hidden features of an object; a physical model or object being interacted with; and a tracked instrument used to interact with the physical object. The tracked instrument can be used to simulate or visualize interactions with internal features of the physical object represented by the physical model. In certain embodiments, one or more of the internal features can be present in the physical model. In another embodiment, some internal features do not have a physical presence within the physical model.

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

Abstract: Creation of subsystems for a user design to be implemented in an integrated circuit (IC) includes generating, using computer hardware, a subsystem topology based on user provided subsystem data, wherein the subsystem topology specifies a plurality of subsystems of the user design where each subsystem includes a master circuit, and determining, using the computer hardware, a system management identifier for each master circuit of the subsystem topology. Programming data for programmable protection circuits of the IC can be automatically generated using the computer hardware based on the subsystem topology and system management identifiers. The programmable protection circuits, when programmed with the programming data, form the plurality of subsystems and physically isolate the plurality of subsystems on the integrated circuit from one another.

Abstract: An apparatus, process, and computer program product provide an improvement to downscaling techniques for image processing. Embodiments of the downscale processes may be applied to images rendered on printed documents. Aspects of the downscaling processes provide quality, discernible rendered images while being efficient with computing resources. Exemplary embodiments carryover binary bit data from adjacent regions into an application region being downscaled for determination of the downscale output. Depending on the downscale output value for the application region, bits from the application region may be carried over to adjacent regions and used in determining whether those regions, when processed will have an “ON” or “OFF value when downscaled.

Abstract: A flow control system of a clinical perfusion system comprises flow control devices 110, such as pumps, valves and/or clamps, capable of controlling a fluid flow rate according to flow rate parameters from the flow control system. The flow control system comprises an indicator arrangement including a device indicator 122a, 122b on each flow control device 110 capable of providing a plurality of indications. The device indicators 122a, 122b are controllable by the flow control system to indicate an active condition of the flow control device 110 independently of the flow rate parameters. This allows the indication provided by the device indicator 122a, 122b to be adjusted for different clinical environments, and to provide colour indications that match the colour range discernible by users affected by colour vision deficiency.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, one or more drives added to an extent pool of storage devices. An empty Mapped RAID group may be generated. A plurality of extents in the extent pool may be shuffled. A RAID extent may be mapped to the empty Mapped RAID group, wherein the RAID extent is mapped to the empty Mapped RAID group while shuffling the plurality of extents in the extent pool.

Abstract: A system, method and computer program product for improving video codec performance, including a pre-processing stage configured for downscaling by a variable amount an uncompressed video signal before sending such downscaled, uncompressed video signal to an input of a video codec; and a complimentary post-processing stage configured for upscaling the decompressed video signal received from an output of the video codec back to its original resolution before transmitting the decompressed video signal. The system, method and computer program product provides improved rate-distortion performance compared to direct use of the video codec alone.

Abstract: A method of performing diadic operations in a processor is provided that includes receiving a first request packet initiating a read operation from a first memory address in the first request packet, and executing a first operation in the first request packet once the read request is completed. Also, the method includes generating a second request packet at a second memory address by combining the results of the first operation with the unused information in the first request packet. Furthermore, the method includes sending the second request packet to the Memory-Side Processor (MSP). When the MSP receives the second request, the MSP checks to determine if a write operation is requested and writes data to the second memory address, if a read operation is requested, the MSP reads data from the second memory address.

Abstract: Examples described herein generally relate to capturing and executing graphics processing operations. A memory trap function can be activated to cause a graphics processing unit (GPU) to report memory accesses in executing graphics processing operations. Based on activating the memory trap function and for each of a sequence of executed graphics processing operations executed by the GPU, a sequence of memory accessing commands and associated portions of memory modified based on executing the sequence of executed graphics processing operations can be received. Each of the sequence of multiple memory accessing commands and associated portions of memory can be stored and provided to the GPU to emulate re-executing of the sequence of executed graphics processing operations by the GPU.

Abstract: A method of operating a data processing system 4 is disclosed that comprises producing data in the form of blocks of data, where each block of data represents a particular region of a data array, processing the data using a processing operation in which one or more output data values are each determined using data values from plural different lines of the data array, storing the processed data in a memory 21 of the data processing system, and reading the data from the memory 21 in the form of lines.

Abstract: A system, method and computer program product for improving video codec performance, including a pre-processing stage configured for downscaling by a variable amount an uncompressed video signal before sending such downscaled, uncompressed video signal to an input of a video codec; and a complimentary post-processing stage configured for upscaling the decompressed video signal received from an output of the video codec back to its original resolution before transmitting the decompressed video signal. The system, method and computer program product provide improved rate-distortion performance compared to direct use of the video codec alone.

Abstract: Operating a data processing system including producing data in the form of plural blocks of data, where each block of data represents a particular region of an output data array, storing the data in a memory of the data processing system, and reading the data from the memory in the form of lines. Storing the data in the memory comprises storing each block of data of a first row of blocks of data in the memory at one or more memory addresses of a first set of memory addresses of a sequence of memory addresses for the memory, and storing each block of data of a second row of blocks of data in the memory at one or more memory addresses of a second set of different memory addresses of the sequence of memory addresses for the memory.

Abstract: In some examples, additional content is provided with the main content of a content item presented on an electronic device. For instance, an occurrence of an event may call for presentation of an additional content portion concurrently with the main content of the content item. The additional content portion may interact with other additional content portions, the main content portion, and/or user inputs. In some cases, the additional content portion can be implemented by one or more plug-in modules having designated roles for providing respective different types of additional content. Accordingly, some examples provide a cross-platform module that receives events, selects one or more plug-ins in response to a received event, and causes the one or more plug-ins to perform a desired action for rendering and compositing additional content portions or features to be presented with the main content of a content item.

Abstract: Disclosed are a rendering method of a 3D web-page and a terminal using the same. The rendering method includes loading a source text including depth information on one or more 3D objects constituting the 3D web-page, creating a document object model (DOM) tree and style rules including the depth information by parsing the source text, generating a render tree based on the DOM tree and the style rules, performing a layout on the render tree, painting left-eye and right-eye pages by applying, to the result obtained by performing the layout, a 3D factor including one or more the position, size, disparity, shape and arrangement of the 3D object, and merging the left-eye and right-eye pages and displaying the merged left-eye and right-eye pages on the 3D browser.

Abstract: The instant application discloses receiving a command via a processor to initiate a window creation operation on a client computing device, retrieving at least one image tile pre-allocated in a memory of the client computing device, performing a draw operation that places at least one image overplayed onto the at least one image tile and displaying the image overplayed onto the at least one image tile on a display of the client computing device.

Abstract: A method is provided for sharing access to graphics processing unit (GPU) hardware between multiple client virtual machines, wherein each of the client virtual machines has a high-level application programming interface (API) associated therewith for communicating with the GPU hardware. The method includes virtualizing the GPU by intercepting GPU-specific commands from the plurality of client virtual machines, wherein the commands specific to the GPU are at a lower level than that of the high-level API, and providing the intercepted commands to the GPU hardware.

Abstract: A display device includes a display panel, a first timing controller, and a second timing controller. The display panel includes a first block and a second block adjacent to the first block, with a data line positioned between the first block and the second block. The first block includes a first column of pixels, and the second block includes a second column of pixels. The first and second columns of pixels are alternately connected to the data line. The first timing controller is configured to receive first image data corresponding to the first block. A second timing controller is configured to receive second image data corresponding to the second block. The first timing controller is configured to transfer at least part of the first mage data to the second timing controller.

Abstract: A method for transcoding a video file bit stream in parallel at a sub picture latency and faster than real time rate includes writing to a memory a processed raw pixel data stream. The processed raw pixel data stream is expressed as a sequence of pictures. Each picture is divided into a first sub picture partition and a second sub picture partition. A first encoder encodes each first sub picture partition, the first encoder being communicatively coupled to the memory. A second encoder encodes each second sub picture partition, the second encoder being communicatively coupled to the memory.

Abstract: An image processing system includes an image coding device serving as a host device that outputs image data, and an image decoding device serving as a client device and including a display part that displays an image based on image data transmitted from the image coding device. The image coding device includes an image quality controller that controls the image quality of an image displayed on the display part in accordance with an operation status A of the image processing system. When the operation status is a status under which a delay of displaying an image which is caused by transmission of image data from the image coding device to the image decoding device is allowed, the image quality controller increases the image quality of an image displayed on the display part.

Abstract: A method for customizing a map is provided. The method includes receiving a query for a portion of a map, and determining a predetermined region of interest (ROI) map tile included in the portion of the map. The predetermined ROI map tile indicates information associated with a category. The method further includes providing the predetermined ROI map tile for displaying to a user. Further, an apparatus for customizing maps is provided. The apparatus includes a movement event processor for receiving a query for a portion of a map, and a Region of Interest (ROI) selector for determining a predetermined region of interest (ROI) map tile included in the portion of the map. The predetermined ROI map tile indicates information associated with a category. The apparatus further includes a map tile layout generator for providing the predetermined ROI map tile for displaying to a user.

Abstract: Techniques are directed to managing image generation for desktop and screen sharing systems as well as for large image systems such as mapping. An apparatus may comprise a logic device, a remote sharing module and an image generation module. The remote sharing module is operative on the logic device to share an image with one or more client devices. The image may be divided into a plurality of tiles each corresponding to a portion of the shared image. The image generation module is operative on the logic device to determine a version of each of the plurality of tiles and compares the version of each of the plurality of tiles with a received client version of the same image.

Abstract: A technique for enabling scenario files and image files for supply to a scenario generating device to be created easily is provided. The scenario creating device creates a scenario file supplied to a scenario reproducing device capable of reproducing only image files of a predetermined format. The scenario creating device comprises: an input section including a pointing device; a display section; and a scenario creating section for creating the scenario file. The scenario creating section provides a display of an execution icon on the display screen for causing the scenario creating section to execute a process. When a file icon for a source file of a predetermined format including pagewise scenario information and image information is dragged and dropped on the execution icon by means of operation of the pointing device, a scenario file is created on the basis of the scenario information, and an image file of the predetermined format is generated on the basis of the image information.

Abstract: A method for loading a shader program from system memory into GPU memory. The method includes accessing the shader program in system memory of a computer system. A DMA transfer of the shader program from system memory into GPU memory is performed such that the shader program is loaded into GPU memory in an address independent manner.

Abstract: Methods are provided for reordering operations in execution of an effect graph by graphics processing unit. Memory availability is evaluated for storing images rendered using the effect graph. Memory is allocated for multiple parallel intermediate textures that store images. Operations that write to these textures are executed. It is then determined that there is not sufficient memory to perform additional parallel operations. The memory currently allocated is flushed, and memory for an upper-level texture is allocated. The operations that write pixels to the upper-level texture are executed.

Abstract: For providing a display device and a method for transferring an image data, shortening process time required to transfer image data without greater processing capacity, the CPU 4 outputs the bypass write signal to the GDC 6, the CPU 4 then outputs the read signal to both the ROM 5 and the GDC 6, and the ROM 5 outputs the image data to the data bus 8 according to input of the read signal, wherein the GDC 6 directly reads the image data outputted on the data bus 8 according to input of the read not through the CPU 4 and writes the read image data to the VRAM 7.

Abstract: A display device may reduce the latency of the display of a digital signal by reducing the latency that the display device adds to the digital signal. After a digital signal is received by an input module, the signal is stored in a frame buffer as a plurality of pixels. A controller determines the input frame rate of the digital signal and a pixel delay. The controller monitors the frame buffer to determine when the frame buffer has stored a number of pixels greater than or equal to the pixel delay. After the frame buffer contains enough pixels, the controller initiates transmission of the pixels from the frame buffer to a display module. In certain embodiments, the controller initiates transmission of the pixels to the display module before the frame buffer has stored all pixels corresponding to the frame.

Abstract: The example techniques described in this disclosure may be directed to interaction between a graphics processing unit (GPU) and a system memory. For example, the GPU may include a memory copy engine that handles tasks related to accessing data that is stored or is to be stored in the system memory. In addition, in some examples, the memory copy engine may perform additional tasks such as modification tasks to increase the performance of the GPU.

Abstract: One embodiment of the present invention sets forth a technique for storing only the enabled components for each enabled vector and writing only enabled components to one or more specified render targets. A shader program header (SPH) file provides per-component mask bits for each render target. Each enabled mask bit indicates that the pixel shader generates the corresponding component as an output to the raster operations unit. In the hardware, the per-component mask bits are combined with the applications programming interface (API)-level per-component write masks to determine the components that are updated by the shader program. The combined mask is used as the write enable bits for components in one or more render targets. One advantage of the combined mask is that the components that are not updated are not forwarded from the pixel shader to the ROP, thereby saving bandwidth between those processing units.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: A system and method are disclosed for managing memory requests that are coordinated between a system memory controller and a graphics memory controller. Memory requests are pre-scheduled according to the optimization policies of the source memory controller and then sent over the CPU/GPU boundary in a bundle of pre-scheduled requests to the target memory controller. The target memory controller then processes pre-scheduling decisions contained in the pre-schedule requests, and in turn, issues memory requests as a proxy of the source memory controller. As a result, the target memory controller does not need to perform both CPU requests and GPU requests.

Abstract: Systems and methods are provided for upscaling a digital image. A digital image to be upscaled is accessed, where the digital image comprises a plurality of pixel values. A first half pixel value is computed for a first point in the digital image based on a plurality of pixel values of the digital image surrounding the first point and an activity level. A second half pixel value is computed for a second point in the digital image, and an interpolated pixel of an upscaled version of the digital image is determined using a plurality of the pixel values, the first half pixel value, and the second half pixel value.

Abstract: Embodiments include a single integrated circuit comprising: a first display controller configured to control a non-bistable display screen; and a second display controller configured to control a bistable display screen. Embodiments also include disposing, on a single integrated circuit, a first display controller capable of controlling a non-bistable display screen; and a second display controller capable of controlling a bistable display screen.

Abstract: Virtualization of graphics resources and thread blocking is disclosed. In one exemplary embodiment, a system and method of a kernel in an operating system including generating a data structure having an identifier of a graphics resource assigned to a physical memory location in video memory, and blocking access to the physical memory location if a data within the physical memory location is in transition between video memory and system memory wherein a client application accesses memory in the system memory directly and accesses memory in the video memory through a virtual memory map.

Abstract: An image forming apparatus displays, on a display section, a plurality of button areas to which setting values in relation to functions of the image forming apparatus are assigned. In a case that an input form of an instruction coordinate to the display section is a predetermined first form, the setting values assigned to a button area in which the instruction coordinate is positioned are displayed on the display section. In a case that after the setting values are displayed and further that change operation for a specific setting value is inputted, the specific setting value is changed. In a case that the instruction coordinate is positioned in a button area of the plurality of button areas and that the input form of the instruction coordinate is a predetermined second form, the image forming apparatus is operated based on the setting values assigned in the button area.

Abstract: An apparatus configured to match an input frame rate of a video stream with an output frame rate of an output stream, the apparatus comprising, at least one memory buffer, an output frame generator, and a threshold measurement unit, the threshold measurement unit configured to generate a control feedback, wherein the box is configured to analyze the control feedback to monitor a state of the at least one memory buffer, the threshold measurement unit further configured analyze the control feedback to regulate between two or more different settings, wherein the two or more different settings include slowing down or speeding up the output frame, wherein the two or more different settings further include slowing down or speeding up of the line rate of the output stream.

Abstract: A method of transmitting visual data from a host computer to multiple displays across a computer network is disclosed. Visual data is stored in a plurality of frame buffers, each frame buffer associated with a separate display. A frame buffer update sequence is determined, with operations to be performed on frame buffers in the plurality. The data stored in the plurality of frame buffers is encoded as specified by the buffer update sequence to yield encoded images and each encoded image is sent across a computer network to the separate display associated with the frame buffer from which the encoded image was derived.

Abstract: A telephone book data processor includes: a connection element for connecting to an external device via a short range communication manner to transfer a telephone book data; a telephone book data obtaining element for obtaining the telephone book data; a memory having multiple memory regions for storing the telephone book data; and a controller for executing a telephone book data transfer process and a telephone book data utilizing process. The controller defines one memory region as an object of the telephone book data transfer process and another memory region as an object of the telephone book data utilizing process. The controller executes the telephone book data utilizing process with using the telephone book data in the another memory region while the controller executes the telephone book data transfer process for storing a new telephone book data in the one memory region.

Abstract: Embodiments provide techniques for generation and outputting of display data. For instance, embodiments provide features involving frame data storage within display devices. Also, embodiments provide features involving the isolation of different user contexts to different frame buffers. Further, embodiments provide efficient techniques for saving frame data upon the transitioning between power states. Moreover, embodiments provide techniques for flexibly and dynamically allocating multiple display content to a physical display.

Abstract: A system and method for cryptographically securing a graphics system connectable via an external bus to a computing system, the graphics system including a graphics processor, a video memory and a memory controller for controlling the flow of data to and from the video memory. The graphics system further includes a copy engine for copying data between a system memory of the computing system and the video memory, where this copy engine acts independently of the graphics processor of the graphics system. The present invention enables the copy engine of the graphics system to decrypt encrypted data in the course of copying data from the system memory to the video memory and to encrypt unencrypted data in the course of copying data from the video memory to the system memory. Thus, cryptographic protection of secure content may be assured by the graphics system without the excessive usage of its primary resources for this non-graphical purpose.

Abstract: The disclosure relates to a system for controlling devices and information on a network by hand gestures, and more particularly, to a system for controlling devices and information on a network by hand gestures in which a device or a file to be controlled is selected by a user and a display device is pointed so that information and data can be shared and that various devices can be coupled to each other easily and can be controlled easily. The system for controlling devices and information on a network by hand gestures can remarkably improve the interaction between various input and display devices and a user under a ubiquitous computing environment.

Abstract: An image processing apparatus is provided that includes a main memory; at least one sub-memory that stores data, a cache memory that temporarily stores data, and controller that controls whether to temporarily store the data in the cache memory selectively with respect to each of the at least one sub-memory.

Abstract: A display pipe may include fetch circuitry and a scaler unit, and registers programmable with information that defines active regions of an image frame. Pixels within the active regions are active pixels to be displayed, pixels outside of the active regions are inactive pixels not to be displayed. The fetch circuitry may retrieve frames from memory, retrieving the active pixels and not retrieving the inactive pixels as defined by the programmed contents of the registers. A scaler unit may produce scaled pixels from the fetched pixels, basing each scaled pixel on a respective corresponding set of pixels. When a given pixel of the respective corresponding set of pixels is an inactive pixel, the scaler unit may assign an estimated value to the given pixel based on one or more active pixels in the respective corresponding set of pixels. The scaler unit may provide the scaled pixels to a blend unit for blending with other pixels.

Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.

Abstract: A user interface unit in a graphics processing display pipe may include registers programmable with information that defines active regions of an image frame. Pixels within the active regions of the image frame are meant to be displayed, while pixels outside of the active regions of the image frame are not to be displayed. Fetch circuitry within the user interface unit may fetch frames from memory, fetching only the pixels within the active regions of the image frames as defined by the programmed contents of the registers. The user interface unit may then provide the fetched pixels to a blend unit to blend the fetched pixels with pixels from other frames or pixels of a video stream to produce output frames. When blended with pixels of a video stream, the fetched pixels may be displayed as a graphics overlay on top of the video stream.

Abstract: An apparatus including a first memory, a second memory, and a memory interface. The first memory may be configured to store an entire image. The second memory may be configured to store a portion of the image during an image processing operation. The memory interface may be configured to transfer the portion of the image (i) from a source area of the first memory to the second memory prior to the image processing operation and (ii) from the second memory to a destination area of the first memory following the image processing operation. The memory interface may be further configured to select from among four modes of transferring image data from the source area of the first memory and to the destination area of the first memory based upon how the source area and the destination area overlap in the first memory.