Abstract: A networking conferencing and collaboration tool utilizing an enhanced T.128 application sharing protocol. This enhanced protocol is based on a per-host model command, control, and communication structure. This per-host model reduces network traffic, allows greater scalability through dynamic system resource allocation, allows a single host to establish and maintain a share session with no other members present. The per-host model allows private communication between the host and a remote with periodic broadcasts of updates by the host to the entire share group. This per-host model also allows the host to allow, revoke, pause, and invite control of the shared applications. Subsequent passing of control is provided, also with the hosts acceptance. The model contains no fixed limit on the number of participants, and dynamically allocates resources when needed to share or control a shared application. These resources are then freed when no longer needed.

Abstract: A method for efficiently processing graphics data for graphics primitives, the graphics data including vertex coordinate information and vertex attribute data. Coordinate information, in the form of homogeneous coordinates, of the graphics primitive determines whether the graphics primitive is to be rendered. If the primitive is to be rendered, then attribute data associated with the location information is retrieved. However, if the data is not to be rendered, then the location information is discarded. By only retrieving parameters for a primitive that is rendered, performance is increased. In one embodiment, the attribute data is fetched before it is known whether or not the graphics primitive is to be rendered, and if not, the prefetch is aborted, and new location information is fetched.

Abstract: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: A semiconductor device capable of displaying a still image with low consumption power is provided. In the semiconductor device incorporated with a semiconductor display device capable of displaying the still image, a memory portion is mounted on a substrate on which a pixel portion is formed. As a mounting method, the memory portion is formed on the substrate on which the pixel portion is formed or a stick driver including the memory portion is used. When the still image is displayed using image data stored in such a memory portion, the still image can be displayed by inputting only simple control signals from the outside of the semiconductor device. Thus, there are provided the semiconductor display device capable of displaying the still image with low consumption power and the semiconductor device incorporated with the semiconductor display device.

Abstract: An LCD controller (10) has a DMA unit (18) and a FIFO memory (20) for storing display data. The LCD controller also has a display data generator (26) that generates display information using a line of the display data stored in the FIFO memory in accordance with a predefined algorithm. A holding register (28) is connected to the display data generator and stores the generated display information. A multiplexer (34) selects for display either the data stored in the FIFO memory or the generated display information. The generated display information is selected when there is a bus overload indicating that the data stored in the FIFO may be erroneous.

Abstract: To make it possible to execute the same application regardless of the number of connected panels even in a multi-panel environment. A host system, which transfers an image signal to a plurality of panels connected thereto, comprises: a panel ID recognition section for recognizing a panel ID of a single panel or a predetermined number of collected panels as a unit; a window ID allocation section for allocating a window ID to a window which is a transfer processing unit of the image signal; a control signal output section for outputting a control signal used for setting a window ID to be processed to the panel ID to be read out in transferring the image signal; and an image signal transfer section for adding the window ID allocated by the window ID allocation section to the image signal, thus transferring the image signal.

Abstract: A video display system that co-locates a video display memory with the video display device, and transmits to the display device those portions of the image data that have changed rather than continually updating the entire video image. Each display device is addressable, allowing multiple display devices showing different images to be updated through a single display controller port over a single bus or over a single daisy-chain connection. The image data can be updated synchronously or asynchronously, and display devices using different formats can share the same bus or cable.

Abstract: A method for scaling an image frame by an off-screen technology is provided. An image frame consisting of n rows and m columns of data is stored into a storage device. The image frame is divided into a plurality of image portions. Then, the plurality of image portions are picked in sequence to a frame buffer register. An image scaling operation is performed for each picked image portion, and then the scaled image portion is cleared from the frame buffer register.

Abstract: A graphics plotting apparatus which can realize both optimum division of a processing system into blocks and optimum arrangement of the blocks and can be augmented in terms of the performance for a three-dimensional graphics plotting process. The graphics plotting apparatus includes a logic circuit block and a memory block having a capacity sufficient to store display data to be displayed. Both blocks are built in the same chip. An input buffer having a capacity for more than one apex of a three-dimensional graphics plotting primitive is provided, and an interface for transfer of data to and from the outside and the input buffer are arranged on one side of the logic circuit block. A DDA setup circuit is arranged adjacent the input buffer, and a triangle DDA circuit is arranged adjacent the DDA setup circuit. A pair of texture processing circuit blocks are arranged adjacent the triangle DDA circuit.

Abstract: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating.

Abstract: Systems and methods for private addressing in a multi-processor graphics processing subsystem having a number of memories and a number of graphics processors. Each of the memories includes a number of addressable storage locations, and storage locations in different memories may share a common global address. Storage locations are uniquely identifiable by private addresses internal to the graphics processing subsystem. One of the graphics processors is able to access a location in a particular memory by referencing its private address.

Abstract: A method and system for controlling the algorithmic elements in 3D graphics systems via an improved 3D graphics API is provided. In one aspect, in a 3D graphics system having privatized formats with privatized drivers used to increase the efficiency of display, existing problems are eliminated that are associated with multiple redundant copies of the publicly formatted graphics data made in host system memory pursuant to various graphics operations e.g., lock and unlock operations. The ability to make a system copy of publicly formatted data is exposed to the developer, eliminating the creation of unnecessary, and redundant copies. Efficient switching between the privatized and public format remains hidden from the developers so that applications execute efficiently while removing consideration thereof from the developers. Thus, developers are free to consider other tasks.

Abstract: A method and system are provided for executing SIMD instructions using graphics technology. A SIMD instruction is received and interpreted. The specific data needed for the SIMD instruction is identified. Texel addresses where the specific data are stored are recalled and frame buffer pixels to be used to support the SIMD instruction are selected. In an alternative embodiment, these texel addresses are stored in frame buffer pixel channels such that the pixel containing a particular address will be the pixel to hold the data stored at that address for the SIMD operation.

Abstract: In a graphics processing circuit, up to N sets of state data are stored in a buffer such that a total length of the N sets of state data does not exceed the total length of the buffer. When a length of additional state data would exceed a length of available space in the buffer, storage of the additional set of state data in the buffer is delayed until at least M of the N sets of state data are no longer being used to process graphics primitives, wherein M is less than or equal to N. The buffer is preferably implemented as a ring buffer, thereby minimizing the impact of state data updates. To further prevent corruption of state data, additional sets of state data are prohibited from being added to the buffer if a maximum number of allowed states is already stored in the buffer.

Abstract: The data transfer device for transferring data between a system bus and a local memory having a frame buffer region and a general region includes an interface section and a data processor. The interface section generates a transfer parameter for accessing one of the frame buffer region and the general region based on control data for controlling data transfer sent from the system bus and outputs the generated transfer parameter, in addition to transferring data to/from the system bus. The data processor generates an address of data to be transferred in the local memory according to the transfer parameter, and transfers data to/from the local memory using the generated address, in addition to transferring data to/from the interface section.

Abstract: A method, apparatus, and computer implemented instructions for managing a set of memory resources used to store texture objects in a data processing system. A texture manager allocates memory to a current texture object in a set of memory resources. A stored texture object, handled by the texture manager, is selectively removed in response to an inability to allocate sufficient memory to the current texture object. The allocating and selectively removing steps are repeated until the current texture object is allocated sufficient memory. The repeating step is halted in response to an absence of any stored texture objects, handled by a texture manager, being present in the first memory resource. Stored texture objects, handled by another texture manager, are selectively removed in response to an inability to allocate sufficient memory to the current texture object. Memory is allocated in the set of memory resources to the current texture object in response to selectively removing stored texture objects.

Abstract: A method and apparatus determines if a BLT command meets BLT override criteria. If the BLT override criteria is met, the method and apparatus performs a BLT command override and instead executes a FLIP operation instead of performing a BLT operation.

Abstract: A display control apparatus contains a video memory, a video memory controller, a color palette memory and a color palette replacer signal generator. The video memory stores display data that are read from a CD-ROM and contain header data (HA-HD), palette data (P0-P2) and bitmap data (BA-BD) in connection with four planes which are combined together to form one frame of picture. The header data contain a color palette pointer (CPP) and a color palette replacer instruction (CPP31) with respect to each of the planes. The video memory controller reads the palette data and bitmap data from the video memory in accordance with addresses designated by the header data. The color palette replacer signal generator generates a color palette replacer signal (COL) based on the header data so as to make determination whether to replace contents of color palettes with respect to the planes respectively.

Abstract: A circuit for providing an overlay in a window on a computer output display including scaling circuitry, storage circuitry for receiving a plurality of lines of source data, input circuitry for loading the storage circuitry in a first prefill mode and in a second low water mark mode, and circuitry for selecting a mode for loading the storage circuitry responsive to the characteristics of the demand for data placed on the storage circuitry.

Abstract: A memory system and methods of operating the same that drastically increase the efficiency in memory use and allocation in graphics systems. In a graphics system using a tiled architecture, instead of pre-allocating a fixed amount of memory for each tile, the invention dynamically allocates varying amounts of memory per tile depending on the demand. In one embodiment all or a portion of the available memory is divided into smaller pages that are preferably equal in size. Memory allocation is done by page based on the amount of memory required for a given tile.

Abstract: When a deviation between the color difference vectors in comparison of the confirming patches printed out by both the proofers with the reference patch is within the tolerable value Th2, it is decided that the proofer images outputted by both the proofers are coincident with one another in color.

Abstract: A method and system for controlling the algorithmic elements in 3D graphics systems via an improved 3D graphics API is provided. In one aspect, in a 3D graphics system having privatized formats with privatized drivers used to increase the efficiency of display, existing problems are eliminated that are associated with multiple redundant copies of the publicly formatted graphics data made in host system memory pursuant to various graphics operations e.g., lock and unlock operations. The ability to make a system copy of publicly formatted data is exposed to the developer, eliminating the creation of unnecessary, and redundant copies. Efficient switching between the privatized and public format remains hidden from the developers so that applications execute efficiently while removing consideration thereof from the developers. Thus, developers are free to consider other tasks.

Abstract: A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating.

Abstract: A screen capture tool reduces information transfer when capturing a series of screen areas. For example, the screen capture tool reduces usage of Bit Block Transfer operations from a display card frame buffer to system memory. The screen capture tool scans pixel values in portions of a screen area to detect changes relative to a previously captured screen area, identifying portions to be updated by BitBlt operation. Or, the screen capture tool analyzes display driver commands to identify portions of a screen area to be updated by BitBlt operation. The screen capture tool then constructs a representation of the screen area. For example, the screen capture tool provides portions of the screen area that do not require a BitBlt operation (which may involve copying or other use of pixel information already in system memory) and then captures other portions of the screen area by BitBlt operation.

Abstract: A graphic processing system having a main memory for storing a program and information corresponding to pixels, a main processor for executing a program transferred from the main memory or from external to control the system, display/output devices for outputting graphic information attained by a control of pixels arranged in a plurality of dimensions, a frame buffer for storing information corresponding to pixels output to the display/output devices, and a graphic processor for receiving a command and parameter information from the main memory and/or the main processor, for generating character and graphic data in accordance with a predetermined processing procedure, and for performing a transfer control including an execution of a drawing processing to transfer generated data through first and second address buses and first and second data buses to the main memory and/or frame buffer.

Abstract: A device to spatially and temporally reorder data a processor, memory and peripherals. This device is able to spatially and temporally reorder data for both write and read operations to and from memory, peripherals and a processor. This device uses a peripheral write path spatial reordering unit and a peripheral write temporal reordering unit to reorder data transmitted to peripherals and the memory. Further, this device users a peripheral read data path spatial reordering unit to reorder data read from peripheral devices. In addition, a main memory spatial reordering unit is utilized to reorder data read from main memory.

Abstract: A display controller circuit for controlling a display memory having a plurality of memory locations, each memory location having a memory depth. Pixel data having a pixel data depth and a repeat count having a repeat count depth may be stored in each memory location of the display memory. The repeat count represents the number of times the pixel data is to be repeated for display on the external display device. The display controller circuit may be a “fetch inhibiting” display controller or a “memory saving” display controller. A method for controlling memory having a plurality of memory locations, each memory location having a memory depth, the memory depth divided into a data depth for storing data and an excess depth for storing a repeat count.

Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Abstract: A programmable display controller for use in a digital imaging system has a video control register, a data access controller and a programmable modulator. The programmable display control is designed to be used with a digital imaging systems, such as digital cameras, having a variety of display different devices that require respective different control signals, different image signal modulations, and so on. The video control register stores video mode bits indicating the type of video signal to output. The data access controller has a buffer for requesting image data and storing the requested image data in the buffer. The programmable modulator, in response to the video mode bits, generates a video signal from the image data stored in the buffer. In some embodiments, a decoder detects and decodes a link code in received image data. An address generator is responsive to the decoder and outputs a link address corresponding to the decoded link code for fetching image data that is stored at the link address.

Abstract: A memory controller hub has a data stream controller adapted to use a system memory to store graphics data and to control functions of the system memory, a processor interface, a system memory interface, a graphics subsystem coupled to the data stream controller and adapted to perform graphics operations on graphics data, and a graphics port adapted to couple the memory controller hub to an external graphics device.

Abstract: An efficient method and system for displaying integrated transparent objects and animation with a window, such as an Internet Web page is described. The present invention implements a plugin-control, such as a Netscape plugin or ActiveX control, in the host program, such as a Web browser, wherein the plugin-control provides at least one graphics buffer in addition to the buffers used by the host program. The plugin-control can function according to the host program Application Programming Interface (API) for the plugin-control under which the at least one additional buffer is used to composite a “compositing plane” containing the transparent objects and animation with the host program window and where the resulting composited scene is returned to the host program buffers as part of the regular host program draw pipe. Additionally, the host program API may be circumvented and the resulting composited scene may be written directly to the front buffer for display on the display device.

Abstract: A video capture system and method whereby video frames or images, which are received in one of a plurality of possible formats, are acquired and stored into on-board memory in an image format. The image data can then be transferred into system memory at an optimum rate. The video capture system comprises a host computer, including a video capture board, which is coupled to a video source, such as a video camera. The video source provides digital video data in a first format of a plurality of different possible formats. The video capture board includes a memory controller which receives the digital video data in the first format and selectively provides the digital video data to the buffer memory in an image format. The memory controller includes address generation logic for generating buffer memory addresses for storing the video data to the buffer memory in the image format.

Abstract: A DMA computer system (10) for driving a peripheral device such as an LCD display (12) of a GPS receiver without stealing excessive cycles from a CPU (18). The DMA computer system (10) includes a CPU (18), a first memory (20) that may be written to or read by the CPU (18), a second memory (22) that may be written to or read by the CPU (18), and a DMA controller (24) coupled with the CPU (18) and the second memory (22). The DMA controller (24) is operable to: read data from the second memory (22) and transfer the data to the peripheral device; delay the CPU (18) from accessing the second memory (22) while the DMA controller (24) is reading data from the second memory (22); enable the CPU (18) to regain access to the second memory (22) once the DMA controller (24) has finished reading data from the second memory (22); and allow the CPU (18) to access the first memory (20) without delay even while the DMA controller (24) is reading data from the second memory (22).

Abstract: Methods for operating a frame buffer memory device are disclosed which provide for accelerated rendering of two-dimensional and three-dimensional images in a computer graphics system One disclosed operation is a method for compressing data to be transmitted from a controller to the memory device and then decompressing the data within the memory device once it has been transmitted and received.

Abstract: A DMA computer system (10) for driving a peripheral device such as an LCD display (12) of a GPS receiver without stealing excessive cycles from a CPU (18). The DMA computer system (10) includes a CPU (18), a first memory (20) that may be written to or read by the CPU (18), a second memory (22) that may be written to or read by the CPU (18), and a DMA controller (24) coupled with the CPU (18) and the second memory (22). The DMA controller (24) is operable to: read data from the second memory (22) and transfer the data to the peripheral device; delay the CPU (18) from accessing the second memory (22) while the DMA controller (24) is reading data from the second memory (22); enable the CPU (18) to regain access to the second memory (22) once the DMA controller (24) has finished reading data from the second memory (22); and allow the CPU (18) to access the first memory (20) without delay even while the DMA controller (24) is reading data from the second memory (22).

Abstract: A telecom mask testing zoom function draws mask. pixels into a raster memory. In this way, the mask is treated as a waveform. Comparison of the mask pixels and waveform pixels to detect collision between a waveform pixel and a mask pixel (i.e., a mask violation) is performed substantially in real time, as the pixels are being composited into the raster memory by the rasterizer. The mask is scalable and repositionable by the rasterizer under control of a controller, because it is treated as a waveform. The mask is lockable to the waveform because both are stored in pixel form in raster memory by the rasterizer under control of the controller.

Abstract: A method and apparatus for managing texture mapping data in a computer graphics system, the computer graphics system including a host computer, primitive rendering hardware and a primitive data path extending between the host computer and the primitive rendering hardware. The host computer passes primitives to be rendered by the system to the primitive rendering hardware over the primitive data path. The host computer has a main memory that stores texture mapping data corresponding to the primitives to be rendered. The primitive rendering hardware includes a local texture memory that locally stores the texture mapping data corresponding to at least one of the primitives to be rendered. When a primitive passed to the primitive rendering hardware is to be rendered, a determination is made as to whether its corresponding texture mapping data is in the local texture memory.

Abstract: A video graphics system that includes a graphics processing circuit and a logic enhanced memory is presented. The logic enhanced memory includes an operation block that performs blending operations for fragment blocks received from the graphics processing circuit, where the fragment blocks include pixel fragments generated by rendering graphics primitives. In order to allow limited bandwidth buses that transport data between the graphics processing circuit and the logic enhanced memory to be used with maximum efficiency, an input buffer and an output buffer are included in the logic enhanced memory. A graphics processing circuit maintains history data that indicates how full the input and output buffers of the logic enhanced memory are, and as such, can ensure that new fragments blocks and operational commands are not provided to the logic enhanced memory in a manner that would cause the processing capabilities of the logic enhanced memory to be exceeded.

Abstract: A graphics processing system that includes a graphic processing circuit and an enhanced memory circuit is presented. The graphics processing circuit performs the rendering of graphics primitives to produce pixel fragment data. The pixel fragment data is then grouped into fragment blocks that are compressed and sent across a bus of limited bandwidth in an efficient manner to the enhanced memory circuit. Within the enhanced memory circuit, the compressed fragment blocks are decompressed and restored to their original state. Comparison and blending operations are then performed on a block-by-block basis with pixel data stored in the frame buffer.

Abstract: A method of controlling a terminal device which receives display information from a host device and displays the display information on a screen includes the steps of displaying newest display information supplied from the host device in a predetermined area of the screen, and displaying previous display information in a remaining area of the screen, the previous display information having been supplied from the host device and once displayed as the newest display information in said predetermined area.

Abstract: On-screen-display graphics data is transmitted from a source device to a display device over an IEEE 1394-1995 serial bus network utilizing an isochronous data format. The on-screen-display graphics data is generated by the source device and transmitted to a display device, as a stream of isochronous data, separate from video data. Each packet of isochronous data within the stream of on-screen-display graphics data includes an address value corresponding to a memory address within the display device forming a buffer. When received by the display device the on-screen-display graphics data is loaded into the appropriate memory locations within the buffer corresponding to the address values. At the display device, an embedded stream processor is utilized to strip the header information from each packet and determine the appropriate memory location that the data is to be stored. A trigger packet is sent at the end of the data stream for a screen of on-screen-display graphics.

Abstract: A method to perform image transformations that are simplistic, conducive to miniaturization, and inexpensive to implement is provided. Transformations of an image stored in system memory are carried out by copying the image data, transforming the image data to a selected orientation, and outputting the transformed image for display, printing, or others. Throughout the transformation process, the image stored in system memory remains unchanged in the original orientation (T0-normal transformation). The transformation process is carried out by accessing in predetermined orders/sequences the image data copied from system memory to a frame buffer that is made up of N memory modules and arranged such that image data are stored serially with the image scan lines running the length of the frame buffer like that of a traditional frame buffer but with each memory module capable of being individually accessed.

Abstract: Methods for operating a graphics system which employs one or more frame buffer memory devices are disclosed which methods provide for accelerated rendering of two-dimensional and three-dimensional images in a computer graphics system One disclosed operation is a method for compressing data to be transmitted from a controller to the memory device and then decompressing the data within the memory device once it has been transmitted and received.

Abstract: The object of the present invention is to provide an image display apparatus suited to display a video program or the like for advertisement purposes. The image display apparatus comprises a storage medium installation section (11), a memory section (13) storing image data read out from a storage medium (1) installed into the storage medium installation section (11), a display section (16) displaying the image data stored in the memory section (13) and a control section (19) for repeatedly executing display of the image data stored in the memory section (13) at the display section (16).

Abstract: A method and apparatus for performing selective data reads from a memory are presented. A memory command is received from a requesting entity, and a memory address is derived from the memory command. The memory address is then applied to a memory array that stores a plurality of data packets, where the memory array outputs a selected data packet in response to the memory address. Data selection control information is also derived from the memory command. The data selection control information is used to select a selected portion of the selected data packet. This selected portion is then packed into at least one data flit, which is sent over a bus to the requesting entity.

Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Abstract: The present invention is directed to an Video Processing Engine that is an Overlay Filter Scaler (OFS) having a memory to memory video signal processor decoupled from the display that is better able to meet the feature requirements of a computer graphics system while simplifying the design. The memory-to-memory operation of the video signal processor also facilitates the display of more than one video stream by allowing processed images to be placed in the primary graphics buffers for display. This is particularly useful in video conferencing applications, and for displaying multiple live “thumbnails” of various video feeds. In addition, the signal processor can be used as a graphics anti-aliasing filter by having it process 2-D and 3-D computer graphics images before they are written to the primary display buffer. Similarly, the signal processor can also be used as a “stretch-blitter”, to expand or contract graphics as needed.

Abstract: A computer system and an associated graphics adapter that includes one or more processors connected to a host bus. A system memory is accessible from the host bus via a memory controller and an I/O bridge is coupled between the host bus and an I/O bus. The computer system further includes a frame buffer suitable for storing a representation of a graphic image and the graphics adapter connected to the I/O bus. The graphics adapter includes means for receiving host pixel data that is formatted, according to a host format defining the ordering and width of a set host components, as a set of host component values. The adapter also has means for transforming the host pixel data into frame buffer pixel data where the frame buffer pixel data is formatted, according to a frame buffer format defining the ordering and width of a set of frame buffer components, as a set of frame buffer component values.

Abstract: An interface control apparatus for a frame buffer including a byte swapping/sampling controller connected between the PCI host bus and a FIFO (First In First Out) for performing a data conversion between a big Endian data and a little Endian data or a data conversion between a system data and a user data, a byte conversion/view selection controller connected between the FIFO and the SRAM for converting a pixel data stored in the FIFO from a 8 bit-1 byte data to a 9 bit-1 byte data in accordance with a view selected or converting a pixel data stored in the SRAM from a 9 bit-1 byte data into a 8 bit-1 byte in accordance with a view selected, a RAC for controlling a transmission of a pixel data between the SRAM and the RAM but DRAM, and a display controller for receiving a pixel data outputted from the RAM bus DRAM through the RAC and outputting to the RAMDAC through the display bus, for thereby concurrently performing a pixel data conversion between a big Endian and a little Endian and a pixel data conversion f