Abstract: A system and method for increasing effective bus bandwidth in communicating with a graphics device. Graphics commands and associated parameters are written into a contiguous region of system memory and transmitted in a weakly ordered fashion over a bus to a graphics device. The graphics device reorders the incoming data into the same order as which the data was written into the contiguous region of system memory, thereby allowing the use of order dependent encoded commands with the weakly ordered bus interface.

Abstract: A method and apparatus for managing texture mapping data in a computer graphics system, the computer graphics system including a host computer, primitive rendering hardware and a primitive data path extending between the host computer and the primitive rendering hardware. The host computer passes primitives to be rendered by the system to the primitive rendering hardware over the primitive data path. The host computer has a main memory that stores texture mapping data corresponding to the primitives to be rendered. The primitive rendering hardware includes a local texture memory that locally stores the texture mapping data corresponding to at least one of the primitives to be rendered. When a primitive passed to the primitive rendering hardware is to be rendered, a determination is made as to whether its corresponding texture mapping data is in the local texture memory.

Abstract: In a data transfer circuit, a hold signal generating circuit generates and outputs a hold signal Hold when transmission data is equal to transmission data one cycle before, and sets a 3-state output buffer for transmission data to high-impedance state, while, in a data reception circuit, when the hold signal Hold is valid, a data reception circuit outputs the reception data held, thereby power consumption in a data bus which is terminated with a terminal resistor is reduced.

Abstract: An internal memory section is divided into plural memory blocks. During a period of time, a relevant memory block of the internal memory section is connected to an external memory unit, while another memory block thereof is connected to a data holding section. During a succeeding period of time, the relevant memory block is connected to the data holding section, while the other memory block is connected to the external memory unit. Data exchange between the data holding section and the external memory unit via the internal memory section is performed while the alternative connection is repeated.

Abstract: A graphic processing apparatus for generating, displaying or printing characters and graphic data. A successive column access is used in which a row address is designated for access to a memory and data in different column addresses within the designated same row address are successively accessed and buffer means for buffering a series of data between an access by a processor and an access to a memory is provided. A program and image information for display are stored in a main memory. A frame buffer and the main memory are integrally configured simply and small in size.

Abstract: A method of providing text data for display in a processor controlled apparatus comprised of storing data defining a text character in a memory, in packed monochrome bit map form, addressing the memory to read the text character data, providing the text character to a graphics processor circuit, performing a bitblt operation on each bit of the text character while providing a color attribute, and storing the packed text character having a color attribute for subsequent display.

Abstract: In a rendering processing system having a rendering memory for storing rendering pixel data generated by a rendering operation circuit and a display memory for storing the image data of a current frame read out from the rendering memory, the display memory stores only the pixel data read out from the rendering memory with prescribed information excluded therefrom. Thus, it is possible to decrease the storage capacity of the display memory and also reduce the time required for writing data into the display memory.

Abstract: A method for storing mip map series in a multi-bank texture memory is disclosed. Each mip map has a different size and represents a different resolution version of a texture map image that is to be mapped onto a three dimensional object comprising one or more polygons. To prevent page faults when accessing corresponding texels in consecutive mip maps, each mip map is divided in two halves. The halves are stored in different banks of the multi-bank texture memory. The banks used are alternated so that corresponding texels in consecutive mip maps are stored in different memory banks. Mip maps may be categorized as large or small, with all small mip maps after the first being stored in their entirety in one memory bank. Small mip maps are those that are equal to or smaller than the page size of the multi-bank texture memory. A computer system, graphics subsystem, and software program capable to efficiently store mip map series in a multi-bank texture memories are also disclosed.