Abstract: An LCD device and a method for driving the device reduces power consumption by transmitting data by using at least two clock signals having different phases. The LCD device displays a picture image by driving an LCD panel that includes multiple source drivers applying data signals to the LCD panel. Multiple gate drivers apply gate driving signals to the LCD panel, a timing controller outputs at least two clock signals having different phases and separately outputs data synchronized with each output signal, and at least two data buses transmit the data separately output from the timing controller to the source drivers. The method for driving the LCD device includes outputting at least two clock signals having different phases, and separately outputting the digital data synchronized with respective clock signals per odd/even numbered data or R/G/B display data through different data buses.

Abstract: A liquid crystal display panel driving circuit includes a plurality of data signal lines, a plurality of data lines, a plurality of data switches, each data switch connecting at least one data signal line to the plurality of data lines, a plurality of pixels, a plurality of pixel switches connecting a data signal transmitted on each data line to at least one of the pixels, and a plurality of capacitors, each capacitor connected to at least one of the data lines for storing a voltage corresponding to the data signal transmitted by one of the data switches and for transmitting the voltage to one of the pixels.

Abstract: A gate driving circuit in a liquid crystal display is disclosed which can minimize a power consumption by avoiding unnecessary drive of gate line drivers. The gate driving circuit is used in a liquid crystal display having a liquid crystal panel with thin film transistors and pixel electrodes for displaying an image, a source driving circuit for applying video data to a source line in the liquid crystal panel, and a gate driving circuit for applying a driving signal to a gate line in the thin film transistors. The gate driving circuit includes a plurality of gate line drivers connected in series for applying the driving signal to the gate line, and a plurality of clock generation controlling units corresponding to the plurality of gate line drivers each for controlling a timing of a clock signal to a respective gate line driver, thereby controlling a driving timing of the respective gate line driver.

Abstract: A technique is described for driving a liquid crystal display device having a liquid crystal layer exhibiting a cholesteric phase and switchable between a planar state and a focal conic state according to the magnitude of an applied voltage. The technique comprises the steps of: in a first period, simultaneously applying a voltage by which a plurality of pixels arranged in a matrix array are reset to the focal conic state; in a second period after the first period, sequentially applying voltages corresponding to image data to the pixels, thereby updating the display contents of the pixels; and in a third period after the second period, retaining the display state by utilizing memory characteristics of the liquid crystal.

Abstract: A video signal generator comprises a frequency divider (5), connected to the pixel oscillator (4) to deliver a width-modulated control signal (Ftr) at a lower frequency than, but synchronized with, the pixel signal. A local pixel synchronizing signal generator (14) includes a PLL-loop provided, in succession, with a first division stage (10) and with a second division stage (11) which bring the pixel frequency (fpx) down to the line frequency (ftr). Between the first division stage (10) and the second division stage, the signal is fed into a divider (12) whose output is connected to the clock input (Cp) of a D-type flip-flop, the input D of which is connected to the control signal (Ftr) and the output (Q) of which delivers a signal (Fpwm) for adjusting the screen.

Abstract: A liquid crystal display having a signal line for driving gate driver IC in panel is provided. The liquid crystal display comprises: a gate driving power supply unit for supplying analog signals; a control circuit unit for applying control signal to analog signal outputted from the gate driving power supply unit; a correction circuit unit for applying control signal from the control circuit unit to correct analog signal outputted from the gate driving power supply unit into a saw type; and a corrected power supply unit for supplying saw type signals corrected in the correction circuit unit to the gate driver IC.

Abstract: A liquid crystal display (LCD) having a matrix of liquid crystal pixels is provided. A plurality of digital-to-analog converters (DACs) are coupled to the LCD matrix through analog voltage switches and are adapted to produce output voltages that are applied to the pixels in the LCD matrix. Through the combination of DACs and analog voltage switches, groups of pixels are pre-written to an average value of the pixels in that group which is fairly close to their final voltage values of each pixel so that the liquid crystal material can begin slewing and settling as early as possible. Then one or more writes to each of the pixels is made of the precise voltage value desired at each of the pixels. Alternate, adjacent odd and even rows of pixels may be written together and then only the even or odd rows are finally written to obtain the desired final voltage values at each of the pixels in the LCD.

Abstract: A driving system of an liquid crystal display (LCD) device and an LCD driving method in which an insufficient charging of a liquid crystal capacitor caused by a delayed time taken for raising source and gate signals applied to each pixel of the LCD panel to normal voltage levels is overcome by delaying the source signal output by a predetermined number of source driver IC units or by delaying the gate signal that is output by a predetermined number of gate driver IC units, includes a power supply unit, a controller, a gray voltage generating unit, a gate voltage generating unit, a source drive unit, a gate drive unit, and a liquid crystal panel, wherein the source drive unit or the gate drive unit has a delay unit for delaying an enable signal or a load signal, to thereby output delayed source and gate signals.

Abstract: A driver circuit can be used to drive a matrix display device, such as a liquid crystal display, that includes a plurality of pixels 16 disposed in rows 12 and columns 14. A first switch 328 has a current path coupled between a high voltage node (e.g., VS) and a group of pixels 16. As an example, the group of pixels 16 can be a row 12 or a column 14. A second switch 326 has a current path coupled between a low voltage node (e.g., ground) the group of pixels 16. A third switch 322 has a current path coupled between an inductive storage element 34 and the group of pixels. The inductive storage element 34 is coupled to an intermediate voltage node (e.g., VS/2) with a voltage between the voltage at the high voltage node and the voltage at the low voltage node.

Abstract: Power consumption in driving ICs for electro-optical devices is reduced by driving all pixels in a frame to one extreme state and then introducing intermediate levels (grey-levels, colours) by multiplexing, using a reduced selection pulse width. In this way the number of level transitions for the extreme states and hence power dissipation is reduced.

Abstract: Wiring between output terminals of a source driver IC (output terminals of a TCP for source driver IC) and picture elements is equalized when number of the picture elements is not an integer multiplied by number of outputs of the source driver IC in the liquid crystal display. By giving a start pulse for indicating a start timing of drive sections to a predetermined drive section at a timing different from an originally set start timing, a part of output terminals of the drive section is made unavailable.

Abstract: A control unit includes sample-and-hold circuits, their associated switching circuits and a switch controller. Each of the sample-and-hold circuits includes a switch. The switch controller sequentially outputs switch control signals one after another to the sample-and-hold circuits. For example, at a point in time data has been sampled and held in a first one of the sample-and-hold circuits, a first one of the switching circuits outputs a CLOSED signal to a second one of the switching circuits via a signal line. The second switching circuit does not output the switch control signal, received from the switch controller, to a second one of the sample-and-hold circuits until the second switching circuit receives the CLOSED signal from the first switching circuit. Accordingly, while one of the sample-and-hold circuits is sampling and holding the data, none of the other sample-and-hold circuits is allowed to open its switch.

Abstract: A display apparatus includes a display panel and a logic switch unit. The display panel has a plurality of common electrodes and a plurality of segment electrode arranged in a direction orthogonal to the plurality of common electrodes. Display cells are formed at intersections of the plurality of common electrodes and the plurality of segment electrodes. The logic switch unit short-circuits selected at least one of the plurality of common electrodes corresponding to a display cell group and selected ones of the plurality of segment electrodes corresponding to the display cell group in response to a common-segment short-circuit timing signal. The display cell group includes selected ones of the display cells.

Abstract: A liquid crystal display device includes dual bank type source driver PCBs installed at the top and the bottom of a liquid crystal panel, a gate driver PCB, and a staple-shaped main PCB formed in a body with a top portion and a bottom portion proceeding in the horizontal direction and a side portion proceeding in the vertical direction. The top portion and the bottom portion of the main PCB axially meet the side portion of the main PCB at a predetermined angle. A timing controller is mounted at the main PCB to process signals input from outside and generate driving signals. The main PCB transmits the relevant driving signals to the respective source driver PCBs and the gate driver PCB.

Abstract: It is an object of the invention to reduce a leakage low-frequency electric field from a panel section of a matrix type. In the case where a panel section has a usual current structure in which the panel section has a single common electrode elongating over the whole of the display region of the panel section, the maximum voltage difference of a reference signal supplied to the common electrode is defined to be 0.3678×x−0.6136 (wherein x is the area of the display region) or less. In the case where the panel section has the so-called counter source structure and a plurality of column electrodes, the maximum voltage difference of a reference signal supplied to the column electrodes is defined to be ax−b (wherein a=0.3565×y−0.6829, b=−0.0937y+0.7091, and y is a ratio of the area of all the column electrodes to the area of the display region) or less.

Abstract: A liquid crystal display device includes plural pixels supplied with video signal voltages via video signal lines, and a video signal line driver circuit for supplying the video signals voltage to the video signal lines. The video signal line driver circuit includes plural differential amplifiers each having a pair of a first input terminal and a second input terminal and amplifying inputted video signals and supplying the amplified video signal to the video signal lines, a plurality of pairs of an inverting input terminal and a noninverting input terminal each pair corresponding to each of the differential amplifiers.

Abstract: This invention is related to a method for controlling a threshold voltage of a bottom gate type thin film transistor as follows. Gate electrodes and a gate insulating film are formed on a glass substrate. An amorphous silicon film is formed thereon and then crystallized into a crystalline silicon film. After a buffer layer is formed thereon, an impurity element (selected from Group 13 or Group 15 elements) for a threshold voltage control is added to the crystalline silicon film by ion implantation or ion doping.

Abstract: A display apparatus of the active matrix type using a point sequential driving method is disclosed wherein a sufficient writing time can be assured for a pixel on the scanning ending end side in the horizontal direction even where the horizontal blanking period is short to achieve a high picture quality free from shading. Gate lines of a pixel section are cut leftwardly and rightwardly at central portions thereof to form left side gate lines and right side gate lines, and a pair of vertical driving circuits are disposed on the opposite left and right sides of the display section. Scanning pulse signals for the left side are successively outputted from the left side vertical driving circuit and applied to the left side gate lines. Scanning pulse signals for the right side having phases delayed from those of the scanning pulse signals for the left side are successively outputted from the right side vertical driving circuit and applied to the right side gate lines.

Abstract: A mode detection circuits in LCDs is disclosed, comprising: a first mode signal detection means for detecting an enable/synchronous signal mode in response to a vertical synchronous signal and for generating a first mode detection signal; a second mode signal detection means for detecting an enable mode signal based on a data enable signal and a clock signal and for generating a second mode detection signal; a mode selection means for selecting one of a first mode detection signal and a second mode detection signal from the first mode signal detection means and the second mode signal detection means in response to a mode selection signal and for providing the selected mode detection signal as a mode determining signal.

Abstract: A liquid crystal display apparatus and method for displaying a picture different in aspect ratio than the liquid crystal panel. Picture data sampling times are controlled for a first signal electrode driver that drives signal electrodes in a region where a picture different in aspect ratio from the liquid crystal panel is to be displayed and a second signal electrode driver for driving signal electrodes in a region where picture data different in aspect ratio from the liquid crystal panel is not to be displayed. In particular, the starting points of the picture data sampling is controlled in accordance with the picture data's aspect ratio. With the disclosed apparatus and method, it is possible to display a picture different in aspect ratio from the liquid crystal display along with a blanking picture without introducing excessive noise, and the circuit configuration of the liquid crystal display is simplified.

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sx1 in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: An apparatus and method to delay a field of video by one row in a two field frame to reduce DC build-up or stick caused by textual image.

Abstract: An image processing circuit having a delay unit U1 that delays image data Da and outputs image data as image data Db. The delay time of the delay units U1 is equivalent to the unit time of phase-rendered image signals VID1 through VID6. Upon a first difference circuit 31 subtracting image data Db from image data Da, and thus generating first difference image data Ds1, a first coefficient circuit 32 multiplies the first difference image data Ds1 by a first coefficient K1 and generates first correction data Dh1. Corrected image data Dout is generated by adding the image data Da and the first correction data Dh1. Therefore, ghosting is removed in the event of sequentially selecting blocks of batched multiple data lines to make display.

Abstract: A method of processing signals of a timing controller of a liquid crystal display module, wherein the signals are processed according to a rising edge or a falling edge of a synchronizing signal to generate the control signals for the liquid crystal display module, the control signals including start vertical signals STV (including STV1 and STV2) and gate-on enable signals OE. Then, the gate clock signal CPV, STV1, STV2, and OE pause to be outputted.

Abstract: A data transfer method transfers data to an information-side driver for driving a display apparatus. Wherein, driver circuits each comprise a chip address/video data discrimination circuit and a unit driver are mounted around the display apparatus. A unique chip address is set for each of the unit drivers by a hardware pattern. Data exchange with the driver circuits is performed so that chip address information and video data information are time-divisionally transferred to the target unit driver using a chip address/video data common bus line and a chip address/video data discrimination control signal.

Abstract: An LCD source driver having a plurality of driving channels includes a control logic responsive to an internal polarity control signal, a first clock signal and a second clock signal, the control logic being inputted alternately and consecutively with digital video signals of multiple bits including odd channel digital video signals and even channel digital video signals, the control logic generating the odd channel digital video signals and the even channel digital video signals corresponding to a logic value of the internal polarity control signal in one of an inputted order and a reversed order, a shift register being activated successively and outputting a plurality of enabling signals, a latch block having a plurality of latches for receiving the odd channel digital video signals and the even channel digital video signals synchronized by enabling signals, the latch block generating simultaneously the odd channel digital video signals and the even channel digital video signals when the enabling signals ar

Abstract: A rush current preventing circuit for a liquid crystal display that is suitable for eliminating a rush current at the time of applying an initial power to the liquid crystal display includes an output enable signal generator generating an output enable signal to control outputs of the gate drive integrated circuits. A start output enable signal generator generates a start output enable signal having at least a desired interval of disable pulse at the time of applying an initial power. An output enable signal switching device switches the output enable signal and the start output enable signal in accordance with the start output enable signal.

Abstract: TFT-LCD devices having improved data line driver circuits therein comprise an follower amplifier which drives a data line of a panel “hard” during a first portion of a selection time interval (when a strong pull-up or pull-down is required) and a transmission gate which performs a “soft” pull-up or pull-down of the data line to a desired gray level voltage during a second portion of the selection time interval. The “soft” pull-up or pull-down can be utilized to reduce the offset margins of gray level voltages to within ±5 mV.

Abstract: A liquid crystal display device comprising a start pulse generation circuit which gives the timing for displaying a received image in a fixed position on a liquid crystal display panel, another start pulse generating circuit which gives the timing for displaying the received image in a specified position on the liquid crystal display panel in response to enable signal indicating an effective display data period concerning the received image from the outside, and selectors which select one of these circuits in response to a select signal. The liquid crystal display device according to this present invention has a data enable signal detection circuit which detects the data enable signal and outputs the result to the selectors as the select signal.

Abstract: To provide an optical spatial modulation device capable of rewriting an image with a high degree of efficiency and implementing a very fast response speed and an extremely high intensity, and to provide an image display apparatus employing the optical spatial modulation device. Created for each pixel of an optical spatial modulation device are a 1st memory for storing pixel data of an image to be displayed, a 2nd memory to which the pixel data stored in the 1st memory is transferred and a driving means driven in accordance with the pixel data transferred to the 2nd memory to change the optical transmissivity, the optical reflectance or the polarization state of the pixel. When displaying an image, first of all, pixel data is stored in the 1st memory of each of all pixels composing the image. Then, the pixel data is transferred from the 1st memory to the 2nd memory.

Abstract: A driving circuit for driving a liquid crystal display is provided. The driving circuit includes a clock generator processing a first clock signal to output a second clock signal, the clock speed of the second clock signal being half of that of the first clock signal, a memory for storing a first video data and a second video data in accordance with the first clock signal, and a data controller for simultaneously outputting the first video data and the second video data stored in the memory in accordance with the second clock signal.

Abstract: The present invention provides a driving circuit for providing display signals to a liquid crystal display panel through a plurality of data lines.

Abstract: A liquid crystal display device having a plurality of row electrodes to which a scanning voltage is applied; a plurality of column electrodes provided so as to cross the plurality of row electrodes, to which a display data voltage is applied; and a liquid crystal layer interposed between the plurality of row electrodes and the plurality of column electrodes, which provides a display function at intersections between the plurality of row electrodes and the plurality of column electrodes in response to a RMS value of a voltage applied between the plurality of row electrodes and the plurality of column electrodes, includes: a section for outputting a display data signal representing the display data voltage having three or more voltage levels; a compensation circuit for outputting a compensation data signal based on a RMS value difference between the display data voltage and a respective resultant display data voltage applied to the plurality of column electrodes; and a driving circuit for applying a compensatio

Abstract: A ramp voltage-generating circuit initially outputs the maximum voltage VH or the minimum voltage VL to be applied to a liquid crystal synchronizing with a ratch pulse and a clock II. In case that the maximum voltage VH is outputted initially, the output voltage of the ramp voltage-generating circuit decreases slowly with the passage of time in a predetermined period. In case that the minimum voltage is outputted initially, the output voltage of the ramp voltage-generating circuit increases slowly with the passage of time in a predetermined period. The output voltage of the ramp voltage-generating circuit keeps VH in the period T3, slowly decreases in the period T4, and keeps V0 in the period T5. In a LCD provided with the ramp voltage-generating circuit mentioned in the above, a voltage impressed upon the pixel electrode of a TFT for driving the liquid crystal follows an input voltage of a data bus line quickly, and a contrast of a picture can be prevented from being deteriorated.

Abstract: A display apparatus for displaying video information by superimposing a plurality of images obtained through a plurality of display systems, each being constituted by a light source, a reflection type liquid crystal panel and an optical system, characterized in that the apparatus comprises at least either of system selection means for selecting at least one of the plurality of display systems and modifying means for modifying the attributes of the image obtained through one of the display systems.

Abstract: The present invention is concerned with a PLL comprising the phase comparator 20, loop filter 21, VCO 14 and loop counter 22, wherein there are further provided a prediction window circuit 23 for outputting HWIN (prediction window signal) for predicting the point at which the REF (reference signal) is generated, an omission compensation circuit 24 for detecting the omission of the REF at the time when HWIN is outputted and outputting d.VARX (the second correction signal) to offset the phase difference between d.REFX (the first correction signal) and the VAR (comparison signal) so that the phase comparator 20 outputs the signals Ph1 and Ph2 corresponding to the phase difference between the VAR and the d.REFX and the signals Ph1 and Ph2 corresponding to the phase difference between d.REFC and d.VARX when the omission of the REF has occurred, thereby enabling proper compensation for omission to be made and stable CLK (clock) to be generated even when VCO 14 having a very wide frequency variation range is used.

Abstract: A flat panel display controller is provided with a circuit for monitoring clocking signal(s) to the flat panel display. A clocking signal output to the flat panel display may be fed back to the display controller using a conventional I/O pad. In the preferred embodiment, the fed back clocking signal resets a counter. In a second embodiment, the fed back clocking signal may then pass through an edge detector whose output then resets the counter. The counter will overflow if a edge signal is not received within a predetermined time period. If an overflow occurs, the carry signal of the counter will initiate a flat panel power shutdown through power control circuitry. The clock signal for the counter may be derived from an off-chip oscillator such that if a failure occurs within the display controller, the counter will continue to function.

Abstract: A method and circuit generates a sampling clock signal that digitizes an analog video signal. The sampling clock signal is generated by a clock divider coupled to the horizontal synchronization signal of the analog video signal. A divisor calculator calculates a divisor for the clock divider to control the frequency of the sampling clock signal. Specifically, the divisor calculator selects an initial divisor for the clock divider. Then the divisor calculator calculates a new divisor based on the target pixel value provided by a mode detector and the measured pixel value from a counter. Some embodiments of the present invention fine tune the frequency by testing other possible divisors with a plurality of different phases. In addition, some embodiments of the present invention calibrate the phase of the sampling clock signal to generate a phase shifted sampling clock signal.

Abstract: An image displaying device comprises a display panel including display pixels connected to signal lines signal line driving circuit sections for sampling a video signal including effective video periods and blanking periods between effective video periods to produce pixel signal voltages and supplying the voltages to the signal lines for each of the horizontal scanning lines a drive timing select circuit section for selecting one of a first timing and a second timing in the blanking period of the video signal and a polarity inverting circuit section for inverting the video signal in polarity with respect to a reference voltage on the basis of a selected one of the first and second timing, wherein the drive timing select circuit section is arranged such that each of the first timing and the second timing is selectable when a pixel signal voltage corresponding to the first video signal is obtained from the video signal and outputted to the signal lines for each of the horizontal scanning lines.

Abstract: A liquid crystal display driver periodically changes common signal lines selectively connected to pixels of a liquid crystal display panel to active level for sequentially supplying segment signals representative of a piece of image to the selected pixels, and bypassing paths are incorporated in the liquid crystal display driver so as to transfer electric charge accumulated on a presently selected common signal line to the next common signal line to be selected, thereby reducing electric power consumption.

Abstract: An object of the present invention is to perform precise A-D conversion of analog video signal in a liquid crystal display monitor, without increasing a transmission line: to attain this object, a horizontal dividing signal synthesizing circuit of a graphics card superposes a horizontal dividing signal synchronized in phase with a clock for D-A conversion of the analog video signal on a horizontal sync signal, to obtain a second horizontal sync signal, to be outputted; a sync signal isolating circuit of the liquid crystal display monitor isolates the horizontal dividing signal and horizontal sync signal from the second horizontal sync signal; the PLL generates an A-D conversion clock synchronized with the horizontal dividing signal.

Abstract: A duty cycle alteration circuit can simply alter a duty cycle of a pulse by using a Schmitt circuit in a monitor. The duty cycle alteration circuit includes: a microcomputer for outputting a waveform amplifying ratio control signal; an amplifying circuit for inputting and amplifying the waveform amplifying ratio control signal outputted by the microcomputer or a triangular wave and for outputting an amplified triangular wave; and a Schmitt circuit for establishing a logic “high” level and a logic “low” level centering around a reference level according to the amplified triangular wave supplied from the amplifying circuit and for changing a duty cycle on the basis of the logic “high” and “low” levels and for outputting a rectangular wave having an altered duty cycle.

Abstract: There is provided a liquid crystal display control device which can display pictures in a magnification mode by using only a memory having low-speed access and a low storage capacity. When a video signal has intermediate resolution or less, the enlargement processing is performed by a frame memory, a line memory and an enlargement processing control circuit. If the input operation and the output operation to and from the frame memory are synchronized with each other, it is sufficient for the frame memory to have a storage capacity of two lines. When the video signal has the same high resolution as a liquid crystal display panel, the video signal is output through a gate circuit to a display timing generating circuit, and it is displayed in a through mode. In this case, no processing is performed by the frame memory or the like.

Abstract: A shift register unit has stages. In each stage, a clamping transistor and the control electrode of an output transistor are connected to the output electrode of an input transistor to which an output one stage behind is input. A pull-down resistor is connected to the output electrode of the output transistor. A capacitor is inserted between the control electrode and output electrode of the output transistor. A clock signal is input to the output transistor, and a signal obtained by inverting a clock signal two stages forward is input to the clamping transistor.

Abstract: A driving circuit has a plurality of sample and hold circuits which are connected to data buses of a liquid crystal display panel. The data buses are divided into a plurality of groups. Each of the groups receives a picture signal to drive the data buses. A timing controller controls operation timing of the groups in response to a synchronizing signal and a clock signal to control each of the groups independently of one another.

Abstract: A delay detecting section detects the phase difference between a first detection signal as a reference and a second detection signal produced by delaying the first detection signal with part of a data signal line driving circuit itself or part of a circuit formed by the same process as the data signal line driving circuit. A phase adjusting section presumes an internal delay of the data signal line driving circuit, and adjusts the phase difference between a clock signal and start signal, and a video signal so that the data signal line driving circuit samples the video signal at an appropriate timing. These structures prevent a lowering of the image quality due to a difference in the timings of the video signal and sampling signal, and provide an image display device capable of displaying a good-quality image with a simple circuit structure.

Abstract: Image data resulting from a digitizing process, for display of an image on a digital display device, is monitored by selectively storing the data in diagnostic registers. This data is analyzed, and used to track the performance of the digitizer on the basis of various operating parameters such as inter-channel balance, intra-channel balance, contrast, brightness, white point, image centering and data clock. A communication channel from the image source provides information regarding the content of the image data being monitored. Based upon the indicated content provided by the image source, the system automatically compensates for any detected error, to thereby maintain optimum performance.

Abstract: A display apparatus includes a plurality of scanning lines to which a plurality of scanning signals are inputted, respectively and a plurality of signal lines to which a plurality of display signals are inputted, respectively and a plurality of capacitance sections respectively provided through a plurality of switching elements at a plurality of intersections of the plurality of scanning lines and the plurality of signal lines, and a display section including the plurality of capacitance sections. The display section is divided into first and second display regions by a virtual line parallel to at least one of the plurality of scanning lines. The plurality of scanning signals are inputted at first intervals to a first group of the scanning lines corresponding to the first display region of the plurality of scanning lines.

Abstract: The display device has a driving circuit provided with a pulse generator for generating a copying clock pulse signal within one horizontal period in addition to an original clock pulse signal upon an enlargement display, a gate clock generator for generating a gate clock signal obtained by superimposing the total original clock pulse signal and the copying clock pulse signal corresponding to a number obtained by subtracting the number of vertical pixels of a video signal from the number of vertical pixels of a display unit, and a gate driver for generating a plurality of gate driving signals brought to high levels with different timings in association with respective pulses in the gate clock signal and having high level periods equal in length to one another.

Abstract: An active matrix display device includes a plurality of gate lines and a plurality of data lines, which are arranged in a screen so as to be mutually perpendicular, and pixels arranged at the intersections of both lines, which are selectively driven via the gate lines and the data lines. Also, a vertical driving circuit is disposed outside the screen, and outputs selection pulses sequentially selecting each gate line. In addition, a horizontal driving circuit is similarly disposed outside the screen, and outputs selection pulses sequentially selecting each data line. This horizontal driving circuit includes an address counter for counting the number of clock signals inputted from the exterior and sequentially outputting an address signal, and a plurality of decoders for decoding the address signal and sequentially outputting the selection pulses.