Abstract: According to one embodiment, a solid-state imaging device includes a pixel region which is configured such that a photoelectric conversion unit and a signal scanning circuit unit are included in a semiconductor substrate, and a matrix of unit pixels is disposed, and a driving circuit region which is configured such that a device driving circuit for driving the signal scanning circuit unit is disposed on the semiconductor substrate, wherein the photoelectric conversion unit is provided on a back surface side of the semiconductor substrate, which is opposite to a front surface of the semiconductor substrate where the signal scanning circuit unit is formed, and the unit pixel includes an insulation film which is provided in a manner to surround a boundary part with the unit pixel that neighbors and defines a device isolation region.

Abstract: Providing for pausing data readout from an optical sensor array is described herein. By way of example, an interruption period can be introduced into a readout cycle of the optical sensor array to suspend readout of data. During the interruption period, other operations related to the optical sensor array can be performed, including operations that are typically detrimental to image quality. Moreover, these operations can be performed while mitigating or avoiding negative impact on the image quality. Thus, greater flexibility is provided for global shutter operations, for instance, potentially improving frame rates and fine control of image exposure, while preserving image quality.

Abstract: A driving circuit includes first through N-th selective operation driving portions selectively producing first through N-th selective operation driving signals, a selection circuit selectively driving the first through the N-th selective operation driving portions in response to an input signal and a control signal, and a supplying arrangement combining the first through the N-th selective operation driving signals to supply a combined driving signal to a solid-stage image pickup device. An n-th selective operation driving portion includes (M×2(n-1)) P-channel FETs connected in parallel with each other and (M×2(n-1)) N-channel FETs connected in parallel with each other. The (M×2(n-1)) P-channel FETs have drains connected to drains of the (M×2(n-1)) N-channel FETs.

Abstract: To avoid reset noise in a CMOS chip for direct particle counting, it is known to use Correlative Double Sampling: for each signal value, the pixel is sampled twice: once directly after reset and once after an integration time. The signal is then determined by subtracting the reset value from the later acquired value, and the pixel is reset again. In some embodiments of the invention, the pixel is reset only after a large number of read-outs. Applicants realized that typically a large number of events, typically approximately 10, are needed to cause a full pixel. By either resetting after a large number of images, or when one pixel of the image shows a signal above a predetermined value (for example 0.8 × the full-well capacity), the image speed can be almost doubled compared to the prior art method, using a reset after acquiring a signal.

Abstract: A solid-state imaging device includes a photoelectric conversion layer, a MOS transistor circuit. The photoelectric conversion layer is formed over a semiconductor substrate. The MOS transistor circuit reads out a signal corresponding to charges generated in the photoelectric conversion layer and then collected, and that is formed in the semiconductor substrate, the charges having a given polarity. The MOS transistor circuit includes a charge accumulation portion, a reset transistor, and an output transistor. The charge accumulation portion is electrically connected with the photoelectric conversion layer. The reset transistor resets a potential of the charge accumulation portion to a reset potential. The output transistor outputs a signal corresponding to the potential of the charge accumulation portion. The reset transistor and the output transistor have carriers whose polarity is opposite to the given polarity.

Abstract: A CCD image sensor includes vertical CCD shift registers and gate electrodes disposed over the vertical CCD shift registers. The gate electrodes are divided into distinct groups of gate electrodes. The CCD image sensor is adapted to operate in an accumulation mode and a charge transfer mode, an accumulation mode and a charge shifting mode, or an accumulation mode, a charge transfer mode, and a charge shifting mode. The charge transfer mode has an initial charge transfer phase and a final charge transfer phase. The charge shifting mode has an initial charge shifting phase and a final charge shifting phase.

Abstract: An apparatus configured to match an input frame rate of a video stream with an output frame rate of an output stream, the apparatus comprising, at least one memory buffer, an output frame generator, and a threshold measurement unit, the threshold measurement unit configured to generate a control feedback, wherein the box is configured to analyze the control feedback to monitor a state of the at least one memory buffer, the threshold measurement unit further configured analyze the control feedback to regulate between two or more different settings, wherein the two or more different settings include slowing down or speeding up the output frame, wherein the two or more different settings further include slowing down or speeding up of the line rate of the output stream.

Abstract: An image sensing device includes a first circuit unit configured to convert an image signal provided from a first pixel into a digital value and generate first image data, a second circuit unit configured to convert an image signal provided from a second pixel into a digital value and generate second image data, and a processing unit configured to receive the first image data and the second image data at a substantially same time and sequentially output the first image data and the second image data according to a predetermined speed.

Abstract: A solid-state image capture device includes; a solid-state imaging element having output portions configured to output signals read from pixels; samplers provided for the respective output portions and configured to sample the signals output from the output portions of the solid-state imaging element; and a controller configured to vary, at the samplers, sampling timings at which the samplers sample the signals or to vary, at the output portions, output characteristics with which the output portions output the signals read from the pixels.

Abstract: A method of increasing dynamic range of pixels in an imaging sensor is disclosed. In one aspect, two image captures are performed, one at a first short integration time and one at a second optimum integration time. An electrical value obtained from a pixel or group of pixels at the first short integration time is used to predict the second integration time using a comparison with a set of reference values. The reference values relate to a saturation electrical value for each pixel or group of pixels to predict the second integration time. The first short integration time is determined as a fractional multiple of the saturation electrical value. The second integration times are such that there is no saturation of the pixel or group of pixels. Adjustments can be made to the reference values to allow for offset immunity and variability in light levels during the second integration time.

Abstract: Apparatus and a method for performing neutral density filtering in a digital camera. The camera includes a pixel array having rows and columns of pixels. The pixels in the array may be reset and read with variable timing between the reset operation and the read operation. The timing between the reset and read operations is controlled to implement a neutral density filtering operation.

Abstract: A column circuit for an image sensor includes a first column read circuit configured to read data of a first column line, and a second column read circuit configured to read data of a second column line, wherein, during a binning mode, data from two or more pixels are outputted through the first column line and stored in the first column read circuit in a first phase, data from two or more pixels are outputted through the second column line and stored in the second column read circuit in a second phase, and charges are shared between the first column read circuit and the second column read circuit in a third phase.

Abstract: A solid-state imaging including a comparing circuit, an inverting circuit, and a masking circuit, and that performs column parallel AD conversion processing of analog pixel signals output from a plurality of pixels arranged in a two-dimensional matrix form. The comparing circuit outputs a difference signal obtained by comparing each of the pixel signals outputted from the pixels with a reference signal having a ramp waveform. The inverting circuit inverts a logic of the difference signal outputted from the comparing circuit. The masking circuit masks an output of an output signal of the inverting circuit to a circuit in a subsequent stage during an input offset canceling period in which the comparing circuit cancels an input offset between the pixel signal and the reference signal.

Abstract: In a driving method of device having plural pixels, each pixel comprises photoelectric converter, floating diffusion, transfer transistor to transfer charge of the photoelectric converter to the floating diffusion, amplifying transistor to amplify signal based on the transferred charge, and reset transistor to reset voltage of the floating diffusion, the method comprises first step of, after putting the transfer transistor into conduction state, resetting the charge of the photoelectric converter by putting the transfer transistor into non-conduction state in non-conduction state of the reset transistor, and second step of, after the first step and after putting the transfer transistor into the conduction state, transferring the charge of the photoelectric converter to the floating diffusion by putting the transfer transistor into the non-conduction state in the non-conduction state of the reset transistor, and the signal based on the charge transferred in the second step is amplified by the amplifying transi

Abstract: A CCD image sensor includes vertical CCD shift registers and gate electrodes disposed over the vertical CCD shift registers. The gate electrodes are divided into distinct groups of gate electrodes. The CCD image sensor is adapted to operate in an accumulation mode and a charge transfer mode, an accumulation mode and a charge shifting mode, or an accumulation mode, a charge transfer mode, and a charge shifting mode. The charge transfer mode has an initial charge transfer phase and a final charge transfer phase. The charge shifting mode has an initial charge shifting phase and a final charge shifting phase.

Abstract: An electric camera includes an image sensing device with a light receiving surface having N vertically arranged pixels and an arbitrary number of pixels arranged horizontally, N being equal to or more than three times the number of effective scanning lines M of a display screen of a television system, a driver to drive the image sensing device to vertically mix or cull signal charges accumulated in individual pixels of K pixels to produce, during a vertical effective scanning period of the television system, a number of lines of output signals which corresponds to 1/K the number of vertically arranged pixels N of the image sensing device, K being an integer equal to or less than an integral part of a quotient of N divided by M, and a signal processing unit having a function of generating image signals by using the output signals of the image sensing device.

Abstract: A read out operation for reading out image data from a conversion circuit irradiated with a radiation, and a read out operation for reading out offset image data from the conversion circuit without irradiated with a radiation are selectively conducted, a control is conducted to repeat at a plurality of times the operation for reading out the offset image data, offset data corresponding to each pixel is extracted from one of the plurality of the offset image data to generate corrective offset image data such that offset data corresponding to all the pixels in a row of the matrix is not extracted from one of the plurality of offset image data, and the corrective offset image data is subtracted from the image data to perform an offset correction to render line noise less noticeable, for an offset correction without line noise by a simple signal processing to be provided.

Abstract: A solid-state imaging apparatus of a dynamic range enlarged by reading out a carrier accumulated in a carrier accumulation unit at a plurality of times during a single carrier accumulation time period.

Abstract: A blinking-signal device 1 includes a light receiving section 10, a row selecting section 20, a readout section 30, a detecting section 40, and a control section 50. By the row selecting section 20, charge generated in its photodiode of each pixel unit P2i-1,n of the (2i?1)-th row in the light receiving section 10 is accumulated in its charge accumulating section during a first period, and charge generated in its photodiode of each pixel unit P2i,n of the 2i-th row in the light receiving section 10 is accumulated in its charge accumulating section during a second period. With the detecting section 40, it is detected whether or not light reaching the pixel units P2i-1,n and P2i,n is a blinking signal on the basis of a difference between data D2i-1,n and D2i,n of the pixel units P2i-1,n and P2i output from the readout section 30.

Abstract: An adjacent color difference data generator calculates a differential between adjacent data in a data row having different color information per pixel of the digital signal to thereby generate a first color difference data having a first code format. A code converter converts the first color difference data into a second color difference data having a second code format. The second code format is a code format where only a small number of bits change before and after the code conversion from the first code format. The number of changing bits in the switching between codes when, for example, an image monochromatic but having gradation change is imaged to reduce any noise generated when digital image data is outputted.

Abstract: An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. An analog front end (AFE) circuit processes pixel data output from the output circuits and an AFE clock controller transmits an AFE clocking signal to the AFE circuit to effect processing of the pixel data. A timing generator outputs a column address sequence that is received by a column decoder. During one or more sample operations the timing generator suspends the column address sequence and subsequently during the one or more sample operations the AFE clock controller suspends the AFE clocking signal. The AFE clocking signal and the column address sequence resume at the end of the one or more sample operations.

Abstract: A focus detection apparatus includes: an image sensor that has a first pixel group which receives a luminous flux passing a first pupil area of an imaging optical system, and a second pixel group which receives a luminous flux passing a second pupil area different from the first pupil area; a storage unit that stores first and second distribution functions corresponding to the first and second pupil areas, respectively; a calculation unit that generates a first image signal by performing calculations on a first subject image, obtained from the first pixel group, using the second distribution function, and generates a second image signal by performing calculations on a second subject image, obtained from the second pixel group, using the first distribution function; and a focus state detection unit that detects a focus state of the imaging optical system based on the first and the second image signals.

Abstract: Timing generators and methods of generating timing signals are disclosed. In one implementation, a timing generator for an imaging device includes a timing generator memory configured to store timing information, a timing core coupled to the timing generator memory and configured to read the timing information from the timing generator memory, and a processor core coupled to the timing core and configured to control a plurality of counters. The timing core can be further configured to generate a plurality of timing patterns based on the timing information and the plurality of counters. The timing generator can also be configured to generate a plurality of toggle positions for a plurality of timing signals based on the plurality of timing patterns.

Abstract: This disclosure describes: (1) two different schemes to enhance dynamic range, (2) a new motion detection scheme using in-pixel digital storage, and (3) the motion detection in high illumination for CMOS image sensors. The schemes may be implemented in a small pixel size and easily incorporated in simple column-level circuits for existing CMOS image sensor systems.

Abstract: In an imaging apparatus which subjects signal electric charges of photodiodes of IT-CCD for interlaced scanning of 1080 effective scanning lines to vertical pixel addition to be read out as image signals, at least one of vertical transfer at the last horizontal period and horizontal transfer at half period in reading of pixels is stopped while fixing pairs of vertical pixels to be subjected to vertical pixel addition to be read out as image signals of progressive scanning of 540 effective scanning lines from the CCD and the read-out image signals of 540 effective scanning lines are subjected to scanning line conversion of 3 to 4 to be converted into image signals of progressive scanning of 720 effective scanning lines, the image signals of progressive scanning of 720 effective scanning lines being outputted.

Abstract: An image capture apparatus includes an image sensor, a determination unit which determines one image capturing mode, a driving unit which drives the image sensor by different driving methods in the respective image capturing modes, and a control unit which controls the operation of the driving unit. The image sensor includes a plurality of two-dimensionally arrayed pixels, a predetermined number of vertical output lines arranged for each array of pixels, and a holding memory which holds pixel signals from pixels on rows. The control unit drives the image sensor in the first power save mode when a horizontal transfer period is not less than twice a vertical transfer period, and drives the image sensor in the second power save mode when the vertical transfer period is not less than twice the horizontal transfer period.

Abstract: According to one embodiment, a solid state imaging device has a semiconductor substrate. First, second and third photoelectric conversion portions are provided in a surface region of the semiconductor substrate. A blue color filter has a film thickness to give a first light path length. A green color filter has a film thickness to give a second light path length longer than the first light path length. A red color filter has a film thickness to give a third light path length longer than the second light path length. A flattening film is formed on the blue color filter, the green color filter and the red color filter. The flattening film flats steps of the color filters. Micro lenses are provided on the flat film. Each of the micro lenses is formed at a position corresponding to each of the first, second and third photoelectric conversion portions.

Abstract: The present invention relates to improved imaging devices having high dynamic range and to monitoring and automatic control systems incorporating the improved imaging devices.

Abstract: Provided is a solid-state imaging apparatus comprising signal lines to each of which a signal is outputted from each of pixels, a first holding capacitor for holding the signal outputted from each of the signal lines, first CMOS switches arranged between the signal lines and the first holding lines, each of the first CMOS switches including a first NMOS transistor and a first PMOS transistor, a first control line commonly connected to the gates of the first NMOS transistors of the first CMOS switches, and a second control line commonly connected to the gates of the first PMOS transistors of the first CMOS switches, and signals of different timings are supplied to the first control line and the second control line such that a timing of turning off the first NMOS transistor is shifted from a timing of turning off the first PMOS transistor.

Abstract: An image sensing apparatus has an image sensor including two-dimensionally arranged photoelectric conversion elements, a VCCD for transferring in a vertical direction electric charge accumulated in the photoelectric conversion elements, and a HCCD for transferring in a horizontal direction the electric charge transferred from the VCCD, the image sensor for carrying out transfer of electric charge by the VCCD during transfer of electric charge by the HCCD; a noise reduction unit for reducing noise including noise caused by driving the VCCD from an image signal output from the HCCD; and a control unit for controlling whether or not noise reduction is to be carried out based on at least one of the sensitivity, shutter speed, and temperature of the image sensor.

Abstract: A CCD-type solid-state imaging device includes: light receiving devices arranged in vertical and horizontal directions; vertical transfer parts arranged along vertical rows of the arranged light receiving devices, reading out charge accumulated in the adjacent light receiving devices, and transferring the read out charge in the vertical direction; a horizontal transfer part supplied with the charge transferred in the vertical transfer parts and transferring the supplied charge in the horizontal direction; an output part outputting the charge transferred in the vertical transfer parts; an input terminal for readout and transfer clocks that command readout of the charge from the light receiving devices and transfer of the read out charge in the vertical transfer parts; a resistor connected between the input terminal and a clock supply part of the vertical transfer parts; and a switch part connected to the resistor in parallel and switching between the charge readout and the charge transfer in the vertical trans

Abstract: An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. An analog front end (AFE) circuit processes pixel data output from the output circuits and an AFE clock controller transmits an AFE clocking signal to the AFE circuit to effect processing of the pixel data. A timing generator outputs a column address sequence that is received by a column decoder. During one or more sample operations the AFE clock controller suspends the output of the AFE clocking signal and the timing generator suspends the output of the column address sequence during the sample operation. The output of the AFE clocking signal and the column address sequence resume at the end of the sample operation.

Abstract: In a conventional image pickup apparatus, a plurality of reset methods for resetting a photodiode cannot be set. A row selection unit is provided with a first storage unit for storing an address of a read row, a second storage unit for storing an address of a shutter row, and further a third storage unit for storing an address of a row in which potential of photodiode is fixed.

Abstract: Each of a plurality of unit pixels includes first and second photoelectric conversion units, and a pixel output unit shared between the first and second photoelectric conversion units. A monitoring unit configured to control the charge-accumulation operation of the first photoelectric conversion unit by monitoring a signal generated based on the second photoelectric conversion unit is provided.

Abstract: At a transfer electrode to which a normally low transfer pulse is applied, the time period in which the negative potential is applied is long, and an electric field is applied to a gate insulating film, such that the device's reliability decreases. To overcome this drawback, a negative side potential (VL?) of a normally low vertical transfer pulse (V?3, V?4) is set smaller in the absolute value than a negative side potential (VL) of a normally high vertical transfer pulse (V?1, V?2). Thereby, while the influence of increase in the dark current is being suppressed, the electric field being applied to the gate insulating film is reduced.

Abstract: An image pickup device is provided, capable of complete correction with data of once analog-to-digital conversion, and prevention of excess use of switches and analog devices and/or erroneous correction, including: an image sensor having a plurality of analog-to-digital converters determining conversion results from a digital signal of higher order bit through separate steps of two or more times; a first correction unit which has a correction factor for correcting nonlinear errors of the plurality of analog-to-digital converters so as to adapt to the analog-to-digital converters and corrects a nonlinear error of a digital signal output from respective analog-to-digital converters based on a correction factor corresponding to respective analog-to-digital converters, characterized in that the first correction unit corrects the nonlinear errors after converting the digital signals from the plurality of analog-to-digital converters into a serial output.

Abstract: According to one embodiment, in a pixel array unit, pixels that accumulate photoelectrically converted charges are arranged in a matrix shape. A vertical signal line transmits a signal read out from the pixels in the vertical direction. An acceleration circuit shifts the potential of the vertical signal line in advance before a signal is read out from the pixels. The acceleration control circuit controls timing for shifting the potential of the vertical signal line in advance. The timing control circuit generates a control signal for controlling the acceleration control circuit.

Abstract: A pulse generator with a filter section limiting a band of an input signal, and a pulse generating section generating a plurality of pulses which are sequentially delayed one after another by a time period (?) substantially equal to a reciprocal of a center frequency of the band of the filter section, and inputting the plurality of pulses to the filter section.

Abstract: When an external trigger is received as a predetermined signal after receiving a signal concerning a start of imaging, controls are carried out to stop driving of a CCD type solid-state image sensor (CCD) from receipt of the signal concerning a start of imaging until receipt of the external trigger, and to start the driving of the CCD synchronously with the receipt of the external trigger. Thus, the driving of the CCD is not started immediately upon receipt of the signal concerning a start of imaging, and the driving time of the CCD can be shortened by the time from receipt of the signal concerning a start of imaging until receipt of the external trigger, thereby suppressing heat generation of the CCD.

Abstract: An image sensing apparatus includes an image sensing unit that performs image sensing by converting incoming light into electrical signals, a control unit that controls driving of the image sensing unit so as to read out the electrical signals by each area of a plurality of areas of the image sensing unit, and a signal processing unit that processes the electrical signals read out by each of the plurality of areas. The control unit varies a horizontal cycle that drives the image sensing unit for each of the plurality of areas.

Abstract: A physical quantity detecting device includes a pixel array and a vertical driving circuit. In the pixel array, pixels each for converting a physical quantity supplied from the outside into an electric signal and storing the electric signal are two-dimensionally arranged in a matrix. The vertical driving circuit scans a plurality of sets of read rows so that a storage time for each of the electric signals differs from one another and performs a shutter operation on a shutter row in synchronization with a readout operation performed on the corresponding set of read rows out of the plurality of sets of read rows during 1H period that is a unit of time of scanning.

Abstract: An imaging apparatus includes a composite low frequency cutoff filter. The composite low frequency cutoff filter includes a first low frequency cutoff filter, a second low frequency cutoff filter, and an adder-subtractor. The second low frequency cutoff filter receives an output of the first low frequency cutoff filter. The adder-subtractor subtracts an output of the second low frequency cutoff filter from an input to the composite low frequency cutoff filter, and outputs a result of the subtraction to the first low frequency cutoff filter. An output of the first low frequency cutoff filter is outputted as an output of the composite low frequency cutoff filter.

Abstract: The digital still camera 1 has CCD 33 with an electronic shutter for controlling an exposure amount, and a timing generator 34 and a vertical/horizontal driver 35 for driving CCD 33. Under control of a controlling unit 42, the timing generator 34 and a vertical/horizontal driver 35 generate an electronic shutter pulse signal once every time plural periods have come each for reading charge of one line from CCD 33. Power consumption can be reduced in controlling exposure using the electronic shutter.

Abstract: In various embodiments, a time-delay-and-integrate (TDI) image sensor includes (i) a plurality of integrating CCDs (ICCDs), arranged in parallel, that accumulate photocharge in response to exposure to light, (ii) electrically coupled to the plurality of ICCDs, a readout CCD (RCCD) for receiving photocharge from the plurality of ICCDs, and (iii) electrically coupled to the RCCD, readout circuitry for converting charge received from the RCCD into voltage.

Abstract: The present invention discloses a transmitted/received data decoding method and apparatus, which achieve effects of decoding performance improvement and synchronous detection. The decoding method includes setting a coded edge pattern, and filtering a received data by using the set coded edge pattern as a window; respectively computing absolute values of filtered values filtered by using the coded edge pattern windows; detecting a maximum absolute value from the computed absolute values; determining a sign (+/?) for the detected maximum absolute value; outputting an intermediate bit value of the corresponding original data as a resultant decoded value according to the determined sign and a window type (i.e. coded edge patter) with the selected maximum absolute value.

Abstract: According to one embodiment, a solid-state imaging device includes a pixel region which is configured such that a photoelectric conversion unit and a signal scanning circuit unit are included in a semiconductor substrate, and a matrix of unit pixels is disposed, and a driving circuit region which is configured such that a device driving circuit for driving the signal scanning circuit unit is disposed on the semiconductor substrate, wherein the photoelectric conversion unit is provided on a back surface side of the semiconductor substrate, which is opposite to a front surface of the semiconductor substrate where the signal scanning circuit unit is formed, and the unit pixel includes an insulation film which is provided in a manner to surround a boundary part with the unit pixel that neighbors and defines a device isolation region.

Abstract: A solid-state imaging device includes a photoelectric conversion layer, a MOS transistor circuit. The photoelectric conversion layer is formed over a semiconductor substrate. The MOS transistor circuit reads out a signal corresponding to charges generated in the photoelectric conversion layer and then collected, and that is formed in the semiconductor substrate, the charges having a given polarity. The MOS transistor circuit includes a charge accumulation portion, a reset transistor, and an output transistor. The charge accumulation portion is electrically connected with the photoelectric conversion layer. The reset transistor resets a potential of the charge accumulation portion to a reset potential. The output transistor outputs a signal corresponding to the potential of the charge accumulation portion. The reset transistor and the output transistor have carriers whose polarity is opposite to the given polarity.

Abstract: An image-signal processor may be provided to support CCD image sensors. A timing generator may provide timing signals to CCD image sensors, to enable each of the CCD image sensors to output captured-image data in form of an analog signal that a corresponding A/D converter converts into a CYMG signal. Image-processing parts may receive the CYMG image signal from the A/D converter and convert the CYMG image signal into an YCbCr signal. An image-combination part may combine horizontally or vertically images in form of the YCbCr signal into a combination image and store the combination image in an internal memory, and scale down horizontally or vertically the combination image while reading out the combination image from the internal memory, storing the scaled-down combination image in an external memory, and outputting the scaled-down combination image in form of an YCbCr signal.

Abstract: An image sensing apparatus, having an image sensor for sensing an image of an object and an analog-digital converter which operates at a predetermined frequency and converts an analog signal read from the image sensor to a digital signal, controls the relationship between a phase of the analog signal read from the image sensor and a phase of a timing signal for operating the analog-digital converter in accordance with the peripheral condition.

Abstract: An image sensing apparatus, having an image sensor for sensing an image of an object and an analog-digital converter which operates at a predetermined frequency and converts an analog signal read from the image sensor to a digital signal, controls the relationship between a phase of the analog signal read from the image sensor and a phase of a timing signal for operating the analog-digital converter in accordance with the peripheral condition.