Abstract: A signal change differential value detector detects a signal change differential value between two digital signals obtained when the analog imaging signal is converted into the digital value for each pixel using two phase adjustment sampling pulses. An analog imaging signal waveform estimator estimates a waveform of the analog imaging signal based on the signal change differential value. A timing adjuster calculates an optimal phase of the imaging pulse based on the waveform of the analog imaging signal estimated by the analog imaging signal waveform estimator.

Abstract: A solid-state imaging includes a comparing circuit, an inverting circuit, and a masking circuit, and performs column parallel AD conversion processing of analog pixel signals outputted from a plurality of pixels arranged in a two-dimensional matrix form. The comparing circuit outputs a difference signal obtained by comparing each of the pixel signals outputted from the pixels with a reference signal having a ramp waveform. The inverting circuit inverts a logic of the difference signal outputted from the comparing circuit. The masking circuit masks an output of an output signal of the inverting circuit to a circuit in a subsequent stage during an input offset canceling period in which the comparing circuit is canceling an input offset between the pixel signal and the reference signal.

Abstract: A solid-state image sensor includes: a plurality of pixels, each having a photodiode, a floating diffusion, a transfer transistor, a reset transistor, and an amplifying transistor; vertical signal lines 31 for receiving signals from the plurality of pixels; sampling capacitors 62; circuits 78 for comparing a voltage on a corresponding one of the vertical signal lines 31 with a reference voltage to determine whether the voltage on the corresponding vertical signal line 31 is higher or lower than the reference voltage; and clip circuits 79 for outputting a clip voltage Vclip to a corresponding one of the sampling capacitors 62 based on the output of a corresponding one of the circuits 78. A voltage on each vertical signal line in the state where the signal accumulated in a corresponding photodiode has been transferred to a corresponding floating diffusion, can be used as a comparison voltage of each column.

Abstract: A dual sensitivity image sensor provides a standard mode and a high-sensitivity mode of operation via iSoC integration. In addition to boosting sensitivity, the high sensitivity mode also reduces temporal noise thereby optimally boosting the Signal-to-Noise Ratio (SNR) of the image sensor. The circuit does not significantly increase pixel complexity and requires minimal changes to the support circuits in the iSoC including the addition of support and control circuitry to facilitate seamless mode change.

Abstract: A method for shutting down a digital image capturing device is provided, The steps of the method are as follows: first, outputting a reset signal from a control unit of the capturing device to a timing generating unit; then setting a vertical pulse signal of the timing generating unit to a ground level within a time frame of the timing generating unit outputting a horizontal blanking signal; lastly, automatically shutting down the timing generating unit.

Abstract: An electric camera includes an image sensing device with a light receiving surface having N vertically arranged pixels and an arbitrary number of pixels arranged horizontally, N being equal to or more than three times the number of effective scanning lines M of a display screen of a television system, a driver to drive the image sensing device to vertically mix or cull signal charges accumulated in individual pixels of K pixels to produce, during a vertical effective scanning period of the television system, a number of lines of output signals which corresponds to 1/K the number of vertically arranged pixels N of the image sensing device, K being an integer equal to or less than an integral part of a quotient of N divided by M, and a signal processing unit having a function of generating image signals by using the output signals of the image sensing device.

Abstract: A drive control method for an image pickup device is disclosed. The image pickup device includes two-dimensionally arranged light receiving elements to photoelectrically convert incoming light, vertical transfer paths to transfer charges, which have been generated through the photoelectric conversion by the light receiving elements, in the vertical direction, and a horizontal transfer path to transfer the charges, which have been transferred by the vertical transfer path, row by row in the horizontal direction. In the method, the charges, which have been horizontally transferred by the horizontal transfer path, are directed and outputted in more than one directions, and the directed charges are respectively transferred and are added by temporarily stopping the transfer of the charges.

Abstract: A solid-state image pickup device relating to the present invention comprises a pixel area where multiple pixels used for photoelectric conversion of incident light are two-dimensionally arranged. Vertical signal input lines to which vertical transfer signals for transferring signal charges generated at the pixels vertically in the pixel area are applied are connected to the pixel area. Furthermore, horizontal signal input lines to which horizontal transfer signals for horizontally transferring the signal charges are applied are connected to a horizontal transfer part for horizontally transferring the signal charges transferred vertically in the pixel area. A signal separation part separates vertical and horizontal transfer signals from a pulse signal supplied via a complex signal input terminal and supplies the separated signals to the vertical signal input line and the horizontal signal input line, respectively.

Abstract: A timing signals generator, a frequency divider, an oscillator, and a signals processing IC generates driving signals and transfer signals of a CCD. When the CCD is exposed through a long time exposure in which exposure is performed for not less than a predetermined time, each of a clock frequency of driving signals during an exposure period and a clock frequency of each of driving signals and transferring signals during a transferring period is adjusted to be lower than a clock frequency of thereof in an exposure state in which exposure is performed for less than the predetermined time period.

Abstract: An imaging device driver for transmitting a signal onto a signal line for controlling transistors of a pixel row. The device includes a controller and associated circuitry for reducing shoot-through current within and between row driver circuits for driving the signal line. The controller reduces shoot-through current by preventing concurrent transmission of high and low signal outputs to the signal line by respective high and low voltage sources of the same or different row driver circuits.

Abstract: A solid-state image-capturing device which has built in an image-capturing area including a light receiving element provided on a semiconductor substrate, a substrate bias circuit, and a clamp circuit for receiving output of the substrate bias circuit and applying the output of the substrate bias circuit to the semiconductor substrate in accordance with a substrate pulse, comprises a substrate bias control circuit for controlling so as to reduce an electric current of the clamp circuit during a predetermined period.

Abstract: A driving method for a solid-state image sensing device having a plurality of sensor portions being disposed two-dimensionally in a horizontal and a vertical directions, and a vertical charge transfer portion being disposed between said plurality of sensor portions and being provided with transfer electrodes of a plurality of systems disposed along its disposed direction, including the steps of; selectively applying high level driving pulses to the transfer electrodes of said plurality of systems in respective sectional periods in a vertical transfer period, and transferring the signal charges read out from said plurality of sensor portions in the vertical direction, wherein a sectional period in a vertical transfer period, in which the number of systems of the transfer electrodes to be applied with high level driving pulses becomes minimum is set longer than that of the other sectional periods.

Abstract: A solid-state imaging device and a charge transfer method are provided. The solid-state imaging device includes light receiving portions arranged in a matrix of rows and columns, vertical transfer portions, and a horizontal transfer portion. The vertical transfer portions are formed for each column of the matrix of the light receiving portions, for transferring charges transferred from the light receiving portions in a vertical direction. The horizontal transfer portion transfers the charges transferred from the vertical transfer portions in a horizontal direction. The vertical transfer portions divide the charges transferred to the vertical transfer portions and transfer the divided charges in the vertical direction. The horizontal transfer portion transfers the divided charges in a mixed state in the horizontal direction.

Abstract: According to the present invention, as a structure of a pixel section (10), in each of columns from a first to a m-th column, a plurality of pixel signals outputted from a plurality of pixels arranged in a column direction are transmitted, respectively, to a plurality of output signal lines (15l to 15n) different from each other. Then, a read control and are set control are simultaneously executed on the plurality of pixels.

Abstract: A shooting operation is performed using a short exposure time at least one to obtain frame image data “A”, and a shooting operation is performed a plurality of times using a long exposure time to obtain sequential frame image data “B”. The image data “A” and “B” are recorded in a single file. In a moving image displaying operation, a moving image consisting of the plural pieces of frame image data “B” sequentially shot using the long exposure time is displayed. When the moving image being displayed is paused, a still image is displayed based on the frame image data “A” shot using the short exposure time.

Abstract: Circuitry for reducing fixed pattern noise in an image processing system with a 4-T (4 transistors) pixel and a method thereof is proposed. The image processing system includes two voltage sources, two current sources, a 4-T pixel, a second portion of a linearized source follower, a ping pong memory, a PGA, and auto-zero circuitry. By coupling the auto-zero circuitry to the PGA, an open loop is formed to clamp the output of an op amp of the PGA to a stable reference when resetting the PGA so as to remove DC offsets at the output terminal of the op amp.

Abstract: When a signal is read from a CCD solid-state image pickup element, the CCD solid-state image pickup element is driven with at least two driving voltages so that high-speed reading is performed with generation of noise due to interference between the driving voltages reduced. The CCD solid-state image includes a charge storage section between a vertical transfer register and a horizontal transfer register. By performing the transfer of charge in the direction of columns during an effective transfer period of the transfer in the direction of rows, signal charge of one row generated by a light receiving sensor is transferred to the charge storage section, and by performing the transfer outside the effective transfer period in the transfer in the direction of the row, the signal charge of one row transferred to the charge storage section is transferred to the horizontal transfer register.

Abstract: A CCD Device of the type for providing charge gain by impact ionisation has a multiplication register. Gain provided by a subset of the elements of the multiplication register are independently controllable from other elements in the register. This enables the register to be used in one setting with the same gain applied to all elements and a different setting with a subset of elements arranged to provide a different gain. By comparing the two signals, the gain provided by each element and the register as a whole may be derived.

Abstract: In one embodiment, a configurable timing generator outputs at least one timing signal. The configurable timing generator comprises a first timing generator configurable to output the at least one timing signal so that the at least one timing signal is adaptable to a plurality of applications. In one embodiment, a configurable parameter storage unit comprising a parameter storage area configurable so as to store a plurality of parameters at least partially defining a desired plurality of waveform hierarchy elements, where the desired plurality of waveform hierarchy elements enable the definition of a waveform. In one embodiment, a method of constructing a waveform for a configurable timing generator, the method comprising acts of constructing a first pattern waveform, where the first pattern waveform comprises a first basic pulse, and constructing a first sequence waveform, where the first sequence waveform comprises a plurality of repetitions of the first pattern waveform.

Abstract: A transfer pulse supplying circuit for supplying transfer pulses to a solid-state imaging apparatus including a charge transfer unit includes N (N is an integer of two or more) transfer pulse supplying wirings to which the transfer pulses are supplied, and lead-in wirings connecting the transfer pulse supplying wirings to corresponding lead-out wirings from the charge transfer unit. The respective lead-in wirings have almost the same width and length as one another. At least part of the lead-in wirings is divided into a first region and a second region by slits, and the first region is connected to the transfer pulse supplying wirings and the lead-out wiring, the second region is connected to the lead-out wiring. Regions of the respective lead-in wirings connected to the transfer pulse supplying wirings have almost the same ratio of width to length as one another.

Abstract: In a phase adjustment device according to the present invention, a first luminance level detector detects a luminance level of a digital imaging signal in a first pixel region, a second luminance level detector detects a luminance level of the digital imaging signal in a second pixel region, a data comparator compares detection results by the first and second luminance level detectors, an adjustment judger judges if it is necessary to adjust a phase of a pulse based on a result of the comparison by the data comparator, a timing adjuster shifts the phase of the pulse in the second pixel region when the luminance levels are detected, and further, the timing adjuster adjusts the phase of the pulse when the judgment by the adjustment judger indicates that the phase adjustment is necessary.

Abstract: To provide a solid-state imaging apparatus which is capable of preventing electric charge from being injected from a semiconductor substrate while electric charge is being accumulated into photodiodes. The solid-state imaging apparatus includes a solid-state imaging device and a driving pulse control unit. The solid-state imaging device includes: a semiconductor substrate, photodiodes which are two-dimensionally formed on the semiconductor substrate, and vertical Charge-coupled devices (CCDs) having at least one arranged read-out gate and non-read-out gate for each of the photodiodes, the read-out gate being for reading out accumulated electric charge from the associated photodiode, and the non-read-out gate being not for reading out accumulated electric charge from the associated photodiode.

Abstract: In one embodiment, a configurable timing generator outputs at least one timing signal. The configurable timing generator comprises a first timing generator configurable to output the at least one timing signal so that the at least one timing signal is adaptable to a plurality of applications. In one embodiment, a configurable parameter storage unit comprising a parameter storage area configurable so as to store a plurality of parameters at least partially defining a desired plurality of waveform hierarchy elements, where the desired plurality of waveform hierarchy elements enable the definition of a waveform. In one embodiment, a method of constructing a waveform for a configurable timing generator, the method comprising acts of constructing a first pattern waveform, where the first pattern waveform comprises a first basic pulse, and constructing a first sequence waveform, where the first sequence waveform comprises a plurality of repetitions of the first pattern waveform.

Abstract: In an imaging apparatus according to the present invention, the driving unit drives each of the pixels in the non-readout region in the first mode such that the setting unit sets the input unit to a third electric potential with the transfer unit being ready to transfer the electric charge to reset the photoelectric conversion unit in a first period and that the setting unit sets the input unit to a fourth electric potential for the pixel to be deselected in a second period later than the first period.

Abstract: An image sensor array is provided with: first and second CCD image sensors that output a plurality of first and second signal voltages from first and second output terminals, respectively; a switch circuit selectively connecting one of the first and second output terminals to a signal voltage output terminal; and a timing generator circuit responsive to a basic clock generating first and second control signals and switch control signals. First and second control signals control generation of the first and second signal voltages, respectively. The switch control signals are used for controlling the switch circuit. The timing generator circuit controls the first and second CCD image sensors so that the first and second CCD image sensors alternately output the first and second signal voltages. The timing generator circuit controls the switch circuit to alternately output from the signal voltage output terminal one of the first and second signal voltages.

Abstract: A solid-state imaging device includes: a plurality of pixels arranged in a matrix, the matrix defining columns of the pixels, and each of the pixels outputting an analog signal by performing photoelectric conversion; an analog-digital converter provided for each of columns which sequentially converts a plurality of analog signals outputted from the pixels in a column into a plurality of digital signals; a memory circuit provided for each column which includes memories and performs, in parallel, a process of storing a one of the digital signals in one of the memories and a process of outputting another of the digital signals previously stored in another of the memories; and data buses connected to the memory in each column.

Abstract: The solid image pickup device of the present invention comprises a photoelectric conversion part, a charge-voltage conversion part for converting electric charges from the photoelectric conversion part to voltage signals, a signal amplifier for amplifying the voltage signals generated in the charge-voltage conversion part, charge transfer means for transferring photo-electric charges from the photoelectric conversion part to the charge-voltage conversion part, and means for applying a certain voltage to a charge-voltage conversion part, wherein at least two readout operations for reading out the photo-electric charges accumulated during a period of accumulating photo-electric charges in the photoelectric conversion part via a signal amplifier.

Abstract: An image sensor and an image sensing method can obtain image signals with a high S/N ratio in a high-speed image pickup operation. Signal charges are input to input transfer stage 31 of CCD memory 30. Final transfer stage 32 is formed so as to be connected to the input transfer stage 31 and able to transfer signal charges to the input transfer stage 31. In an accumulation mode, read gate 42 and drain gate 40 are not turned on and the next transfer operation of the CCD memory 30 is conducted. The accumulated signal charges are transferred on a stage by stage basis and the signal charges obtained at the first image pickup timing are transferred again straightly to the input transfer stage 31. In this state, the signal charges obtained newly at photoelectric conversion section 20 at the next image pickup timing are injected into the input transfer stage 31 by way of input gate 21.

Abstract: A CCD-type solid-state imaging device includes: light receiving devices arranged in vertical and horizontal directions; vertical transfer parts arranged along vertical rows of the arranged light receiving devices, reading out charge accumulated in the adjacent light receiving devices, and transferring the read out charge in the vertical direction; a horizontal transfer part supplied with the charge transferred in the vertical transfer parts and transferring the supplied charge in the horizontal direction; an output part outputting the charge transferred in the vertical transfer parts; an input terminal for readout and transfer clocks that command readout of the charge from the light receiving devices and transfer of the read out charge in the vertical transfer parts; a resistor connected between the input terminal and a clock supply part of the vertical transfer parts; and a switch part connected to the resistor in parallel and switching between the charge readout and the charge transfer in the vertical trans

Abstract: A transfer pulse generator circuit for outputting a vertical register transfer pulse includes transfer pulse control circuit for controlling to set rise and fall timings of the vertical register transfer pulse to desired timings in a predetermined period.

Abstract: When a signal is read from a CCD solid-state image pickup element, the CCD solid-state image pickup element is driven with at least two driving voltages so that high-speed reading is performed with generation of noise due to interference between the driving voltages reduced. The CCD solid-state image includes a charge storage section between a vertical transfer register and a horizontal transfer register. By performing the transfer of charge in the direction of columns during an effective transfer period of the transfer in the direction of rows, signal charge of one row generated by a light receiving sensor is transferred to the charge storage section, and by performing the transfer outside the effective transfer period in the transfer in the direction of the row, the signal charge of one row transferred to the charge storage section is transferred to the horizontal transfer register.

Abstract: A solid-state imaging device includes a reflection timing control signal output unit, a data holding unit, and a collective-reflection processing unit. The reflection timing control signal output unit outputs a reflection timing control signal for controlling a timing of outputting operation setting data. The data holding unit latches the operation setting data inputted from outside and outputs the operation setting data. The collective-reflection processing unit collectively latches the operation setting data in synchronism with the reflection timing control signal, and outputs the latched operation setting data to a driving section.

Abstract: A method and apparatus for propagating charge through a sensor and implementation thereof is provided. The method and apparatus may be used to inspect specimens, the sensor operating to advance an accumulated charge between gates of the TDI sensor. The design implementation provides a set of values representing a plurality of out of phase signals, such as sinusoidal or trapezoidal signals. These out of phase signals are converted and transmitted to the sensor. The converted signals cause the sensor to transfer charges in the sensor toward an end of the sensor. Aspects such as feed through correction and correction of nonlinearities are addressed.

Abstract: A solid-state image-capturing device which has built in an image-capturing area including a light receiving element provided on a semiconductor substrate, a substrate bias circuit, and a clamp circuit for receiving output of the substrate bias circuit and applying the output of the substrate bias circuit to the semiconductor substrate in accordance with a substrate pulse, comprises a substrate bias control circuit for controlling so as to reduce an electric current of the clamp circuit during a predetermined period.

Abstract: An image sensing apparatus includes an image sensing unit that performs image sensing by converting incoming light into electrical signals, a control unit that controls driving of the image sensing unit so as to read out the electrical signals by each area of a plurality of areas of the image sensing unit, and a signal processing unit that processes the electrical signals read out by each of the plurality of areas. The control unit varies a horizontal cycle that drives the image sensing unit for each of the plurality of areas.

Abstract: An image pickup apparatus includes the following units. An image pickup unit captures an image and outputs an analog image signal. A conversion unit converts the analog image signal into a digital image signal. A synchronization signal generation unit generates a synchronization signal to be supplied to the image pickup unit and the conversion unit, and supplies the synchronization signal to the image pickup unit. An adjustment unit adjusts the timing at which the synchronization signal generated by the synchronization signal generation unit is supplied to the conversion unit, and supplies the synchronization signal to the conversion unit. The adjustment unit is disposed in a position such that the adjustment unit is affected by the self-heating of the image pickup unit.

Abstract: A method of transferring charge from a photosensitive array using a plurality of vertical shift registers, each having a plurality of vertical elements including first and last vertical element is disclosed The vertical shift registers are capable of transferring charge in a first direction from the first to the last vertical element The method also includes using at least one horizontal shift register having a plurality of horizontal elements. Each of the horizontal elements is arranged to receive charge transferred from the last vertical element of a respective one of the plurality of vertical shift registers, and shift the charge in a horizontal direction. The method includes operating the horizontal shift register during a plurality of horizontal operating intervals and operating the plurality of vertical shift registers during at least a portion of the plurality of horizontal operating intervals.

Abstract: A reference charge generator provided on an image capture element generates reference charge. The reference charge is transferred through a vertical transfer section as is signal charge of a pixel which is generated by a photoelectric converter. A reference signal corresponding to the reference charge is output from the image capture element. Data of a digital value obtained by conversion from the reference signal and a digital value which is obtained from the reference signal when the image capture element ideally operates are compared to estimate the state of a pulse for driving the image capture element. The state of the pulse is adjusted such that the pulse has optimum phase and duty.

Abstract: There is provided a sensor driving circuit that includes: an image sensor that converts light reflected from an original to be read into electric signals; a driver circuit that drives the image sensor; and a timing generator circuit that outputs timing signals for use in control of the image sensor. The driver circuit includes a first inverting buffer circuit and a second inverting buffer circuit that are equivalent to each other and arranged in series connection of two stages with the first inverting buffer circuit at the first stage of the two stages. The timing signal output from the timing generator circuit has the same polarity as the polarity of an input signal fed to the image sensor.

Abstract: A charge-coupled device image sensor includes (a) a two-dimensional array of pixels having a plurality of rows and columns, the two-dimensional array includes: (i) a plurality of gates arranged as a charge-coupled device; wherein the array further includes a plurality of charge-coupled devices that are arranged to be clocked by one or more common timing signals; (ii) a transition region, electrically connected to the array, having a first and second row of gates in which the second row is electrically mated into a plurality of first and second pairs of gates in which first pairs of gates are clocked by a first common timing signal and second pairs of gates are clocked by a second common timing signal; wherein the first row of gates are all clocked with a third common timing signal; and (b) a horizontal shift register adjacent the second row of gates for receiving charge from the second row of gates.

Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.

Abstract: A method for reducing dark current within a charge-coupled device, the method includes each gate phase n having a capacitance Cn, voltage change on the gate phase n given by ?Vn such ? n ? C n ? ? ? ? V n ? 0 ; for the first time period, maintaining a set of first gate phases holding charge in the accumulated state and maintaining a set of second gate phases not holding charge in the depleted state; for a second time period, clocking the charge into a set of third gate phases in the depleted state and clocking the second set of gate phases not holding charge into the accumulated state; for a third time period, clocking the third set of gate phases holding the charge into the accumulated state and clocking a fourth set of gates not holding the charge into the depletion state; wherein the second time period is shorter than the first and third time periods.

Abstract: There is provided an image-signal processor capable of supporting a plurality of CCD image sensors (10, 20), including a timing generator (110) providing timing signals, each with the same phase, to the at least two CCD image sensors (10, 20), to enable each of the CCD image sensors (10, 20) to output captured-image data in the form of an analog signal which a corresponding A/D converter converts into a CYMG signal; at least two image-processing parts (11, 21), each of which receives the CYMG image signal from the A/D converter and converts the CYMG image signal into an YCbCr signal through application of color interpolation; an image-combination part (50) combining horizontally or vertically at least two images being in the form of the YCbCr signal into a combination image and then storing the combination image in an internal memory, and, at the same time, scaling down horizontally or vertically the combination image while reading out the combination image from the internal memory (53), storing the scaled-do

Abstract: The CMOS image sensor includes a plurality of photoelectric conversion elements arranged in a matrix having a plurality of rows and columns. A plurality of floating junctions are provided, each of which is arranged between one of a plurality of pairs of the photoelectric conversion elements arranged in adjacent two rows and is connected to one of the pairs of the photoelectric conversion elements, so that output signals of the pair of the photoelectric conversion elements may be transferred. Output circuits are connected to a plurality of the floating junctions arranged in the column for reading in common the output signals of the photoelectric conversion elements transferred to these flowing junctions. Output signal lines are provided for each column so as to supply output signals of the output circuits. The output circuits are arranged between the pairs of photoelectric conversion elements adjacently arranged in the row.

Abstract: In a solid state imaging device, signal charges are branched to be output to in the form of one or plural outputs. At a horizontal transfer speed not lower than a predetermined transfer speed, the imaging device transfers signal charges of color attributes classified by a branching section, to plural horizontal transfer paths, where the signal charges are converted into analog voltage signals, which will be output synchronously. At a horizontal transfer speed lower than the predetermined transfer speed, the analog voltage signal converted is output from, e.g. the horizontal transfer path which has been selected. Output amplifiers arranged on the horizontal transfer paths are differentiated in sensitivities in detecting signal charges, depending on color attributes of signal charges supplied, and output the analog voltage signals.

Abstract: A driver circuit provided with a shift signal generator for sequentially outputting shift signals at a predetermined time interval; a plurality of amplifiers respectively receiving a plurality of detection signals read out in parallel corresponding to a detectable object image pattern and respectively receiving the shift signals, wherein the plurality of amplifiers respectively amplify and output the detection signals inputted thereto based on the output timing of each of the shift signals inputted thereto; a data converter for outputting in time series each of the amplified detection signals outputted from each of the amplifiers based on the output timing of each of the shift signals and for generating time series read data. Power consumption and the amount of heat generation are suppressed in the driver circuit provided with means to individually control a supply state of electrical current to each of the amplifiers.

Abstract: An apparatus and method for generating a programmable boost signal. A first input receives at least one programming control signal. A second input receives a reference signal. The programmable boost signal generation circuit receives the programming control signal and the reference signal and generates a boost signal with at least two programmable levels based on the reference signal. The level of the boost signal is selected by the programming control signal.

Abstract: An image pickup method of picking up images at a frame rate changeably set out of a plurality of frame rates is provided. The method includes the steps of: setting a vertical synchronization cycle in accordance with a set frame rate and adding an image pickup signal that does not include a valid image pickup region in accordance with the set vertical synchronization cycle while keeping a horizontal synchronization cycle of each image pickup signal constant, when obtaining an image pickup signal from an image sensor; and correcting a time axis of an obtained image pickup signal that includes a valid image pickup region, correspondingly to the set frame rate and deleting an obtained image pickup signal that does not include the valid image pickup region.

Abstract: A transfer pulse generator circuit for outputting a vertical register transfer pulse includes transfer pulse control circuit for controlling to set rise and fall timings of the vertical register transfer pulse to desired timings in a predetermined period.

Abstract: Preview mode low-resolution readouts occur, and then a shutter button on a camera is pressed, which causes an image sensor cleanout operation to occur. Following the cleanout, a high-resolution readout occurs. As rows of sensor values are read, the first rows are rows corresponding to a pre-defined horizontally-extending shielded area. There are no valid area sensor elements to either side of the horizontally-extending area. Data values read from the horizontally-extending area are used to determine optical black (OB) values that are then used to adjust the valid area values read out of the image sensor in that same frame. The same OB values are used throughout the adjusting of the valid area values of the entire frame. No values from the preview readouts are used in the OB value determination, so there is a clean break between the preview mode OB level and the high-resolution capture OB level.