Abstract: There is provided an electronic camera comprising an imaging element which photo-electrically converts an object field light, a timing generator including an internal register in which timing of a drive signal used to operate the imaging element can be programmed, a power supply control portion which supplies a second voltage to the imaging element when a predetermined time has elapsed after supply of a first voltage to the timing generator, and a control portion which starts at least program setting in the internal register of the timing generator after elapse of a time that the timing generator requires to operate stably at the first voltage and before elapse of a time that the imaging element requires to operate stably at the second voltage.

Abstract: An image capturing device having a function of clamping an image signal. When the image capturing device is activated, a synchronous signal generating section begins creation of a horizontal synchronous signal, and a counter begins counting a pulse of the horizontal synchronous signal. When the counted value reaches a predetermined value, the clamping capability control section changes the level of a clamp mode signal to an H level. During a period from the start of power supply to the image capturing device to the raising of the level of a clamp mode signal to an H level, a clamp pulse generating section sets a longer width for a clamp pulse than in a normal operation so that a switch element of a clamping circuit remains in an on state in a longer period, whereby a smaller time constant for clamping is set. After elapse of a predetermined period, the switch element is controlled so as to remain in an ON state in a normal period, which is relatively short, whereby a larger time constant for clamping is set.

Abstract: A pixel area of a megapixel solid-state color imaging device is divided into unit areas for pixel adding and all the pixels for the same color are added together in each unit area. Accordingly, the percentage of utilized pixels is raised to 100% and aliasing noise to low frequencies in a high-frequency video signal is greatly suppressed by a spatial LPF (low pass filter) effect of the pixel addition in the area units.

Abstract: A processing apparatus having a drive pulse generator circuit for generating a drive pulse to be supplied to an image pickup element, and a wave form data supply circuit for supplying wave form setting data for generating the drive pulse to the drive pulse generator circuit at each horizontal line, wherein the wave form setting data includes a wave form setting data to be set at each horizontal line and wave form setting data sharing a setting area.

Abstract: A solid-state image sensor includes photodiodes, which constitute pixels, shifted in position from each other and red (R), green (G) and blue (B) filter segments fitted on the photodiodes in a preselected pattern. R transfer gates, G transfer gates and B transfer gates each are connected to a particular vertical transfer electrode. Particular vertical drive pulses are fed to the electrodes to drive the transfer R, G and B transfer gates. Photodiode read pulses are applied to each of the electrodes at a particular timing on the basis of image signals output from the image sensor. Consequently, a signal charge generated in each photodiode is shifted to a particular vertical transfer path via the R, G or B transfer gate in accordance with color-by-color exposure time.

Abstract: A CCD shift register capable of switching between two-phase driving and three-phase driving in which crosstalk among clock signal lines is reduced and a decrease in transfer efficiency is prevented. Transfer electrodes disposed at regular intervals along a channel region are supplied with clock signals through clock signal lines. Three pairs of clock signal lines that are supplied with an in-phase clock signal at three-phase driving are disposed next to each other. One pair of odd-numbered clock signal lines supplied with an in-phase clock signal at two-phase driving is disposed next to each other, and one pair of even-numbered clock signal lines supplied with an in-phase clock signal at two-phase driving is disposed next to each other.

Abstract: A reference charge generator provided on an image capture element generates reference charge. The reference charge is transferred through a vertical transfer section as is signal charge of a pixel which is generated by a photoelectric converter. A reference signal corresponding to the reference charge is output from the image capture element. Data of a digital value obtained by conversion from the reference signal and a digital value which is obtained from the reference signal when the image capture element ideally operates are compared to estimate the state of a pulse for driving the image capture element. The state of the pulse is adjusted such that the pulse has optimum phase and duty.

Abstract: An imaging system controller (5) outputs a control signal (VC). The control signal (VC) gives a command to output driving clocks (?Vn, ?Hm) of an imaging element (1) in a signal transmission period, and a command to suspend output of the clocks (?Vn, ?Hm) in an idle period subsequent to the signal transmission period. The length of the idle period is a multiple of the length of the signal transmission period by a natural number. The imaging system controller (5) periodically repeats output of the control signal (VC) giving these commands a number of times corresponding to the number of horizontal lines of the imaging element (1). In response to the commands of the control signal (VC), a timing generator (2) generates and outputs the clocks (?Vn, ?Hm), and suspends generation and output of the same. An imaging device (10) thereby intermittently drives the imaging element (1), to generate and output a picked-up image signal (V2).

Abstract: A preprocessor converts an analog image signal, which is outputted from a solid-state image pickup sensor that photoelectric-converts an optical image of a subject, into digital image data. A timing generator periodically generates a drive pulse for driving the solid-state image pickup sensor continuously/discontinuously, and generates an output stop position signal that indicates an output stop position of the solid-state image pickup sensor when the solid-state image pickup sensor is driven discontinuously in sync with the drive pulse. A continuous data generator lets through the image data when the output stop position signal is invalid, and converts the image data inputted in a discontinuous state into continuous image data when the output stop position signal is valid.

Abstract: A digital image process for a digital camera contains a preprocessor and a postprocessor. The preprocessor can include, for example, a uniformity corrector, a sampling filter, a modulation transformer, and a ditherer. The postprocessor can include a color interpolator, an RGB reconstruction block, a digital compressor, and a color pattern data buffer. The digital image process is programmable to operate one or more of the processing blocks of one or both the preprocessor and the postprocessor for flexible programming that can adapt to the requirements of various digital camera designs or users.

Abstract: A solid state image pickup device being provided with a photoelectric converter portion being composed of a plurality of pixels disposed in a row, a charge transfer portion for transferring the charges generated in the photoelectric converter portion, and a charge/voltage converter portion for converting the charges transferred by the charge transfer portion into voltages, comprising; a timing pulse generator portion for generating at least more than one pulse signal from among the followings: a first pulse signal for driving the charge transfer portion, a second pulse signal for reading out the charges generated in the photoelectric converter portion, a third pulse signal for sweeping out the charges generated in the photoelectric converter portion and a fourth pulse signal for discharging the charges transferred to the charge/voltage converter portion, and a switch circuit for switching over at least one pulse signal out of the abovementioned pulse signals to a predetermined fixed potential or a floating le

Abstract: A digital camera 10 includes a systems control section 20. When the systems control section 20 receives any of operation signals from a key operation section 18, the systems control section 20 measures the passage of time with a timer 22, and continues the time measurement for a specified period of time until any of the operation signals is supplied. In an imaging mode, the system controls section 20 generates an oscillation frequency higher than a normal oscillation frequency with a signal generation circuit 260 in response to a button depressing operation of a release shutter button 180, and generates the normal oscillation frequency upon receipt of any one of the operation signals in a specified period of time.

Abstract: A timing generator for an electronic image sensor includes one or more memory based tables for controlling timing events that occur within one or more different types of image sensor lines, and one or more memory based tables for controlling timing events that occur within one or more different types of image sensor frames.

Abstract: A method for reducing shutter latency while maintaining low dark current in the imager and minimizing energy consumption in a digital camera, the method including the steps of providing an imager operating in accumulation mode; and substantially continuous flushing of charges from the imager before capturing an exposure of an image with a time between vertical transfers greater than or equal to time between vertical transfers during normal image readout so that, if continuous flushing for a time necessary to readout substantially all rows of pixels has occurred, the exposure may be captured with substantially zero latency.

Abstract: An imaging apparatus includes an image optical pick-up device, first and second driving mechanisms, a shutter, and a driving current controlling mechanism. The image optical pick-up device photoelectrically converts an incident light image of a subject of a photograph. The first driving mechanism drives the image optical pick-up device and performs a rapid sweep function for rapidly draining unnecessary electric charges remaining in the image optical pick-up device. The shutter opens and closes a light passage for passing the incident light image into the image optical pick-up device. The second driving mechanism generates pulses to drive the shutter. The driving current controlling mechanism performs a control such that a first duration in which the first driving mechanism operates the rapid sweep function and as second duration in which the second driving mechanism generates a pulse for closing the shutter do not overlap under predetermined imaging environmental conditions.

Abstract: A solid-state imaging device of the present invention includes: photodiodes having a vertical overflow drain structure; vertical shift registers for temporarily storing signals transferred from the photodiodes; and a horizontal shift register for storing and horizontally transferring signals transferred from the vertical shift registers, wherein a ?SUB pulse is applied to the substrate, the ?SUB pulse having a larger pulse width than a ?V pulse applied to the gate electrode of each vertical shift register. Thus, it is possible to sweep out smear charges from the photodiode toward the substrate.

Abstract: A timing generator includes a plurality of waveform generators. Each waveform generator includes a register which stores externally input data of a signal waveform to be generated and a waveform generation circuit which generates and outputs a signal on the basis of the data stored in the register, and updates the data stored in the register at a predetermined timing.

Abstract: A charge coupled device is provided with; an output gate; a main CCD region operated in response to a set of clock signals; and an output region positioned between the output gate and the main CCD region and designed to transfer electric charges received from the main CCD region to the output gate. The main CCD region includes first and second transfer electrodes. The output region includes third and fourth transfer electrodes receiving clock signals which are phase-reversed from each other. The set of clock signals received by the main CCD region and the clock signals received by the output region are outputted from different driver circuits.

Abstract: A digital camera includes a CCD operating with accumulation mode clocking for capturing an electronic representation of an image; and two or more clocks operatively and respectively connected to each phase of the two or more phases for initiating flushing of excess current, wherein, to initiate flushing, a time the clocks are at a high level are substantially the same, and a time the clocks are at a low level can be selected at any duration between a minimum width at which dark current starts to substantially increase and twice its normal operating duration during image readout and for reducing power consumption while retaining minimum dark current and for having a substantially uniform dark field.

Abstract: The present invention implements an automated blank time function, which calculates a horizontal and/or a vertical blank time for a desired integration time and window size. Input data and control signals for predetermined integration time and window size are provided to a register interface, which generates configuration signals. The configuration signals are applied to machines, which generate reset control signals and read control signals from the configuration signals for controlling the imager.

Abstract: An image-capturing apparatus, in which solid-state image-capturing elements having a large number of pixels are used, capable of suitably performing image-quality correction on a captured image. In a monitor reading mode, a camera system LSI (6) detects the read image signal which is read by thinning out pixels by an image-capturing device (3). Based on the detected data, control values for image-quality correction are computed in a microcomputer (9), and the camera system LSI (6) performs an image-quality correction process on the image signal based on these control values. When the image-capturing device shifts to a capture reading mode, the camera system LSI (6) temporarily stores the image signal, in which all the pixels are read, in the image memory (7), thereafter reads the image signal and detects it. The microcomputer (9) computes a control value on the basis of this detected data and the detected data in the previously used monitor reading mode.

Abstract: A compact, energy efficient image sensor which enables transfer of images to an external system is made compact in size and low in power consumption comprises an image sensor control circuit 20 which operates to drive a CCD image sensor 4 and stores horizontal lines of image data in a line memory 30. An HREF signal is raised in association with the storing operation. The external system monitors the HREF and supplies an external clock EXCLK to an image sensor 2 during an H level period according to its convenience. A memory control circuit 34 sequentially outputs image data from the line memory 30 to a data bus 10 in pixel units and in synchronization with the EXCLK.

Abstract: There is provided a timing generator that outputs a second periodic signal having a desired phase difference to a first periodic signal by superimposing a voltage on a control voltage of a voltage-controlled oscillating unit of a PLL circuit for generating the second periodic signal. The timing generator includes an initializing unit for measuring a timing shift gain indicative of a ratio of a timing shift amount to a change of a superimposed voltage and a voltage generating unit for generating the superimposed voltage based on the desired phase difference and the timing shift gain.

Abstract: An imaging apparatus with a timing generator supplying an imaging device with drive pulses. The timing generator has registers for independently storing information required for generating a pulse pattern for the imaging device. A selector selects one of the registers to connect it to a pulse generator. Based on the information stored in the selected register, the pulse generator generates pulses of a pulse pattern for the imaging device. External control circuitry rewrites the information stored in an unselected register from the outside of the timing generator. By repeating the steps of selecting one of the registers and rewriting the information stored in the unselected register, drive pulses with various pulse patterns can be supplied to the imaging device.

Abstract: The present invention provides a digital still camera that can read high quality image data from a solid state image pickup device in both the low and the high sensitivity modes. The digital still camera according to the present invention includes shooting mode selecting means for checking and setting a shooting mode and reading mode selecting means for selecting a suitable reading mode in accordance with the set shooting mode. As the reading mode, full-pixel reading mode and two-field reading mode are provided in this invention. The digital still camera also includes a solid state image pickup device having imaging pixels for accumulating signal charges of an image. Since the signal charges are read in the suitable reading mode, it is possible to avoid mixing colors or decreasing signal charges as time go on. Therefore, it is possible to obtain a high quality image data.

Abstract: An image sensor such as the conventional CMOS image sensor, in which automatic controls including so-called automatic iris control and white balance adjustment for adjusting the sensor sensitivity, namely the charge accumulation time in each pixel, according to the brightness of the image sensing ambience are performed, involves the problem that, when the frame rate of the image sensor is slowed to save power consumption, the operation of the automatic control systems will also become slower and the image quality deteriorates. In the invented image sensor system using a CMOS image sensor, while a CMOS image sensor is operated at the full frame rate all the time, a circuit for processing image signals from the CMOS image sensor is operated at a speed close to that of full frame processing only when the power supply is turned on or when the image sensing ambience varies and switched to a lower frame processing speed when automatic controls, including iris control, have become stabilized.

Abstract: A solid-state imaging device comprises, on a semiconductor substrate, a plurality of sensor sections for storing a signal charge commensurate with a quantity of reception light, a charge transfer section for transferring and outputting the signal charge of the sensor sections, and an output section for converting the signal charge transferred by the charge transfer section into an imaging signal for output. A current controller is provided to cut off or reduce a current flowing to the output section in a signal storage period of the sensor section. This cuts off or reduces the current flowing to the output section in a signal storage period of the sensor section, and hence suppresses the amount of the current flowing to the output section in the signal storage period. Thus, wasteful consumption power is greatly reduced.

Abstract: A solid-state image pickup device includes photoelectric converters in row-column matrix configuration, VCCDs, one for each column, a color filter disposed above each converter to form a color filter array including layouts each including n rows, and a drive circuit for conducting readout treating (m*n) rows as one set, and selecting from the sets a plurality of units symmetrically distributed. Electric charge is read from the plural units. A first readout operation reads electric charge from a first group of rows having asymmetric distribution. A j-row transfer operation transfers the electric charge for j rows. A second readout operation reads electric charge from a second group of rows having asymmetric distribution at positions to which the electric charges are transferred by the j-row transfer operation. The electric charges are added in the VCCDs.

Abstract: A method for producing electronic video signals representative of a focused moveable image includs the following steps: providing a charge coupled device, masking substantially less than half of the lines of the device to form a masked storage area and a substantially larger unmasked sensing area; disposing the sensing area in the path of the image; providing a shutter for periodically blocking the image from the sensing area; and providing clocking signals to the device to shift sensed lines of the image from the sensing area to the storage area and to clock image representative electronic video signals out of the device.

Abstract: A fast imaging device 32 has a charge signal converter 33, a charge signal accumulator 36 and a charge signal transporter 37. A charge signal accumulator 36 is provided to each charge signal converter 33. A charge signal accumulator 36 extends linearly while inclining with respect to a line L2 connecting charge signal converter 33. The other end of a charge signal accumulator 36, connected at one end thereof to a charge signal converter 33 constituting a corresponding column, merges to a charge signal transporter 37. This construction reduces noise and increases a frame rate.

Abstract: An operating condition judging circuit judges a supply voltage level of a power supply source. A controller controls a frequency of sweep-out of unnecessary charge in the imaging element based on an output level of the power supply source for reducing peak consumed current and power consumption and thereby extending battery life.

Abstract: A photoelectric sensor outputs a signal by a first signal read mode and a second signal read mode. In the first signal read mode, the sensor outputs the pixel signals accumulated in the plural while subsampling the pixel signals for every one line. In the second signal read mode, the sensor outputs sequentially the pixel signals accumulated in two the plural pixels while adding the pixel signals from two pixels adjoining each other. An interlace/non-interlace converter converts the signal output by the photoelectric sensor in the first signal read mode to a non-interlaced signal. A signal processor generates a first video signal by converting the signal converted by the interlace/non-interlace converter into a specified image format in the first signal read mode, and generates a second video signal by converting the signal output by photoelectric sensor into the specified image format, such as a 4:2:2 YUV signal.

Abstract: An image pickup element drive control method can outputs a sharp image effectively without producing any overlapped images when it is driven for a high rate image pickup operation.

Abstract: A solid-state image pickup apparatus includes a color filter including complementary color filter segments. When a shutter release bottom is pressed to its half-stroke or full-stroke position, light incident via the filter is picked up in a movie/photometry or a still picture mode, respectively. While signal charges are read out of an image sensor in accordance with the mode, the signal charges are digitized to become pixel data. In the movie/the photometry mode, despite that a plurality of pixel data are mixed together, a set of primary color pixel data are generated as if pixel signals were thinned out by mixture. In the still picture mode, all the pixels are sequentially read out and interpolated to generate primary color pixel data greater in number than photosensitive cells. The primary color data are raised in frequency to enhance the resolution of a picture.

Abstract: A color filter arrangement (11) is used, in which a plurality of filter units are each made of 2×2 arrangements of red (R), green (G), green (G) and blue (B) color elements. First, signal charges are added up for all pixels belonging to each of a plurality of pixel blocks made of quadratic arrangements of 3×3 of pixels, which are larger than the filter units (2×2 arrangement). Then, compressed color information for each of the pixel blocks is obtained from a result of the addition for each pixel block, taking the 2×2 arrangements of pixel blocks as large filter units.

Abstract: A solid-state image pickup device has a differential output configuration for an output stage thereof and an IC in a next stage has a differential amplifier configuration for an input stage thereof. An output buffer unit buffers and outputs a digital signal from a horizontal bus line. At this time, in addition to the normal video signal, the output buffer unit generates an inverted output of the normal video signal. The normal video signal and the inverted output are outputted from a video signal output terminal and an inverted video signal output terminal, respectively, to the outside of a chip. Further, a clock, which is supplied from a timing generator to the output buffer unit, is also buffered and outputted to the outside together with an inverted clock A differential amplifier is used in an input stage of an IC in a next stage, whereby even signals having blunter waveforms can be recognized.

Abstract: An image capture apparatus which is compact and structurally simple and allows for prevention of a flicker noise, a method of capturing an image which allows for prevention of a flicker noise, and a mobile terminal using the apparatus and the method, are provided. In the image capture apparatus, a vertical cycle is adjusted so as to maintain 20 fps or 20/2m (m is an integer) fps, thereby to prevent a flicker noise in an image as obtained. To this end, in the image capture apparatus, a frequency of a horizontal transfer clock, a horizontal count level and a vertical line count level may be adjusted. Further, a fraction count is provided to adjust the length of one vertical cycle. Moreover, the image capture apparatus may be incorporated in a mobile terminal.

Abstract: A focal plane array in which information from the pixel forming elements is transferred into a vertical shift register and then from the last stage of the vertical shift registers row by row into a horizontal shift register is provided with a storage element and gate between each vertical register and the corresponding stage of the horizontal register. After the information currently in the storage gates has been transferred to the corresponding HCCD stages, the transfer gate is closed, and the next shift of the vertical registers begins, during a time when the vertical registers would otherwise be stopped, waiting for the multi-phase operation of the horizontal register. This time is used for usefully increasing the time for the vertical shift operation, and the clock is advantageously made slower. Alternatively, a faster frame rate can be handled by conventional clock circuits.

Abstract: In an image scanner, multiple exposures are used for each scan line, and only part of the pixels for each scan line are used for each exposure. For example, with two exposures, half the pixels may be used for the first exposure, and half for the second exposure. For each exposure, half of the charges are shifted out rapidly and discarded, without waiting for the A/D conversion time. As a result, for each exposure, the time required to empty the charge shift register is greatly reduced, reducing the thermal noise for all pixels.

Abstract: The driving device of a solid-state imaging device comprises a driving unit for driving the solid-state imaging device in either an addition driving mode in which a plurality of pixels are added and read as a single pixel or a non-addition driving mode, and a substrate bias voltage supply for applying a bias voltage to the substrate of the solid-state imaging device according to the driving mode. The substrate bias voltage is set according to the number of pixels added in the addition driving mode so that the overflow level of the charge accumulating portion may be lower in the addition driving mode than in the normal driving mode. This suppresses the input of excess charges to the horizontal transfer path even in the addition driving mode, thereby preventing the generation of horizontal streak noise.

Abstract: A charge transfer device having: a semiconductor substrate; a charge transfer path formed in the semiconductor substrate and made of a first conductivity type semiconductor layer; a plurality of charge transfer electrodes formed near above the charge transfer path; and a first pulse signal generator circuit for applying either a first pulse signal train for n-phase (n being an integer larger than 1) driving of charges in the charge transfer path to the charge transfer electrodes or a second pulse signal train for (n+1)-phase driving of charges in the charge transfer path to the charge transfer electrodes.

Abstract: For providing a longer lifetime and sensing an image with less noise, there is provided an image sensing apparatus having a flat panel sensor for detecting radiations, a first power circuit for supplying an electric power to the flat panel sensor, a read-out circuit for reading out data of the flat panel sensor circuit, a second power circuit for supplying an electric power to the read-out circuit, and a control circuit for turning the first power circuit on by a first timing signal and for turning the second power circuit on by a second timing signal.

Abstract: There is provided an image pickup apparatus including a plurality of pixels which are arranged in a horizontal and a vertical direction and which generate charges corresponding to optical signals, in which a color filter arrangement of a first order are arranged in horizontal pixel rows of odd numbers and a color filter arrangement of a second order are arranged in horizontal pixel rows of even numbers; and a drive circuit having a first mode for reading out pixel data of 2k+1 fields (k is a natural number) by an interlace operation from the plurality of pixels, a second mode for reading out pixel data of one field among the 2k+1 fields from the plurality of pixels, and a third mode for reading out images of a plurality of fields, the number of which is smaller than the of the 2k+1 fields, among the 2k+1 fields from the plurality of pixels.

Abstract: A system for controlling photosensitive charge transfers utilizes an array of photosensitive elements, a transfer gate, a charge transfer register, and a controller. The transfer gate is coupled to the photosensitive elements, and the charge transfer register is coupled to the transfer gate. The charge transfer register is configured to receive charges from the array of photosensitive elements, via the transfer gate, and to shift the charges out of the charge transfer register. The controller is configured to control the transfer gate such that charges are collected in each of the photosensitive elements and transferred, via the transfer gate, to the charge transfer register. The controller is further configured to enable the transfer gate during a time period when the charge transfer register is shifting a set of charges previously transferred from the array of photosensitive elements to the charge transfer register.

Abstract: An imaging device includes photoelectric converting portions for converting light from a subject into signal charge pixel by pixel and transfer portions for transferring the signal charge generated by photometric conversion. Photometric photodiodes are disposed over light-shielding membranes covering the transfer portions. Photometric photodiodes are so disposed as to be distributed over an imaging surface of the imaging device. Each photometric area includes at least one photometric photodiode. When a flashlight is emitted, photocurrent output from each photometric photodiode is gathered separately with respect to each photometric area and amplified. The photocurrent of each photometric area is amplified with a gain corresponding to the photometric area, and then added up. Added photocurrent is integrated, and when a result of the integration reaches a predetermined level an emission stop signal of the flashlight is generated.

Abstract: When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping as generally supplied to an A/D converter is generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks of a signal output by an empty transmission unit via a first clamp pulse and a sample/hold output for the second picture element, or a subsequent one of an OPB unit is clamped to the clamp level via a second clamp pulse to prevent a signal output from exceeding a reference voltage from being supplied to an A/D converter at a later stage.

Abstract: An operating condition judging means judges at least one of consumed current, whether or not a mechanically driven part is being operated, the supply voltage level, the ambient temperature, whether or not the lens stop device is operative, whether or not the strobo device is being charged, and whether or not access operation of a recording device is being performed. A controller controls a frequency of sweep-out of unnecessary charge in the imaging element on the basis of the output of an operating condition judging device. Thus, it is possible to effectively reduce the peak consumed current through the entire imaging apparatus, reduce the power consumption and extend the battery life.

Abstract: Even when variation in transistor characteristic, resistance or the like occurs during manufacturing, a noise component is always minimized. Each of k clock phase difference generating circuits 16–18 shifts a phase of a basic clock signal ADCK1 by a specified different value to obtain a clock signal ADCK2 and supplies the clock signal ADCK2 to an A/D converter. A k counter 19 successively selects the clock phase difference generating circuits 16–18 and stores a noise component in an output of the A/D converter measured by a noise measuring circuit 27 in a corresponding register. A comparator 25 compares k noise components and obtains the number j of the clock phase difference generating circuit giving a minimum value. A selection circuit 26 fixedly selects only the j-th clock phase difference generating circuit.

Abstract: In a solid-state image pickup apparatus, an image pickup section includes a color separating section having color filters assigned to three primary colors for separating colors of light incident from a desired scene. The color filters assigned to the color G are arranged in stripes. A system controller controls an output of a drive signal generating section for each of an all pixel read mode and a photometry control mode in response to the stroke of a shutter release operation. In the photometry control mode, the image pickup device is supplied with drive signals in response to a horizontal timing signal fed from a timing signal generator and a control signal fed from the system controller. The image pickup device thus reads out only the signal charges representative of the color G in this mode, thereby especially implementing the signal charge reading at a doubled speed.

Abstract: A control system and method for the CCD scanner, wherein the CCD can process multiple primary colors and includes a shift register and a transfer gate. The control system at least includes a transfer controller. The characteristic includes providing a transfer signal and multiple charge-shift clock signals, wherein any each one charge-shift clock signal corresponds to one primary color. All charge data with respect to the primary colors are transferred to the shift register through the transfer gate in once operation when the transfer signal is true. The shift register shifts out the charge data according to each of the charge-shift clock signals charge coupled device.