Abstract: The number of terminals for a timing signal generating device and the vertical drive device for a solid-state image pickup element is to be reduced, and at the same time the circuit dimensions of the timing signal generating device and the vertical drive device which are increased by the reduction in the number of terminals are to be kept to the minimum. A timing signal generating circuit is provided with a time-division multiplexing circuit, and this time-division multiplexing circuit subjects timing signals vertical transfer pulses and timing signals for read pulses to time-division multiplexing. On the other hand, a vertical driver is provided with a demultiplexing circuit, and the demultiplexing circuit separates four-bit signals subjected to time-division multiplexing into the original timing signals and timing signals. This enables the number of terminals (the number of signal lines) of the timing signal generating circuit and the time-division multiplexing circuit to be reduced.

Abstract: According to a driving method for an interline type CCD imaging device, the voltage level to be applied to a channel electrode in a vertical charge transfer line to which at least one photodiode is connected is controlled to form a shallower potential well just in the channel. At least the voltage levels applied to channel electrodes in the VCCD connected to the PDs are controlled such that potential wells formed within respective channels becomes shallower.

Abstract: A circuit includes a circuit chip and a plurality of clock drivers external to the circuit chip. The circuit chip includes a plurality of isolated clocking subunits and a corresponding plurality of terminals. Each clocking subunit is electrically isolated from any other clocking subunit. Each clocking subunit is coupled to a respective terminal. For each of the plurality of terminals, an output from one and only one clock driver of the plurality of clock drivers is coupled to the corresponding terminal of the plurality of terminals, and inputs of all clock drivers are coupled together.

Abstract: In making solid state imaging devices smaller and increasing their number of pixels, it is desirable to increase the charge amount that can be handled per unit area of the transfer portions. It is possible to achieve this by making the insulating film thinner, but this leads to electric fields in the semiconductor substrate that are too strong, and causes problems such as the generation of noise and the deterioration of the transfer efficiency. This invention relaxes potential steps in the transfer region by applying, when a signal charge 1 is being read out (t=t2), a high voltage to the electrode 43 for reading out the signal charge, a low voltage to at least one of the electrodes 41, 45–47 for preventing unnecessary mixing of signal charges, and an intermediate voltage between the high voltage and the low voltage to the electrodes 42 and 44, which are adjacent to the electrode 43 to which the high voltage is applied.

Abstract: In a solid-state image pickup device, third transfer electrodes are disposed in parallel to vertical transfer registers, and second transfer electrodes are disposed vertically to the vertical transfer registers. These transfer electrodes are also formed on the read-out gate portions to supply a driving voltage for reading out signal charges from photoelectric conversion elements. On the basis of the driving voltage applied to both the third and second transfer electrodes, the read-out of the signal charges to the vertical transfer registers is carried out. At the portion where the read-out of the signal charges is carried out, the transfer electrode at the read-out gate portion side and the sensor area of the photoelectric conversion element are formed so as to be adjacent to each other. At the portion where no read-out of signal charges is carried out, an offset area is provided between the transfer electrode at the read-out gate portion side and the sensor area of the photoelectric conversion element.

Abstract: A method for increasing signal to noise ratio is disclosed. The method can automatically detect saturation output voltage of the photosensors via adjusting exposure time or illumination intensity so as to obtain optimum output voltage of the photosensors as well as high signal to noise ratio that can generate high quality images.

Abstract: A digital camera includes a shutter button. When taking a still picture of a subject in response to operation of the shutter button, a TG carries out first exposure and second exposure. The first exposure and the second exposure are simultaneously started by the suspension of outputting a charge sweep-out pulse. Elapsing a first exposure period, the TG reads a first charge out of a part of the light-receiving elements, thereby ending the first exposure. Elapsing a second exposure period, a mechanical shutter is closed thereby ending the second exposure. A second charge produced due to the second exposure is read out after completing the transfer of the first charge. The first and second charges outputted from the CCD imager are combined together by an image combining circuit.

Abstract: A stable charge coupled device (CCD) imaging apparatus operable in multiple frame rates for displaying a signal having a low frame rate in a viewfinder (VF), and also a recorder built-in type imaging apparatus using the CCD imaging apparatus are presented. The imaging apparatus includes a drive pulse switching circuit for multiplying a CCD drive pulse other than a CCD read pulse by (n/2) (where n is an arbitrary integer) when the multi-frame rate is low, a frame memory for storing an output signal of the CCD of one frame right after pulse output. The signal is read at every (n/2) frames. The frame memory repeats to read out the stored signal in one frame (n/2) times. The imaging apparatus further includes a camera signal processing circuit for performing a camera process to an output signal of the frame memory, and a recorder unit for recording an output signal of the camera signal processing circuit at the frame rate of the set mode.

Abstract: A charge-coupled device for forming an electronic representation of an image from incident light, the charge-coupled device includes a substrate of a first type; a photosensitive area of a second type disposed in the substrate for receiving the incident light which is converted to a charge packet; a transfer mechanism for activating transfer of the charge packet through the charge-coupled device; an output mechanism for receiving the transferred charge packet; a reset operator for resetting the output mechanism to a charge voltage; and a logical element disposed on the substrate that inputs a gate waveform to the reset operator for activating the resetting operation of the reset operator.

Abstract: A CCD image detector includes an image area array, a storage area array, a buffer area array, and a readout shift register, all of which being controlled by a timing controller through separate and independent clock signals. The timing controller controls the transfer of the charge content of an image from the image area array to the storage area array and batch transfers of the charge content of the image from the storage area array to the buffer area array in bands of adjacent rows of gates. Between such batch transfers of bands, the timing controller controls the transfer of the charge content of the band stored in the buffer area array to the readout shift register one row of gates at a time at a slow rate to permit the charge content of each row to be shifted out from the readout register. The batch transfers of bands has the effect of minimizing slow rate transfers from the storage area array which reduces the impact of degraded charge transfer efficiency on performance of the image detector.

Abstract: An image sensing device includes a solid state image sensor, such as a CCD. An electronic shutter controls the exposure of the sensor to light, and thus the period during which the sensor collects or accumulates an information charge with light receiving pixels. The image sensor includes a semiconductor substrate, a semiconductor layer having parallel channel regions formed on the substrate, and transfer electrodes which intersect the channel regions. The channel regions generate and store the information charges.

Abstract: A method for reducing dark current within an image sensor includes applying, at a first time period, a first set of voltages to the phases of gate electrodes of vertical shift registers sufficient to accumulate holes of the vertical shift register, beneath each gate electrode and applying, at a second time period, a second voltage to a first set of the gate electrodes while simultaneously applying a more positive voltage to a second set of gate electrodes, the second voltage being of sufficient potential so holes that were accumulated beneath the second set of gate electrodes during the first time are collected and stored beneath the first set of gate electrodes during the second time period.

Abstract: A solid-state image sensing device comprising a photoelectric converter portion, a solid-state image sensor, and a controlling means. The photoelectric converter portion has a plurality of photoelectric converters arranged in two dimensions on a semiconductor substrate. The solid-state image sensor vertically transfers charges, transferred from the photoelectric converter portion, at separate times of first transfer and second transfer. Further, the photoelectric converter portion has a vertical transfer portion, in which first and fourth gates are provided for odd-numbered photoelectric converters, and second and third gates are provided for even-numbered photoelectric converters, and a horizontal transfer portion for horizontally transferring charges transferred from the vertical transfer portion. The controlling means supplies the vertical transfer portion with vertical transfer pulses and the horizontal transfer portion with horizontal transfer pulses.

Abstract: A driving method for a solid-state image sensing device having a plurality of sensor portions being disposed two-dimensionally in a horizontal and a vertical directions, and a vertical charge transfer portion being disposed between said plurality of sensor portions and being provided with transfer electrodes of a plurality of systems disposed along its disposed direction, including the steps of; selectively applying high level driving pulses to the transfer electrodes of said plurality of systems in respective sectional periods in a vertical transfer period, and transferring the signal charges read out from said plurality of sensor portions in the vertical direction, wherein a sectional period in a vertical transfer period, in which the number of systems of the transfer electrodes to be applied with high level driving pulses becomes minimum is set longer than that of the other sectional periods.

Abstract: An interface for receiving data from an image sensor having an imaging array and a clock generator and for transferring the data to a processor system is described. The interface comprises a memory for storing the imaging array data and the clocking signals at a rate determined by the clocking signals. In response to the quantity of data in the memory, a signal generator generates a signal for transmission to the processor system and a circuit controls the transfer of the data from the memory at a rate determined by the processor system. The memory may be a first-in first-out (FIFO) buffer or an addressable memory. The interface is preferably integrated on the same die as the image sensor. The signal generator may generate either an interrupt signal for transmission to the processor system or a bus request signal for transmission to a bus arbitration unit for the processor system.

Abstract: One horizontal CCD register is provided for a plurality of vertical CCD registers. The horizontal CCD register has horizontal transfer electrodes in such a manner that transfer electrodes that are provided for each pair of vertical CCD registers adjacent to each other are independent of each other electrically. The eight transfer electrodes are supplied with eight kinds of horizontal transfer pulse signals, respectively. An operation that the horizontal CCD register consecutively outputs consecutive signal charges in the same manner as in the conventional two-phase driving method and an operation that the horizontal CCD register outputs consecutive signal charges while mixing desired ones are performed selectively by controlling the eight kinds of horizontal transfer pulse signals properly.

Abstract: A method and apparatus for driving a solid state image pickup device. The method and apparatus include setting a first signal charging period and a second signal charging period for each one of a plurality of unit pixels. The second signal charging period is shorter than the first signal charging period. A first signal charge is produced during the first signal charging period and a second signal charge is produced during the second signal charging period. It is judged whether the first signal charge is saturated or not saturated. Then based on this judgment an input light amount is determined. The input light amount is determined using only the second signal charge when the first signal charge is saturated. The input light amount is determined using only the first signal charge when the first signal charge is not saturated.

Abstract: An image processing apparatus which eliminates noise which occurs due to the influence of output from a parallel bus drive circuit added to an output final stage circuit of signal processor or the like. A delay circuit 110 which delays a video signal is inserted into a VTR signal processor such that a data transition point of particular bit in a bit array indicating horizontal-directional start and end positions of video signal data, added during a horizontal retrace period of a digital recording format video signal, does not overlap with a period for sampling a feedthrough period and a photoelectric conversion signal period in a correlated double sampling circuit.

Abstract: A digital camera (10) that has an array (11) of CMOS sensor elements (11a). The array (11) is read in a manner that performs spatial-to-frequency transforms for image compression on the analog output signals of the sensor elements. More specifically, wordlines (12) and bitlines (13) are pulsewidth modulated so that the coincidence of their “on” times corresponds to a desired coefficient of the basis function of the transform (FIGS. 3 and 4). Additional comparator circuitry (15), quantizers (16), and encoding circuitry (19) can be part of the same integrated circuit as the array (11).

Abstract: Conventionally, it is difficult to design the logic of a Gray code counter that can be used in interlaced counting. Even though interlaced counting is possible with a Gray code counter, the number of simultaneously changing bits increases greatly depending on the number of counts skipped at a time. To overcome these problems, a Gray code counter according to the present invention has a consecutively counting Gray code counter that counts in increments or decrements of one, and an output value converter circuit that converts the Gray code data output from the consecutively counting Gray code counter into a Gray code corresponding to decimal counts as obtained by counting with (2 raised to a particular power minus 1) counts skipped at a time.

Abstract: For preventing the blooming phenomenon, there is provided an image pickup apparatus comprising a solid-state image pickup device adapted for a first readout method in which plural pixels are added to be read and a second readout method in which plural pixels are not added; and a circuit for applying a predetermined substrate voltage common to the first and second readout methods in an exposure period of the solid-state image pickup device and applying a predetermined substrate voltage corresponding to each readout method of the solid-state image pickup device in a period from the end of exposure of the solid-state image pickup device to the start of transfer to the signal transfer channel.

Abstract: An apparatus and a method for synchronizing the velocity of an image of a moving object and the clocking of image sensor elements used to track the moving target. The imaging apparatus includes a two-dimensional array of image sensor elements being configured to sense a first set of image elements in a first direction according to a clock rate. A plurality of rows of image sensor elements are spaced from each other. The rows of image sensor elements are configured to sense a second set of image elements of the target moving in the first direction according to the clock rate. Each row has image sensor elements that are different in length from the image sensor elements of the other rows. A measurement module is coupled with the plurality of rows of image sensor elements to measure the sharpness of detected image elements and to identify the row of image sensor elements having the sharpest detected image elements.

Abstract: A color imaging apparatus includes a CCD imaging device having interline transfer charge transfer paths adapted for interlaced reading and a Bayer-arranged color filter. The apparatus can be put in either of normal shooting mode and high-sensitivity shooting mode. In the high-sensitivity mode, pixel signals from two pixels arranged in the vertical direction in each photosensitive CCD array are transferred by a corresponding vertical transfer path at two times the rate in the normal mode to a horizontal transfer path where they are added together. A line of pixel signals from the horizontal transfer path is output to a preprocess circuit where pixel signals separated by one pixel in the horizontal direction are added together. This process produces a line of image signal.

Abstract: A digital camera includes a CCD imager having an interline transfer scheme. A first charge produced due to first exposure is read from light receiving elements positioned vertically intermittently. A second charge produced due to second exposure is also read from the same light receiving elements to vertical transfer regions. Here, the first charge is vertically moved simultaneously with or prior to reading out the second charge. The moving distance, at this time, is equal to or greater than a distance that the light receiving elements continue in the vertical direction. As a result of this, the second charge will not be mixed with the first charge. The first and second charges are subjected to a compositing process to display a composite image on an LCD.

Abstract: An image pickup device comprises a CCD solid-state imaging element composed of a charge accumulation section and a charge transfer section, a CCD driver for driving the imaging element, a mechanical shutter for switching between the transmitting state and shading state of the subject's image on the imaging element, and a controller for controlling the CCD driver and mechanical shutter. The controller, closes, opens and closes the mechanical shutter in that order. After having discharged charges in the first closing, the device refrains from driving the vertical transfer channel during the period that the channel is exposed to light rays and ends exposure in the presence of a charge transfer pulse. Moreover, in a low-speed shutter, the image pickup device switches to exposure end with the mechanical shutter.

Abstract: A frame transfer type solid-state imaging apparatus has a matrix of pixels which store information charges corresponding to a received image. The information charges are moved from the pixels to vertical transfer registers, and then to a horizontal transfer register, prior to being stored. A timing control circuit generates a vertical scan timing signal and a horizontal scan timing signal using a divided clock signal. A horizontal drive circuit generates a horizontal transfer clock using the divided clock signal and the horizontal scan timing signal. The horizontal transfer clock is used to move the information charges from the vertical transfer registers to the horizontal transfer register. A vertical drive circuit generates a vertical transfer clock using a reference clock signal and the vertical scan timing signal. The vertical transfer clock is used to move the information charges from the pixels to the vertical transfer registers.

Abstract: Any complicates pulse waveform required depending on the type of CCD, can be generated with a simple circuit configuration. Specifically, any complicated pulse is obtainable by inputting an unlimited number of toggle timings, with no limitation imposed on the number of toggle timings inputted. This is achieved only by inputting different toggle timings sequentially from the exterior, because the toggle timing of toggle circuits (14 to 16) is regulated by shift registers (12a, 12b) of a loop structure and comparators (11a, 11b) connected to the rearmost stage of their respective shift registers (12a, 12b).

Abstract: To reduce the amount of data that should be stored on a memory-built-in timing generator for generating timing pulses for use to drive a solid-state imaging device, V- and H-counters, three ROMs, V- and H-comparators and combinatorial logic circuit are provided. The V- and H-counters perform a count operation responsive to vertical and horizontal sync signal pulses as respective triggers. One of the ROMs stores time-series data representing a logical level repetitive pattern of an output pulse train. The other two ROMs store edge data representing at what counts of the V- and H-counters control pulses should change their logical levels. The V- and H-comparators and the combinatorial logic circuit change the logical levels of the control pulses when the counts of the V- and H-counters match the edge data. The comparators and logic circuit also output, as the timing pulses, results of logical operations performed on the output pulse train, represented by the time-series data, and the control pulses.

Abstract: In an image sensing apparatus using an image sensing device, such as a CCD, to be used by connecting to an external device, such as a computer, an operating rate of the CCD is changed in accordance with a rate at which the computer receives image signals from the image sensing apparatus. Further, when the operating rate of the CCD is changed, a proper exposure value is conjectured to obtain an image sensed at a proper exposure on the basis of operating rates of the CCD before and after the operating rate is changed, and a proper exposure value of the CCD before the operating rate is changed.

Abstract: A short duration of exposure is selected for the object for EVEN fields and a long duration of exposure is selected for the object for ODD fields by the electronic shutter, the obtained images being subsequently synthetically combined according to a synthetic reference levels in a dynamic range broadening mode. For the EVEN field, the duration of exposure is automatically controlled according to the brightness for high speed shutter operation. The level of REF is lowered when a small value is selected for the duration of exposure whereas the level of REF is raised when a large value is selected for the duration of exposure. In the case of a dark object that does not require any dynamic range, REF rises to get to the white clip level, when the mode is switched to an ordinary mode to increase the duration of exposure for both EVEN fields and ODD fields.

Abstract: In a moving image display mode, CPU commands a selector to input an output signal of a frequency divider to a signal processing part as a synchronous signal. In case of a CCD with G-stripe or Bayer arrangement, the frequency divider divides the frequency of a clock by an odd number (for example, 3 or 5) and the frequency-divided clock is inputted to the signal processing part. This thins out the pixels of image data to {1/(an odd number)} and the image data is inputted to the signal processing part without changing the arrangement of the pixels. The inputted image data is processed at the signal processing part, and then is outputted to the liquid crystal monitor, which displays a moving image.

Abstract: In a photosensor system formed of a photosensor array including a plurality of photosensors arranged in a two dimensional direction, the intervals of the reset pulse, read pulse and pre-charge pulse applied to each row of the photosensor array are respectively set equal to the sum of the reset period, the read period, and the pre-charge period. It follows that even where the read processing time of a single screen is shortened by allowing the processing cycles for the rows to partially overlap with each other, the reset period, the pre-charge period and the read period are prevented from being overlapped in time with each other, making it possible to perform the read operation accurately.

Abstract: An image pick-up apparatus including a CCD 1 generating an image signal, a timing generator 6 generating various kinds of timing signals for controlling operation timings of CCD, a V driver 30 generating various kinds of driving signals for driving CCU in response to the timing signals, a power supply circuit 31 generating a power supply voltage VDD applied to the timing generator and V driver, and a CPU 8 controlling an application of the power supply voltage to the timing generator 6 and V driver 30 and controlling the operation of the timing generator. The CPU 8 has a first operation mode, in which the timing generator is set into a standby mode such that a leak current from the timing generator to the V driver is avoided when the power supply Voltage is not applied to the V driver, and a second operation mode, in which the timing generator is set into a normal operating condition after the power supply voltage has been applied to the V driver.

Abstract: An image apparatus has a light-receiving section and a light-blocking section. The light-receiving section receives light from an object to generate an analog video signal. The light-blocking section blocks the light to generate reference signals. The analog video signal is converted into a digital video signal. The reference signals are accumulated a predetermined number of times from a predetermined accumulation starting point on scanning lines forming an image of the object for a specific period. The accumulated signal is averaged to generate an average signal. A reference level of the digital video signal is adjusted based on the average signal so that the difference between the digital video signal and the average signal becomes zero. The number of times for accumulation is decided as 2n that is smaller than a specific number “m”, of the scanning lines for forming the image of the object. The accumulation starting point is decided as (m?2n)/2, “n” and “m” being positive integers.

Abstract: A progressive all-pixel scanning type solid-state image sensor adapted for curtailing the power consumption therein by lowering its read voltage with another advantage of reducing the pixel size. The image sensor comprises pixels arrayed to form a matrix, vertical transfer registers corresponding respectively to individual columns of the pixels, read gates formed correspondingly to the individual pixels for reading out signal charges from the pixels to the vertical transfer registers, and a means for applying phase-shifted read pulses respectively to plural kinds of read gate electrodes in the read gates.

Abstract: This invention is to provide a solid-state image pickup element including a sensor unit including a plurality of lines of photoelectric conversion units for generating charges from received light by photoelectric conversion, a memory unit including a plurality of lines of storage units for storing signals from the plurality of lines of photoelectric conversion units, a transfer unit for transferring a signal from the sensor unit to the memory unit, a control unit for causing storage units of an arbitrary block in the memory unit to output an image signal from the photoelectric conversion units and causing the photoelectric conversion units corresponding to the storage units of the arbitrary block to output a noise signal, and a subtracting unit for calculating a difference between the image signal and the noise signal.

Abstract: Exposure control for a solid-state imaging apparatus can be completed in a short time. First exposure information D1 and second exposure information D2 are prepared. The first exposure information D1 is for adjustment of an exposure time L for a CCD (1) through extension or reduction in the unit of one horizontal scanning period; the second exposure information D2 is for direct designation of an exposure time L. When the power is switched on, the second exposure information D2 is selected for supply to a timing control circuit (3). After a lapse of a predetermined time, the first exposure information D1 is then selected.

Abstract: An imaging apparatus having an imaging element for accumulating signal charge corresponding to an incident scene light flux in a photo-electric converting element section and transferring the accumulated signal charge through a vertical shifter to a horizontal shifter so as to be read out there from, and a shutter for selectively blocking the scene light flux to be incident on the imaging element is moved. The operating condition of the imaging apparatus is judged and the operation timings of the shutter and/or the imaging element are/is controlled on the basis of the judged operating condition. The operating condition judging function judges as the operating condition of the imaging apparatus at least one of the ambient temperature, the posture of the imaging apparatus, the power supply voltage level and the number of times of operation of the shutter.

Abstract: A solid-state electronic image sensing device applicable to a digital camera includes signal lines for feeding transfer gate pulses to transfer gates. The signal lines on an “N+1”, an “N+5” and an “N+13” row are connected together while the signal lines on an “N+3”, an “N+7”, an “N+11” and an “N+15” row are connected together. Likewise, the signal lines on an “N+4”, an “N+8”, an “N+12” and an “N+14” row are connected together. Further, the signal lines on an “N+6”, an “N+10” and an “N+14” row are connected together. Six kinds of signal lines, i.e.

Abstract: A digital camera including a CCD imager and a complementary color filter mounted on a light receiving surface thereof. The complementary color filter has color blocks each having 8 rows×4 columns while the CCD imager has, at its light receiving surface, pixel blocks corresponding to those color blocks. The color block is assigned in its each row, with all the kinds of color components, i.e., G, Mg, Ye and Cy, at least one in number per kind. A timing generator reads, from respective columns, pixel signals including all the kinds, of color components at least one in number per kind. A timing generator reads from respective rows pixel signals including all tile kinds of color components at least one in number per kind, and transfers the read pixel signals in vertical direction. The timing generator also transfers the pixel signals in a horizontal direction each time vertical transfer by 8 rows has been completed.

Abstract: A digital pixel sensor-based modular digital imaging system includes several integrated circuit modules. At least one module includes an integrated circuit die having a digital pixel sensor array and a frame buffer, and at least one module includes an integrated circuit die having control circuitry and/or I/O circuitry. In certain embodiments all component modules are generally the same; in other embodiments the component modules include different integrated circuits that perform different functions. A higher pixel count imaging system may be made by disposing several component modules having lower pixel count digital pixel sensor arrays adjacent one another.

Abstract: A separate-type camera lens vehicle reversal monitoring device comprised of an individually disposed camera lens, imaging component, image processor, and power supply circuit that are interconnected by a transmission cable, an arrangement that enables minimum component exposure and simple installation which increases product utility and provides for vehicle reversal safety.

Abstract: An amplifying type solid-state image sensor comprises, in each of unit pixels arrayed to form a matrix of rows and columns, a photoelectric conversion element, an amplifying element having a storage to store a signal charge transferred thereto from the photoelectric conversion element and serving to convert the signal charge of the storage into an electric signal, and a selector switch for selectively outputting the pixel signal from the amplifying element to a vertical signal line. The image sensor further comprises a reset circuit in each of the unit pixels for resetting the storage of each amplifying element every time a pixel signal is outputted from the pixel. A pre-reset signal and a post-reset signal are delivered from each unit pixel and then are transferred via a common path, and the difference between such signals is taken to suppress not only the fixed pattern noise derived from characteristic deviation in each unit pixel but also vertically correlated fixed pattern noises of vertical streaks.

Abstract: An imaging apparatus can obtain a high quality still picture imaging signal in the all pixels read out mode and output it by means of an output processing means adapted to the interlaced read out mode. The imaging signal read out from a CCD image sensor 23 in the interlaced read out mode is directly supplied to a DV recording/reproducing processing section 4 by way of a camera signal processing circuit 24. The imaging signal read out from said CCD image sensor 23 in the apparatus is converted into an interlaced signal by a scan conversion section 3A, which is then supplied to the DV recording/reproducing processing section 4.

Abstract: A high frame rate high definition imaging system and method are disclosed. An imager is clocked asynchronously to a desired output video clock. During a frame cycle, data held in a first portion of the pixel array in the imager is clocked out of the imager using an imager clock signal, and data held in a second portion of the pixel array is bypassed. The imager data is subsequently converted to a higher video clock rate and output as desired video data.

Abstract: An imaging device includes a matrix array of photosensor pixels. An effective area in the array is set to a first region during a first mode of operation of the imaging device, and is set to a second region during a second mode of operation of the imaging device. The first and second regions are different in number of photosensor pixels contained therein. A holder retains the array. The holder is moved between a first position at which an optical axis related to light incident to the array coincides with a center of the first region and a second position at which the optical axis coincides with a center of the second region. The holder is fixed at the first position during the first mode of operation of the imaging device, and is fixed at the second position during the second mode of operation of the imaging device.

Abstract: Featured is a method for driving a CCD imaging device, including a plurality of photodetector columns each including a vertical array of photodetectors, a plurality of vertical CCDs, and a horizontal CCD, in a monitoring mode where only the signal charges from some of the photodetectors are used. The method includes reading a first signal charge from any one of said some photodetectors into a corresponding first packet of a corresponding one of the vertical CCDs, dividing the first signal charge in the first packet into smaller portions and placing one or more of the signal charge portions of the first signal charge into one or more second empty packets of the corresponding one of the vertical CCDs, and vertically transferring the signal charge portions in the first and the one or more second packets by the total number of the first and second packets.

Abstract: A programmable two-dimensional timing generator according to the invention employs a clock generator (102) and a user-defined two-stage waveform generator (106, 108). A single static random access memory (SRAM) (112) stores a user-defined waveform control word for both waveform generator control units. The SRAM data is entered via the host controller external data bus. A single waveform control word may be used to control both waveform generators.

Abstract: Defective sweep occurs when strong light enters, i.e., a quantity of input light increases, and smear and blooming components increase during an exposure period because a quantity of unnecessary charge to be swept during a sweep-out transfer period of a first field side exceeds a quantity of charge to be handled. The inventive image pickup system solves the above-mentioned problem by setting the sweep-out transfer period of the first field side to be longer than the sweep-out transfer period of a second field in a digital still camera which controls an exposure time by using a mechanical shutter in using as an image pickup device, a solid-state image pickup device which carries out the sweep-out transfer of transferring and sweeping charges within a vertical transfer section quickly more than transfer speed in transferring the signal charges read out from a sensor section to the vertical transfer section before reading out the signal charges from the sensor section to the vertical transfer section.

Abstract: Apparatus for reducing exposing time of an image processing system is disclosed herein. The image processing system including a shift register coupled to a photo-sensing means, the photo-sensing device is used to convert an optical image from a lens to a plurality groups of charge to form an electrical signal. The apparatus includes control device (counter) and a reset gate. The control device generates the first reset signal and the second reset signal depending on whether the image processing system is in a first resolution mode or a second resolution mode. A first number of cells of the photo-sensing device are exposed to the light of the optical image during the first resolution mode, and a second number of cells of the photo-sensing device being exposed to the optical image during the second resolution mode. The first number of cells is greater than the second number of cells.