Abstract: Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

Abstract: Implementation efficient video decoder for decoding multiple bitstreams to provide picture-in-picture capability in a digital video display device is disclosed. The video decoder includes a full resolution video decoder and a reduced resolution video decoder. The reduced resolution decoder decodes and downsamples video images using the same video memory device used by the full resolution decoder. By using a sufficient amount of downsampling, the amount of memory required to implement the video frame memory and decoder buffer required by the reduced resolution video decoder is reduced to a point where the frame memory and decoder buffer can be implemented using excess memory which is left over from the implementation of the full resolution decoder frame memory and decoder buffer. Accordingly, the present invention avoids or reduces the need to provide additional memory for frame storage when implementing picture-in-picture capability in a digital video display device.

Abstract: A method and apparatus for compensating for a position of a main picture displayed on a display screen of a display includes a sub-picture processor, a chroma processor and a display controller. The sub-picture processor receives an intermediate frequency signal of a sub-picture, and produces a sub-picture video signal of a predetermined aspect ratio from the intermediate frequency signal. The chroma processor receives a main picture video signal representing the main picture, and the sub-picture video signal. The chroma processor generates a composite video signal from the main picture video signal and the sub-picture video signal, and outputs the composite video signal to the display. The display controller controls the sub-picture processor and the display such that the main picture and the sub-picture are displayed on the display screen with a position of the main picture shifted on the display screen in a first mode of operation.

Abstract: An apparatus and method for calculation of the inverse discrete cosine transform for image decompression are disclosed. The apparatus may be implemented with approximately 10,000 transistors for MPEG2 main level speed and with less than 10,000 transistors for MPEG1 main level speed.

Abstract: A display is to be produced based on video signals having aspect ratios of 4:3 and 16:9. Controller 21 turns on switches SW1 and SW2 so that the digitalized video signal of the first picture is compressed at a rate of 3/8 in the time axis. Simultaneously, the video signal of the second picture is converted digitally, written into memory 14 in synchronization with the first picture video signal, read out based on a delay of 3H/8 from the synchronization with the first picture video signal, and sent to a digital processing circuit 13. The controller 21 controls the digital processing circuit 13 so as to compress in the time axis the video signal of the second picture at a compressing rate of 5/8. Also, the controller 21 controls a vertical amplitude switching signal generator 19 to adjust a vertical deflecting current in a deflecting circuit 18 based on an operation by the audience.

Abstract: A television receiver has horizontal reducing filter and a vertical reducing filter independently responsive to a first filter control signal and a second filter control signal for reducing auxiliary luminance/chrominance signals indicative of a sub-picture at an arbitrary aspect ratio, and a display unit reproduces a main picture and a reduced auxiliary picture on a screen in an overlapped manner.

Abstract: A single line buffer in a motion video card is used for both vertical reduction of the pixel image before storage in a video memory buffer and vertical expansion of the pixel image after being outputted by the video memory buffer. When the desired display size is smaller than the original pixel image size, then the line buffer is used by the input pipeline to reduce the image. When the desired display size is larger than the original pixel image size (or larger than the image stored in the memory buffer), then the line buffer is used by the output pipeline to enlarge the image.

Abstract: A video display for a television apparatus has a wide format display ratio and is synchronized with a first video signal representative of first picture. A PIP processor is responsive to a second video signal representative of a second picture to define an auxiliary picture smaller in size than the video display. A FIFO line memory stores successive lines of video information representative of the auxiliary picture, which are combined with certain successive lines of video information representative of the first picture. A counter initialized at a time corresponding to the start of each horizontal line of the first video signal generates a variable time delay. A FIFO control circuit successively initiates a transfer of the lines of video information representative of the auxiliary picture from the line memory for combination with the video information representative of the main picture after the variable time delay.

Abstract: The bandwidth capability of a full-motion video buffer is prevented from being exceeded by automatically controlling the horizontal scaling of the incoming video data and the horizontal zooming or expansion of the outgoing display data to force the bandwidth of the video data to virtually match the bandwidth capability of the video buffer. In one embodiment, this automatic control of the horizontal scaling and zooming is performed in a dynamic fashion where a detector detects the dropping of any video bits caused by the bandwidth of the incoming video data exceeding the bandwidth capability of the video buffer. Upon detection of these dropped bits, the horizontal scaling of the incoming video data is incrementally reduced (and the horizontal zooming is proportionally increased) until the bandwidth of the incoming video data is at or below the maximum bandwidth capability of the memory buffer. In this way, the video buffer cannot be overdriven and no video data is lost.

Abstract: A processing unit (13) for providing secondary images in a video display system (10) in accordance with a choice of scaling ratios. The processing unit (13) scales the luminance component of an analog input signal by first using an analog low pass filter (22) for anti-aliasing, and then sampling (23) the data at a rate appropriate for the selected scaling ratio. The sampled data is processed by a digital filter (24), on a line-by-line basis, which provides weighted average values derived from the sampled data, on a line-by-line basis. A formatter (25) combines sampled chrominance data with the filtered luminance data, and selects lines for inclusion in the secondary image.

Abstract: A television signal processing circuit that includes a display device having a screen with an aspect ratio of m1:n1 (m1<n1), a circuit for displaying a main-picture originated from a first television signal on the display device, a processor for superimposing a sub-picture originated from a second television signal with a reduced size smaller than the main-picture on a part of the main-picture by thinning out the scanning lines of the second television signals, a selector for selecting the display mode of the main-picture between a normal display mode associated with a first number of scanning lines and a zoom display mode associated with a second number of scanning lines less than the first number of scanning lines as well as an expanded vertical amplitude, and a thinning-out processor responsive to the selecting means for thinning out the scanning lines of the sub-picture, either to display the sub-picture at an aspect-ratio of m2:n2 (m2<n2) by thinning out the scanning lines of the sub-picture to 1/a

Abstract: A vertical filter circuit comprises a first shifter connected to an S/P converter, a calculation circuit connected to the first shifter and a second shifter, a buffer memory connected to the calculation circuit, first and second delay circuits each connected to the calculation circuit, and a second shifter connected to the first and second delay circuits. The first delay circuit comprises a first write selector, a first line memory, and a first read selector, all of which are connected in series. The second delay circuit comprises a second write selector, a second line memory, and a second read selector, all of which are connected in series.

Abstract: A picture overlay system assures proper size and placement of picture overlays in simultaneous picture displays. The system comprises a video memory and a control circuit for writing and reading information from a video signal into and out of the video memory, the information relating to video data and field type. A reading circuit supplies information from the video memory synchronously with a display for another video signal. An interpolator selectively compresses and expands the information read from the reading circuit. The field type information undergoes the compression and expansion together with the video information. A decoding circuit decodes the field type information to identify first and second types of fields and an absence of valid video data. A multiplexer combines the video signals for simultaneous display, operating responsive to the decoding circuit.

Abstract: A video display system comprises: a video display; first and second signal processors for cropping first and second video signals representative of first and second pictures; a circuit for generating a side-by-side display format of the pictures on the video display; and, a panning control circuit, responsive to panning command signals, for positioning said pictures in the side-by-side display format and for independently panning the pictures, as positioned. The panning control circuit generates independent fixed and variable delays for controlling line memories in the signal processors. Fixed delays control picture positions and variable delays control panning.

Abstract: The present invention relates to an apparatus and method for processing a picture-in-picture video signal for PIP display of a compressed sub-picture displayed within a main picture on advanced TV receivers. More particularly, the present invention relates to the apparatus and method for processing a PIP video signal of advanced TV systems which use real video data lines, as opposed to artifically generated lines of video data, as the interleaving line to interleave the present field being compressed, when vertically compressing a sub-picture video signal. Accordingly, the present invention provides a hardware of simple constitution and a PIP display with advanced resolution.

Abstract: For decoding compressed digital image data of source image, end-of-block (EOB) codes appearing in entropy coded data are utilized to detect a portion of "0" elements in a frequency range coefficient matrix. An inverse orthogonal transform process is fully or partly omitted according to the "0" coefficient distribution.

Abstract: A method for generating a picture-in-picture digital television frame comprises the steps of: converting a first analog television signal into a first digital frame comprising a first prescribed number of pixels; deriving a mean-only frame from the first digital frame, the mean-only frame comprising a second prescribed number of pixels; creating an insertion frame on the basis of the mean-only frame; and inserting the insertion frame into a second digital frame, thereby generating a picture-in-picture digital television frame. A Vector Quantization receiver/decoder comprises a mean-only decode section 20, a full decode section 30, and an image inserter 40.

Abstract: A vertical direction filter is realized without using an additional memory. If a reduction ratio is larger than 1/2, line memories (11) and (12) are connected in series with each other by switches (SW1) and (SW2) to thereby form one line memory which is capable of storing one original memory. If the reduction ratio is equal to or smaller than 1/2, inputs to and an output from the line memory (11) are each filtered by calculator units (13) and (14) and an adder (15) and then given to the line memory (12) and the switch (SW2) through the switch (SW1) as data about a filtered reduced line. Since the reduction ratio is equal to or smaller than 1/2, the line memories (11) and (12) are both capable of storing one reduced line. An output of the line memory (11) is given to an output terminal (71b) while an input to the line memory (11) is given to an output terminal (71c ) through the switch (SW2). Thus, the line memories which are used in vertical decimation also function as a filter.

Abstract: A method and an apparatus for converting a video signal having a predetermined aspect ratio into a signal adapted for a television receiver having a wider aspect ratio. An analog to digital converter converts the received video signal into a digital signal. A main picture processor converts the video signal of the first aspect ratio into a main screen of the television receiver. A picture-out-picture processor converts the video signal having the first aspect ratio into at least one picture-out-picture screen of the television receiver. A multiplexed picture formation portion multiplexes the video signals for the main and picture-out-picture screens into a video signal having the second aspect ratio appropriate for the television receiver. A control signal generator controls the picture-out-picture processor and the multiplexed picture formation portion.

Abstract: A wide screen television apparatus comprises a video display having a first format display ratio of width to height, for example approximately 16.times.9. A first video signal defines a first picture. A second video signal defines a second picture in a second format display ratio of width to height smaller than the first format display ratio, for example approximately 4.times.3. A video signal processor asymmetrically compresses the second picture, for example 4:1 horizontally and 3:1 vertically. A video memory stores lines of video of the asymmetrically compressed picture. Another video signal processor combines portions of lines of video in the first video signal with the stored lines of video of the asymmetrically compressed picture for simultaneous display of the first and second pictures. The asymmetrically compressed second picture is displayed without aspect ratio distortion. The second picture can form an inset within the first picture.

Abstract: A multi-picture treatment apparatus which, can display several video signals on one screen, and which can compress input signals to be displayed on one screen in multi-pictures, and at the same time, can transmit external input messages to the multi-pictures so as to be displayed along with the pictorial images.

Abstract: A line memory and control system comprises a line memory, for example a first in first out (FIFO) device. A comparator compares a first value, specifying a location in the horizontal line period where reading or writing of the line memory is to begin, with a second value, fixing pixel location within each line period. A register stores the number of data samples stored in the line memory. A counter counts the number of data samples which have actually been written into the line memory or read from the line memory. The counter has an output of the comparator as a first input and the number of data samples previously stored in the line memory as a second input. In the case of both compression and expansion, a line memory control system assures that the number of samples written into each FIFO line memory be the same as the number of samples read out of each FIFO line memory.

Abstract: A video system comprises a video display having a wide format display ratio for displaying a video signal. A signal processor has an interpolator and a first in first out line memory having asynchronous write and read ports for selectably expanding and compressing a picture represented by data in the video signal. The picture is cropped to define a subset of the picture for display by controlling writing of the data into the line memory. A microprocessor for controls provides control signals with selectable time durations and selectable phases relative to a synchronizing component of said video signal for selecting boundaries of the subset of the picture for display. The microprocessor can select the time durations and the phases responsive to user commands.

Abstract: Alkylamide derivatives having the formula, These compounds have a strong antiulcer action depend on histamine H.sub.2 -receptor antagonistic action and a cytoprotective action upon gastric mucous membrance.