Abstract: The invention provides an image communication apparatus in which an image input unit for entering image and a portable communication unit capable of wireless connection with a public wireless network are constructed in separate manner and are rendered capable of mutual wireless communication.

Abstract: A data storage unit of an image compression device for compressing motion picture frame is provided. The data storage unit comprises: a previous frame field having a plurality of slices; a decoded frame field having a plurality of slices; and a current frame field having a plurality of slices, wherein the previous frame field stores a previously decoded image and the decoded frame field stores a currently decoded image, wherein the number of slices of the previous frame field is greater than the number of slices of the decoded frame field and the current frame field.

Abstract: In a liquid crystal display (LCD) panel based display, a method of dynamically selecting either frame rate conversion (FRC) or pixel voltage overdrive is disclosed. The method is carried out by performing the following operations. A video vertical refresh rate of an incoming video data stream is determined and based upon the determining, only one video data stream conditioning protocol from a number of available video data stream conditioning protocols is selected. The selected video data stream condition protocol is then applied to the video data stream.

Abstract: A video processing circuit for preventing generation of contour noise irrespective of varied directions of light emission schemes. A first video signal and a second video signal delayed by a predetermined field are received, a first motion detection result is output when a signal level of the first video signal is greater than that of the second video signal, and a second motion detection result is output if the second video signal is greater than the first video signal. A flag is established according to the first motion detection result, and a third video signal generated by delaying the first video signal is output. The lighted pattern of the third video signal is switched according to the second motion detection result and the flag.

Abstract: Each functional block constituting a pipeline resets its own memory device in synchronization with a timing that last pixel data of one line is processed and output. A reset controlling unit in a first functional block includes an attribute signal generation circuit for generating an attribute signal indicating whether or not each pixel data being input is last pixel data and attaches this attribute signal to the pixel data by transferring in synchronization with corresponding pixel data. When the processed pixel data is output, the attribute signal of the corresponding pixel data is referred to control resetting the memory device. Other functional blocks control resetting their own memory devices using an attribute signal synchronized with the pixel data and transferred from previous functional block.

Abstract: An exemplary method relates to buffering closed captioning data.

Abstract: A method and an apparatus for an integrated high definition television controller are described. The integrated high definition digital television controller includes two or more the following functions in a single chip: MPEG2 Transport, Audio and Video Decoders, Video input capture and converter, flexible video scan rate converter, de-interlace processor, display controller and video D/A converters, graphics controller, a unified local bus, N-plane alpha blending, a warping engine, audio digital signal processor, disk drive interface, peripheral bus interfaces, such as PCI bus and local bus interfaces, various I/O peripherals, a bus bridge with a partitioned chip, and a CPU with caches. The integrated controller, in one embodiment, is designed to handle multiple television standards (for example ATSC, ARIB, DVB, AES, SMPTE, ITU) and designed to be deployed in various countries in the world.

Abstract: A system and method for displaying frames with dynamically changing display parameters is described herein. The display engine stores new display parameters detected by the decoder in one buffer of a ping pong buffer, while continuing to use another set of display parameters stored in the other ping pong buffer. The display engine switches the buffers when the first frame for which the new display parameters are applicable is to be presented.

Abstract: A method of processing video data in a receiver/decoder including at least one port (31) for receiving data and memory means (40) including a data buffer area (45A0, 45A1) for storing incoming data for display, and a graphics buffer area (45Ai) for storing graphics data, said method including passing graphics data stored in the graphics buffer area to the data buffer area for combination with display data stored therein.

Abstract: A video system that performs TV signal decoding, deinterlacing, and de-motion-blurring for progressive scan flat panel display is introduced. The system embeds a frame buffer and a scaler for conducting format and resolution conversions for display panels of different sizes. The output of the scaler is sent to a de-motion-blur processor for reducing the blurriness due to the motion of image objects and the slow response time of flat panel display devices. The de-motion-blur processor gets the motion and noise indication signal from scaler or the pre-frame-buffer video processor. Based on the motion and noise information and the information of temporal difference, the de-motion-blur processor performs over driving for the display panel interface and improves the rising and falling response time of the flat panel display. The decoding, deinterlacing, and de-motion-blur processing share the same frame buffer controller so the entire system can be optimized in cost and performance.

Abstract: A video signal processing system for processing a video data VIN and graphic data D?P includes a filter unit, which receives the video data VIN. The filter unit filters the video data VIN to convert the video data VIN into video pictures formatted with a different number of columns and/or lines, and provides a filtered video signal indicative thereof. The filter unit buffers individual pixels and/or lines in a first memory device. A second memory device receives and stores the graphic data D?P and the filtered video signal and provides stored signals indicative thereof. A third memory device is connected to the second memory, and stores data received from the second memory device. A mixing unit receives and mixes the stored graphic data and the stored filtered video data to provide a video output signal VOUT.

Abstract: First selected image frames in a native format are read from a frame storage device (103) and are directly modified in response to a first process. Output signals are supplied to a display device (102) such that the display device displays a view of stored frames. The frames are stored in the native format but appear in the view as if stored in an alternative format. Frames are selected and in response to receiving input selection signals, selected frames are translated into an alternative format and supplied to a second process in the translated formats.

Abstract: The present invention provides an image processing apparatus and an image processing method. The image processing apparatus includes: a first to a fourth writing FIFO unit and a first to a fourth reading FIFO unit (hereinafter referred to as “FIFO units”) for temporarily retaining image data to write to and read from a data retaining memory; a memory access control unit for performing access to the data retaining memory, the access being requested by the FIFO units; and a writing data control unit for shifting, at all times by a predetermined time, timing of the request made by at least one of the FIFO units to the memory access control unit in comparison with timing of the request made by the other FIFO units to the memory access control unit.

Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.

Abstract: A method for scrolling MPEG-compressed pictures consists in decoding a sequence of pictures (34, 35, 36) or any two pictures to be viewed by a MPEG decoder (5) and storing the sequence of pictures (35, 35, 36) or any two pictures in MPEG decoder memory. Then the sequence of pictures (34, 35, 36) or any two pictures is formed as a group of pictures (37), which is transferred to the first screen buffer (24) which is active. In the following step, any another compressed picture, after decoding in the MPEG decoder (5), is stored in a MPEG decoder memory as a decoder new picture and then is transferred from the MPEG decoder memory to the first screen buffer (24), where its edge line perpendicular to the intended scrolling direction is adjoined to the external edge of the group of pictures (37).

Abstract: An electronic program guide (EPG) hardware card is disclosed. The card is insertable into a television tuning device having EPG capability. A non-volatile memory, such as flash memory, is situated within a case of the hardware card, and has data stored thereon representing one or more loader programs for the device. Each program corresponds to an EPG provider, and gives the device the capability to receive EPG information from this provider. The case of the hardware card may have a form factor such as a Smart Card, a Compact Flash, a Smart Media, or another form factor. Alternatively, the data stored on the card represents non-executable information corresponding to an EPG provider. A business model and a server-based embodiment are also disclosed.

Abstract: In a manufacturing process in a factory or in a maintenance process in a service center, an initial control program or an updated control program is easily written in a digital TV receiver. The digital TV receiver has an IDE connector to which an external memory apparatus through an IDE cable. A main controller judges whether the external memory apparatus is connected or not with utilizing opening terminals of the IDE connector. When the external memory apparatus is connected, the control program is read out from the external memory apparatus, and written into a control program memory of the digital TV receiver or the existing control program is replaced with the updated control program. When the external memory apparatus is not connected, the existing control program is read out from the control program memory and the digital TV receiver is controlled corresponding to the control program.

Abstract: A data elementary buffer with underflow and overflow operational constraints is incorporated into a digital televison receiver to regulate the flow of data related to an ancillary data service to be presented in synchronization with a video or audio program element. The data elementary buffer ensures that data is received in time for decoding and presentation in synchronization with the video or audio element. The data elementary buffer also limits the amount of data that the receiver may be required to cache. The minimum size of the data elementary buffer is three times the size of a nominal data access unit or three times the quantity of data that the receiver can receive at the maximum rate in the period that a video element is displayed by the receiver.

Abstract: Method for controlling a memory in a digital system, including the steps of (a) dividing the memory into a plurality of fixed sized memory blocks, (b) defining at least one of the memory blocks as a compression/decompression region, (c) assigning compression priorities to rest of the memory blocks except the memory blocks defined as the compression/decompression region, and (d) making the memory blocks to deal with an external data received according to an external command, and carrying out compression/decompression of data required in the dealing with the external data at the compression/decompression region according to the compression priorities.

Abstract: The objective of the invention is to provide an image processing device that can operate at high speed even if input/output with respect to the outside is performed at low speed, and that can fully exploit processibility, by means of input line memory 23 and output line memory 24, which can store image data of one scan line, and are arranged in the input unit and output unit, respectively; the input image data are written in input line memory 23 at the speed of the input image data; the image data that have been written to the input line memory are read at a speed n times faster than the input image data and are sent to processing unit 25 or memory unit 26; processing unit 25 and memory unit 26 receive the image data of one scan line at a speed n times faster than the speed of the input image data, perform a prescribed processing, and then output the processing results at a speed n times faster than the speed of the input image data; the image data output from processing unit 25 or memory unit 26 are selected

Abstract: A removable memory device is inserted into a channel information source computer, such as computer connected to the Internet, and channel map information is downloaded to it. The removable device is then removed from the source computer and engaged with a television to download the channel map into the television, thereby avoiding prolonged autoprogramming by the television's receiver.

Abstract: A system and method for processing YCbCr video data stored in a paged memory with reduced page breaks. A method is disclosed for retrieving YCbCr planar video data in 4:2:0 format from paged memory. A page of the paged memory containing Y data is accessed; Y data corresponding to M pixels of video data is then retrieved, where M is a value greater than or equal to two. The retrieved Y data is then stored in a shift register. Similar steps are taken to access, retrieve and store Cb and Cr data. Within the shift register, the Y, Cb, and Cr data is stored as sets of planar video data. The Y, Cb, and Cr data is retrieved from the shift register as a series of pixel data for generating pixels on a video display unit.

Abstract: The invention relates to a process and a device for time-managing the utilization of data detected in a data flow and constituting a data set. The device comprises a circuit (MP) for calculating a minimum duration of utilization of the detected data, which is proportional to the amount (L) of data contained in the data set. The invention applies more particularly to the case in which the detected data are digital data representing subtitles detected in a flow of data conveyed according to the MPEG 2 System transport standard. The utilization of the data then corresponds to the displaying of the subtitles.

Abstract: A video data transfer system which increases the rate of capturing video data into a system memory without being affected by a data bus and which prevents the display of data on a display unit from being affected even when data is being captured. Video data from a video processor 21 is sent, not via a frame buffer 14 but via a capturing-only path 26, directly to a system bus 17. This means that video data may be captured into a system memory 18 regardless of the status of a real time output path 25. On the other hand, video data is sent to a display 16 via the real time output path 25 provided independently of the capturing-only path 26. This means that video data may be sent to the display 16 at a constant rate regardless of whether or not data is being captured.

Abstract: A processing circuit for motion compensated de-interlacing of video signals, having a line memory 21, a de-interlacing circuit 22, a frame memory 24, and a cache memory 25, further includes a pixel mixer 29 interposed between the cache memory 25 and the de-interlacing circuit 22.

Abstract: A memory circuit achieves much higher bandwidth and reduced power consumption by maintaining the maximum number of memory arrays open simultaneously. Circuit area is also saved by sharing bit line sense amplifiers between adjacent arrays. When selected, an array remains open until a different row in the same array or an array adjacent to it is selected. Thus, as long as access is made to an open row of every other array, access time and power are reduced by eliminating the need to turn arrays on and off.

Abstract: An adaptive filter is adjustable for performing scaling operations. During a scaling operation, the adaptive filter stores scaled data in a memory such that more data samples may be retrieved during a subsequent scaling operation. The size of a finite impulse response filter used during the subsequent scaling operation may be adjusted to access the additional data samples.

Abstract: In a video-processing unit comprising a processing means, memory means and a memory manager, an output of the processing means is coupled to the memory manager for storing of the processed data from the processing means in the memory means to allow execution of different processes in video-processing unit by a single processing means.

Abstract: An apparatus such as a television signal receiver includes first and second circuit boards. The first circuit board includes a memory, and control circuitry for controlling at least one function of the apparatus. The second circuit board is operably coupled to the first circuit board via control lines. The second circuit board includes a controller for generating first and second control signals. The control lines transmit the first control signals from the controller to the memory when the apparatus is in a first operational state, and transmit the second control signals from the controller to the control circuitry when the apparatus is in a second operational state. To prevent inadvertent writes to the memory during the second operational state, the controller places the memory in an unpowered state when the controller transmits the second control signals to the control circuitry.

Abstract: Television receiver furnished with a memory (21, 22, 23) for receiving service data comprising a processing module (11) which correlates usage criteria received together with the service data and storage criteria characterizing the memory or memories of the receiver. By correlating the two criteria, the module determines the conditions of storage. Advantageously, a reorganizing module (12) can process the content of the memory so as to free some space in order to store new service data. The invention also relates to the storage process.

Abstract: A picture data memory device which can be used universally comprises a central picture data memory for storing picture data of a plurality of picture data input channels, in which case the stored picture data can additionally be read out via a plurality of picture data output channels for different kinds of further processing. A memory controller is provided for coordinating the individual storage operations of the picture data input channels and the individual rend-out operations of the picture data output channels.

Abstract: A special effect device by which an entirely new special picture effect is to be implemented in accordance with a read address control system. The device includes an address signal generating unit 3 which generates a readout address signal for picture signals stored in a frame buffer 2 so that, by rupturing a picture portion of an area at an optional position of a picture in the frame buffer, defined by a circle having a radius of an optional size, with the center of the circle as a rupturing point, a folded picture portion will be obtained which has the circumference of the circle as a topological boundary.

Abstract: A method for storing pages of a teletext service, with at least one page being received by a storage circuit of a television receiver, is provided. The storage circuit includes a data memory for storing the at least one received page. The method includes extracting a reference number from the at least one received page, checking whether the at least one received page is a requested page, and evaluating contents of the data memory to decide whether the at least one received page is to be stored as a function of free space in the data memory and an importance of the at least one received page. The method also includes storing the at least one received page if it is decided that the at least one received page is to be stored.

Abstract: A video signal processor and a video signal processing method which can prevent the length of one period of a clock from being shortened and can output a video signal that is in phase with a reference signal. When a video data signal that has been processed using a first clock signal is processed using a second clock signal, this video signal processor does not utilize as the second clock signal, a clock signal that is in phase with a reference signal but a clock signal that is employed in a later stage signal processor, and interpolates the video data signal by an interpolation circuit so as to make the signal in phase with the reference signal.

Abstract: An IR camera and a DV processing unit are disclosed which enable a user to use a standard DV recorder to record an IR film sequence and be able to play it back at a later time, and edit it, without using dedicated software. At the same time, the user has access to calibration data, enabling him the selection of data and processing of the film using dedicated software. This is achieved by including additional data related to the image processing in the signal, preferably in the part of the signal normally reserved for audio information.

Abstract: A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).

Abstract: Data from a video source are downscaled prior to storage in memory. This results in using less memory to store the image, less bandwidth in transmitting the image to the memory and display, and a reduction in power consumption. Downscaling may use methods of interpolation and a combination of dropping pixels and lines from the original image. The device and method require no decompression of data.

Abstract: Disclosed is an image processor with frame-rate conversion that can perform frame-rate conversion of a video signal with a single frame memory. In this image processor with frame-rate conversion, input digital video signals are successively written on the frame memory with a timing synchronized with a vertical synchronization signal included in the input digital video signals. During this time, a frequency signal that mainly consists of a train of N pulses for every M cycles of the vertical synchronization signal is generated as a vertical synchronization signal being rate-converted, and the input digital video signals stored in the frame memory are read out in the order in which they were written with a timing synchronized with the vertical synchronization signal being rate-converted. Such a configuration makes it possible to convert the input digital video signals to video signals having a desired vertical synchronization frequency with use of a single frame memory, thereby converting frame-rate.

Abstract: A television based on an operating system, including: a first memory storing a boot loader program, the boot loader program performing a hardware basic test and a booting; a television signal generating portion outputting a television broadcast; a second memory storing a MPEG control program and preset channel information, the MPEG control program driving the television signal processing portion to output a video signal corresponding to a received television broadcast corresponding to the stored preset channel information; and a central processing unit executing the boot loader program, executing the MPEG control program after the hardware basic test of the boot loader program and loading the operating system onto a random access memory after the MPEG control program drives the television signal processing portion to output the video signal corresponding to the received television broadcast corresponding to the stored preset channel information.

Abstract: A method and system for buffering pixels of a pixel line such that complex processing circuit between a horizontal format converter buffer and a horizontal format converter filter is not required. The horizontal format converter buffer (52) includes multiple parallel circular buffers (60, 62 and 64) that are addressable by a controller (54) such that a variable sequence of pixels may be read from the horizontal format converter buffer (52) to the horizontal format converter filter. The controller (54) may turn off selected circular buffers (60, 62 or 64) of the horizontal format converter buffer (52) if the selected buffers (60, 62 or 64) are not necessary for processing a pixel line.

Abstract: A system and method are provided for frame capture and redisplay in a stand-alone television. The method comprises: down-converting a television signal including a plurality of frames; selecting an accepted frame; capturing the selected frame; storing the captured frame; selecting a stored frame; and, displaying the selected frame. Some aspects of the method further comprise: storing auxiliary information with the stored frame, such as time, date, or channel. Then, displaying the frame includes displaying the frame with the auxiliary information. Other aspects of the method further comprise: accepting a remote capture and remote display signals from a television remote control. Down-converted frames are selected for storage, and stored frames are selected for display in response to the remote signals. In other aspects, stored frames are displayed as thumbnail displays. For example, a single thumbnail display, or a group of thumbnail displays can be presented overlying the down-converted television signal.

Abstract: A cache memory system for use in a motion estimation system is disclosed. The system includes: a first cache memory defined in terms of a first width and a first height, and a second cache memory defined in terms of a second width and a second height, wherein said second height is less than said first height, the cache memory system being operable in one of two modes: the first mode being characterized by banks of memory from the second cache memory being concatenated vertically such that their concatenated height is at least equal to the first height, and said concatenated banks being arranged to be appended to the width of the first cache memory to form a single contiguous address space; and the second mode being characterized by banks of memory from the first and second cache being stacked vertically, and being arranged to be addressed as two separate address spaces.

Abstract: “An image processing system, in which bit shuffling is done in order to maintain image quality, stores digitized video data bits stream in a conventional memory, such as a DRAM. The image processing system is suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the DV-SD standard, or “Blue Book”). The image processing system receives a number of blocks associated with a first video frame and stores these blocks in the DRAM. The image processing system receives and stores blocks associated with a second video frame in the DRAM. The image processing system, processes the blocks of the first video frame while storing the blocks of the second video fame.

Abstract: One frame of an image having 1312 pixels in the horizontal direction thereof is divided into 192 pixels at a time in the horizontal direction to obtain a plurality of image areas. The one frame of image data is subjected to synchronization processing repeatedly using a line memory that is capable of storing 192 pixels of data.

Abstract: Compressed audio video data is constituted by a sequence of video information blocks each of which constitutes one unit by a predetermined number of I pictures, a predetermined number of P pictures and a predetermined number of B pictures. In a case of reproducing one of the pictures of the compressed audio video data as a still picture by motion compensation prediction, when a picture stops at the B picture, one of the I pictures closest to the B picture or one of the P pictures closest to the B picture is selected, and the I picture or the P picture thus selected is displayed on a monitor in place of the B picture.

Abstract: Imaging apparatus having a video memory function includes a video memory having a plurality of read ports and a capacity of storing images in two fields or more, wherein CCD storage sensitivity enhancement means is connected to a write port; a write control circuit for storing a single-field image in each memory area provided by dividing the storage space of the video memory into a plurality of sub-spaces; a plurality of read control sections for reading a single-field image stored in each memory area; and memory control means for reading an image from the video memory by a delay amount corresponding to the timing of a synchronization signal from the CCD storage sensitivity enhancement means. This configuration allows adjustment of the delay amount and prevents an image write address from passing by an image read address so that image data given CCD storage sensitivity enhancement is processed normally.

Abstract: A method of rapidly generating motion vector predictions based on vertical and horizontal position categorization of macroblocks within a video object plane (VOP) for use within a video decoder or encoder. By way of example, the location of the subject macroblock is categorized vertically as either Upper_Edge or Not_Upper_Edge, and horizontally as either Left_Edge, Right_Edge, or Not_Edge. The position categories are utilized in conjunction with selected block number (Block1 through Block4) within the luminance macroblock within a decision-tree which generates three predictors MV1, MV2, and MV3. The prediction rules may be implemented within hardware, software, or combinations thereof, within both video encoders and decoders, such as according to the MPEG-4, H.263, or similar standards.

Abstract: A television receiver comprising a tuner, a microprocessor, a communications bus and a rewritable memory, e.g., an electrically erasable programmable read only memory (EEPROM). The memory is programmed to contain the tuner parameters for a tuner. The memory can be programmed to be matched with a tuner such that, on the manufacturing floor, the tuner from each manufacture is supplied with a matched memory for the television chassis that the tuner and memory are going to be placed within. The tuner parameters are recalled by the microprocessor and used to facilitate tuning of the tuner in a conventional manner.

Abstract: A method for the storage of sub-pages of a teletext service comprises a page (Y0) to be stored, said page (Y0) to be stored comprising at least one sub-page. A desired sub-page is stored (E2, E4) and, as the case may be, sub-pages neighboring the desired sub-page are stored (E5) until a maximum number of stored sub-pages (MAXY0) is reached or until a limit number (NB_LIMY0) of sub-pages of the page to be stored is reached. In one example, the desired sub-page is the rank 1 sub-page of the page to be stored, and the neighboring sub-pages, if any, are the following sub-pages. A user thus has direct access to the start of the information contained in the page to be stored. In another example, the desired page is a rank X0 sub-page requested by a user, and the sub-pages neighboring the desired sub-pages are pages with ranks 1, X0+1, X0−1, etc.

Abstract: An audio and video recording and reproduction apparatus and method is described, which uses a movable storage memory such as a memory card, so that audio and video signals are easily accessed without separate editing devices. The apparatus uses a separable memory so that a deck is unnecessary, allowing small, lightweight constructions, and a compression algorithm results in longer playing time, while read/write operations robust to noise are achieved. Also, data desired by the user is easily accessible, and applications as a substitute for magnetic or disk media are also possible.