Abstract: Pictures recorded by a digital camera can be stored and utilized by a method convenient and appropriate for the situation. The system comprises variety of means for transferring picture image data recorded by a variety of digital cameras to an image server installed in a DPE or the like and a variety of accessing means for enabling the picture image data stored in the image server to be accessed.

Abstract: Video data formatting apparatus and method in which an input signal is converted (transcoded) into an intermediate compressed video signal, where the intermediate compressed video signal has a GOP format in which each GOP contains fewer pictures than a GOP associated with the input video signal. A metadata signal which indicates data defining coding decisions is derived from the input video signal. A data quantity allocation is generated to control the transcoding into the intermediate video signal, whereby each picture of the intermediate video signal is transcoded so as not to exceed a respective data quantity allocation.

Abstract: A memory management process for buffering progressive, interlaced, CCIR 601/656 compliant, and MPEG compliant video signals in a video memory that is partitioned into first and second buffers. The process includes identifying the format of a received video signal, buffering the received video signal in the video memory in accordance with a standard buffering mode if the video signal is in an interlaced, CCIR 601/656 compliant, or MPEG compliant format, and buffering the received video signal in the video memory in accordance with an override buffering mode if the video signal is in a progressive format such as a 240p signal generated by a game console, VCR, cable text generator, and the like.

Abstract: The present invention provides a display controller for scaling an input source image. The display controller dynamically adjusts the output clock so line buffer requirement is reduced to a minimum to balance input and output image timing for image scaling or non-scaling to destination devices. The present invention supports up-scaling and down-scaling or bypass. The blocks of the line buffer operates in a continuous and cyclical manner according to the status signal generated by the line buffer status detector and the output clock. As a result, any buffer overrun or underrun condition will be immediately corrected by the timing and therefore the number of blocks of line buffer are greatly reduced.

Abstract: A video processor card stores tap generation information for determining a predetermined tap coefficient when the tap generation information is used together with tap generation information stored in another video processor card, and supplies a video processing interface with the tap generation information. The video processing interface generates the tap coefficient from the tap generation information of the one video processor card and the other video processor card loaded therein. The video processing interface extracts video data having a predictive tap used to predict a target pixel and video data having a class tap used to classify the target data, and class classifies the target data based on the class tap. The video processing interface determine the target pixel based on the tap coefficient and the predictive tap of the class of the target pixel.

Abstract: A receiver for detecting a predetermined SD broadcast program transmitted at a high speed using an HD broadcast channel, storing the detected predetermined program in a storage, and reproducing a broadcast signal of the predetermined program stored in the storage at a speed faster than the normal reproduction speed.

Abstract: An apparatus for automatically searching information includes an extraction unit extracting a packet data from a broadcasting signal; an input unit for inputting searching conditions from a user; a receiving unit receiving the searching conditions; a server connection unit connecting a computer to an Internet server under the searching conditions and receiving and transmitting data of an Internet site; an interpreter judging whether the data received and extracted by the server connection unit and the extraction unit meets the searching conditions: a memory storing a content of the Internet site, its address, and time point information of when the site was previously searched by the user in a file form; an output unit transmitting the time point information and the data of the Internet site to the memory; and a microprocessor controlling operations of each element, with which various information desired by a user is searched based on pre-set searching conditions, and desired information out of various informa

Abstract: In order to reduce memory requirements in a chip for demodulating digital video broadcast signals, symbol data values stored for a channel equalisation process have their scattered pilots removed, to achieve a 9% reduction in memory space required. This is achieved by providing a write pointer and a read pointer, the write pointer being arranged to exclude carriers carrying scattered pilots, and the read pointer being arranged to read the stored symbol data, but to add nominal data values at positions of excluded scattered pilots.

Abstract: A digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slice processor having an input coupled to the slice-buffer memory. The vertical slice processor reassembles the vertical slices into processed raster-scanned data in an output buffer that is coupled to the output of the vertical slice processor. The digital image processor preferably utilizes multiple sequential processing stages and processes the raster-scanned data along the horizontal axis of the vertical slices.

Abstract: A data elementary buffer with underflow and overflow operational constraints is incorporated into a digital televison receiver to regulate the flow of data related to an ancillary data service to be presented in synchronization with a video or audio program element. The data elementary buffer ensures that data is received in time for decoding and presentation in synchronization with the video or audio element. The data elementary buffer also limits the amount of data that the receiver may be required to cache. The minimum size of the data elementary buffer is three times the size of a nominal data access unit or three times the quantity of data that the receiver can receive at the maximum rate in the period that a video element is displayed by the receiver.

Abstract: Decoded data, which has been output from a decoder, is stored on storage so as to be presented or used for decoding another encoded data. A presentation method recognizer recognizes a presentation method for the decoded data. If the presentation method has been changed into a new presentation method, the recognizer sets the number of frame memories as required by the new presentation method. In that case, a memory allocator allocates the same number of sub-areas of the storage area as that set by the recognizer for the frame memories such that the sub-area previously allocated for the frame memory, on which the decoded data being presented is stored, is included in the sub-areas newly allocated.

Abstract: A method and apparatus are disclosed for capturing and storing digital high definition television signals. The signals are taken from an input device in 8-bit parallel fashion at a constant flow rate and put into each of four 8-bit first in-first out memory registers until they are half full. After the respective first in-first out memory registers are half filled, additional quantities of data equal to half filling the registers are added while the data from the first half register filling is presented to the system memory as 32 bit words. That data is filled into a first of two concurrent blocks of system memory and after the first block is filled, while the second block is filled, the data is written from the first of the two concurrent blocks into another part of the system memory. The transfer of the 32-bit data words is accomplished at a faster rate than the input rate of the 8-bit data.

Abstract: Embodiments of the present invention relate to an apparatus (i.e. a Personal Video Recorder) comprising a memory (i.e. firmware), a storage device (i.e. a hard drive), and a network interface (i.e. a Local Area Network interface). The memory is configured to substantially exclusively store the operating system of the apparatus. The storage device is configured to substantially exclusively store video content (i.e. television programs). The network interface is coupled to the memory and the storage device.

Abstract: During image processing of video pictures, it is generally necessary to have fast, repeated access to adjacent picture blocks. Picture memories with a sufficient capacity to store complete video pictures do not have the necessary access time to perform image processing in real time. The invention therefore provides for the writing of picture blocks from a picture memory to a fast access memory. Only the pixels in the access memory are accessed when the image processing operation is performed. During the read-out, a further block from the picture memory is simultaneously read into the access memory. As a result, fast access to the picture data is possible in conjunction with little additional outlay in respect to memory. Areas of application for the method are in the image processing of video pictures.

Abstract: Fixed pattern noise of an analog memory is reduced. Transfer paths of an address selection signal (SL) between an address generation unit (10) and respective storage elements (21) for storing an analog signal are constructed to have a substantially uniform electric characteristic in driving the storage elements (21) by the address selection signal (SL) to such an extent that the output signal of the analog memory is free from fixed pattern noise. A buffer unit (50) for temporarily storing and outputting the address selection signal is provided between the address generation unit (10) and the respective storage elements (21), and the buffer unit (50) is constructed to have an output characteristic substantially uniform between the storage elements (21). Also, lines between the buffer unit (50) and the storage elements (21) are constructed to have substantially the same electric characteristic.

Abstract: In a method of controlling a memory (5) to allow for a display of at least two images, write and read speeds of writing image data into and reading image data from the memory (5) are measured (9-15) to predict a crossing where a write action overtakes a read action or reversely, where a new field of said image data is written (13, 3) into the memory (5) from a same initial position as from which a previous field of the image data was written into the memory (5) if no crossing is predicted, and the new field of said image data is written (13, 3) into the memory (5) from an end position in the memory (5) at which an end of the previous field of the image data was written into the memory (5) if a crossing is indeed predicted, the memory (5) having a size being larger than that needed for one field but less than that needed for two fields of the image data at its largest read-out size.

Abstract: A receiver arranged to receive and store broadcast data transported by elementary stream of a multiplexed and modulated digital television signal in a rewritable memory during a low power consumption mode for later recall by a user of the receiver. For recall, the receiver is fully energized, and the receiver is further arranged to transfer the broadcast data stored in the rewritable memory to a receiver storage device for further processing of the data under control of the user.

Abstract: The present invention relates to an image data reconstructing apparatus for reconstructing an original image by dividing image data into a plurality of blocks each comprising N×N picture elements, performing two-dimensional orthogonal transform on each of the blocks, quantizing and encoding the result of the two-dimensional orthogonal transform, decoding the encoded result, dequantizing and two-dimensional inverse orthogonal transforming the above result, wherein an operation associated with the multiplication is skipped if a multiplication by zero is detected when two-dimensional inverse orthogonal transform is performed. Before performing dequantization, two block volume of buffer is provided before or after performing two-dimensional inverse orthogonal transform for executing a pipeline process.

Abstract: Memory requirements in a video processor and display system are reduced by storing in memory processed video signals for a plurality of regions of a picture, processing video signals for additional regions of a picture while stored video signals are retrieved in controlling a display, and then storing the newly processed video signals in the memory space occupied by the retrieved video signals. An entire reconstructed frame of image signals is not needed in order to begin the display of the same frame, certain regions of the frame can be displayed while other regions are still being reconstructed. Overwrite protection is provided for stored image signals until the stored image signals are retrieved for image display.

Abstract: Disclosed is a display system displaying a picture on a screen by a video signal from a computer and serving as an input device of a computer coupled to the display system. The display system includes an input part through which a user inputs data, a signal processing part converting a signal inputted from the input part into a signal to be identified by the computer, a data interface between the computer and the display system, and a controlling part transmitting the signal inputted from the input part to the computer via the signal processing part and the data interface.

Abstract: A video decoding system is disclosed with a increased efficiency by allowing a parallel processing when high speed is required and/or a serial processing when high speed is not required, and by effectively managing memory requests from different system blocks. The video decoding system according to the present invention includes a variable length decoder, an inverse quantizer, an inverse scanner, an inverse discrete cosine transform unit, a motion compensation unit, a half pel prediction unit, and a memory controller, allowing control of the processing time depending upon a video bit stream compression method.

Abstract: An information processing apparatus includes an address generation circuit for generating an address signal. A memory operates for storing an information signal containing a video signal in response to the address signal. The address signal is periodically updated. A compression processing circuit operates for reading out the information signal from the memory, and subjecting the readout information signal to a compressively encoding process. A head of every frame represented by the information signal is detected. A state of the address signal is stored which corresponds to the detected frame head. Detection is made as to whether or not the information signal becomes discontinuous. The updating of the address signal and also the operation of the compression processing circuit are suspended when it is detected that the information signal becomes discontinuous. Detection is made as to whether or not the information signal returns to a normally continuous state after the information signal becomes discontinuous.

Abstract: A television receiver which is coupled to a digital VCR to receive an ATSC-encoded multi-program stream containing video, audio and data programs. The receiver recognizes one of the data programs as containing computer software for the digital television receiver, extracts the data program from the multi-program stream into a memory area which is separate from the memory areas used to decode the audio and video programs and then uses data in the extracted data program to update information which controls the operation of the television receiver. The television receiver includes a microprocessor which is coupled to a video processor via an IC bus. The video processor includes registers which are coupled to the IC bus. The microprocessor updates these values from the information in the extracted data program. The extracted data program may include a program image for the operational software for the microprocessor and may replace the operational software to update the operation of the television receiver.

Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.

Abstract: New and improved methods and apparatus for code packing in a digital video system. Among others, a method of transferring a data block to a storage device is disclosed. The storage device can include a plurality of compartments. The method includes receiving a plurality of length values. Each length value can correspond to a data block from a plurality of data blocks. The method further includes filling a first compartment of the storage device with a portion of data from a first data block, searching the length values to identify one of the plurality of data blocks having a length value less than a threshold value, and filling a second compartment with a remaining portion of the data from the first data block. In one embodiment, the second compartment can correspond to the identified data block.

Abstract: The apparatus comprises a processor (15) which has specialized high-speed link terminals intended for the network communication with another processor linked to a rewritable application program memory (26) and includes means for updating this memory. The apparatus includes a connector (30) linked to said high-speed terminals and enabling the communication to the exterior.

Abstract: A method and apparatus for providing audio in a digital video system. Equations for a value n are provided for replacement into the conventional audio data shuffling equations. The equations for the value n provide for simple, efficient techniques to, in turn, calculate values for track number (TK), block number (BK), and data position number (DP). The values TK, BK, DP can be used in an address generation scheme to generate a page value and an offset value. The page value and the offset value for a particular sample of digital audio data, in part, determine the location of the sample in a memory storing the digital audio data. The present invention can be implemented for both four channel and two channel modes under both the NTSC and the PAL standards in accordance with specifications set forth in the Digital Video Standard (the “Blue Book”).

Abstract: Methods and systems for enhancing the storage and display of video data and other digital content in a set-top box or other television environment so that such data is securely stored and displayed are provided. Example embodiments provide an enhanced display controller (EDC) that executes in an electronic device, such as a set-top box, to provide secure storage and playback of streamed digital content. The EDC creates or identifies a secure storage location and stores the data stream in that secure location in a secure manner, thereby minimizing unauthorized access. In addition, the EDC supports the secure display of the data stream using standard (or proprietary) encryption techniques, and/or obfuscation techniques. The EDC also optionally supports various requirements for complying with the usage limitations typically associated with DRM data content. In one embodiment, the enhanced display controller is a modified set-top display (device) driver that includes a VBI decoder, mechanisms (e.g.

Abstract: An embodiment of the present invention provides a system and method for adaptive resource access priority allocation. A method for adaptive resource access priority allocation includes determining whether a resource constrained mode is to be initiated, and responsive to a determination that the resource constrained mode is to be initiated, initiating the resource constrained mode, including modifying a resource access priority. For example, adaptive resource access priority allocation may include increasing the priority for graphical data transfer during intervals of high demand for memory and/or bus bandwidth resources.

Abstract: A double-rate signal achieved by subjecting a video signal to double-rate conversion is supplied to a scan line number converter. In the converter, the portion of the effective scan lines of the double-rate signal is written into a frame memory on the basis of a signal achieved by multiplying horizontal and vertical synchronous signals based on the double-rate signal. In the effective scan line section of HDTV signal, the video signal written in the frame memory is read out on the basis of horizontal and vertical reference signals based on the HDTV signal. Out of the effective scan line section of the HDTV signal, a pedestal level signal written in a memory is read out on the basis of the horizontal and vertical reference signals based on the HDTV signal, thereby achieving HDTV signal whose vertical scan line number is equal to 1125 lines.

Abstract: The present invention relates to method and apparatus of recording digital data stream on a recording medium such as a high-density digital versatile disk. The present recording method searches received digital data stream containing video signals for each picture section, packetizes a data section including at least one picture section found in the searching process into a PES (Packetized Elementary Stream) packet, slices the PES packet to make the sliced data pieces to a plurality of transport packets, and writes the plurality of transport packets within a stream object unit if the stream object unit has a space enough to store the plurality of transport packets, or from head point of a next stream object unit if not. Therefore, the head of each stream object unit is aligned with start of an arbitrary picture, thereby improving random accessibility of A/V data stream recorded on a recording medium.

Abstract: The invention concerns a method of increasing the storage capacity of service information data (SI) in a receiver for digital TV transmissions, such as e.g. in accordance with the MPEG 2 and the DVB standard. The increase takes place to enable keeping a larger quantity of service information data ready for recall, which is used to create the display of an interactive electronic program guide that is shown as an “On Screen Display” (OSD) on the screen. Such a program guide is designed to make the transmission choice easier and to automate the adjustment of the receiver for the desired transmission. The object of the invention is to provide a solution which makes it possible to expand the storage capacity, especially the mentioned cache area, without additional hardware. To achieve the object the unoccupied area of the image memory (MPEG-RAM) is used as a cache area by the video decoder (V-DEC) while graphic displays are shown on the full screen surface as a “Full Screen OSD”.

Abstract: A method and apparatus for delaying the display of a portion of audio and video broadcast signals received from a remote location. Received broadcast video and audio signals are placed in a first-in/first-out storage queue to enable the control of the playback of the signals. Signals may be placed in the tail of the queue while previously received signals are simultaneously routed from the head of the queue to a television monitor. Passing the signals through the queue creates the delay. The system may be controlled either by input to the receiver from the broadcast facility or by remote or manual control by the user. The control functions that are available to the user are pause, play, fast forward and replay. The control from the broadcast facility is through the ability to “mark” segments of the video and audio program to be immune to the fast forward function, thus guaranteeing that those segments are viewed by the user.

Abstract: Under some circumstances, it is necessary to contiguously displaying pictures stored in one display buffer. In order to solve the problem mentioned above, the present invention discloses a method for reordering a decode order into a display order of images by inserting virtual pictures to minimize hardware and software cost.

Abstract: A method and apparatus for de-interlacing a buffer of image data, wherein scan lines from an image sensor have been transferred to the buffer and stored in a group of even scan lines and a group of odd scan lines. The method for de-interlacing the buffer includes providing a first table to indicate current storage locations of each scan line in the buffer and providing a second table to indicate which scan line is currently stored in each storage location. The first table and a temporary line buffer are then used iteratively swap pairs of scan lines that are stored out of numerical order in the buffer, such that after a swap, one of the scan line in the pair is stored in numerical order in the buffer. After each swap, the first table is updated using the second table, and then second table is updated, such that the first and second tables reflect a change of storage locations for the scan lines, whereby the buffer is de-interlaced in place without using a duplicate buffer.

Abstract: A video pre-processing/post-processing apparatus which stably operates at high speed with a minimum memory using a new hardware-software cooperation method, and a method used by the apparatus. The video pre-processing method for capturing video includes assigning numbers to a plurality of memory regions in order and circularly increasing the numbers in response to a frame synchronizing signal, checking the storing memory regions in response to the frame synchronizing signal and capturing input video data, and storing the captured video data in the memory regions in a predetermined order.

Abstract: In a video signal capturing apparatus with a simple construction capable of distinguishing fields in units of a color field, a separation circuit separates from input video signals, vertical synchronizing signals that lead fields in a one-to-one relationship. A field counter formed by, for example, a scale-of-four counter, counts the number of vertical synchronizing signals. Based on the count value of the field counter and values set in a register, a timing generating circuit performs data capture in such a manner that color fields are distinguished from each other. If color field 3 is to be captured, a value “3” is set the register. The timing generation circuit compares a count value from the field counter with the set value “13”. When the count value equals 3, the timing generation circuit starts capture of digital video data in the determined field. An even-odd number determining circuit may be provided for distinguishing (i.e.

Abstract: An analog FIFO memory device allowing for the suppression of the adverse effects produced by fixed pattern noise, generated inside an analog FIFO memory, on signal components. First and second analog multipliers are respectively provided on the input and output sides of the analog FIFO memory. In synchronism with the inputs/outputs of signals to/from the analog FIFO memory, a non-inverting operation and an inverting operation are alternately and repeatedly performed on the input signals and the output signals. Then, although the signal input/output characteristics of the analog FIFO memory are not changed, the fixed pattern noise generated inside the analog FIFO memory is modulated by the second analog multiplier. As a result, the spectrum of the fixed pattern noise, which originally has a lower frequency, is shifted to have a higher frequency.

Abstract: When an OSD data storage area for storing OSD data needs to be reserved, an area of a frame storage apparatus that should store macroblocks corresponding to an invisible area on a screen is allocated as the OSD data storage area. There is no degradation in picture quality. When doing so, the data reduction control unit 64 receives an instruction to reserve the OSD data storage area and discards the corresponding macroblocks. The OSD data access unit 63 writes the OSD data into an area of the frame storage apparatus that was assigned to store the discarded macroblocks.

Abstract: A video compression technique is provided which reduces motion estimation computations. A digital signal processing system employs external memory. Detection speed is improved by loading a succession of refined search windows are loaded on-chip. By so doing, the search involves fewer accesses to external memory and so completes in a shorter amount of time.

Abstract: A video apparatus has a digital decoder having a first memory on an internal bus and linked to an OSD circuit and to a second memory via a main bus.

Abstract: Method for controlling a memory in a digital system, including the steps of (a) dividing the memory into a plurality of fixed sized memory blocks, (b) defining at least one of the memory blocks as a compression/decompression region, (c) assigning compression priorities to rest of the memory blocks except the memory blocks defined as the compression/decompression region, and (d) making the memory blocks to deal with an external data received according to an external command, and carrying out compression/decompression of data required in the dealing with the external data at the compression/decompression region according to the compression priorities.

Abstract: Method for controlling a memory in a digital system, including the steps of (a) dividing the memory into a plurality of fixed sized memory blocks, (b) defining at least one of the memory blocks as a compression/decompression region, (c) assigning compression priorities to rest of the memory blocks except the memory blocks defined as the compression/decompression region, and (d) making the memory blocks to deal with an external data received according to an external command, and carrying out compression/decompression of data required in the dealing with the external data at the compression/decompression region according to the compression priorities.

Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: A system for transferring video data includes a difference detector for detecting the difference between a current field information and the preceding field information. The preceding information is obtained from an entered interlaced video signal. An interpolator generates current display frame information in response to an interpolation based upon the current filed information with regard to an area of the video signal in which there is a difference value between successive fields that exceeds a predetermined threshold value. The interframe difference between the current display frame information and preceding display frame information is detected by the difference detector. Only the interframe difference is transferred over a system bus to enable a frame display to be presented on non-interlacing display device.

Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: Methods and apparatus for storing data using two-dimensional arrays mapped to memory locations.

Abstract: Circuitry for identifying digital data packets, each comprising a useful signal and a header signal containing data pertaining to the contents of the useful signal is provided. The circuitry includes a means (30) for extracting data from each header signal, which data is representative of a corresponding useful signal, a means for storing reference data in a memory, at addresses each corresponding to a packet type, and a means for comparing the data extracted from each header signal with said reference data stored in memory, and for the delivery, to a data processing unit (32,34), of an address signal indicating the nature of the corresponding packet. The data storage means and the comparison means preferably employ an associative memory (38) adapted to ensure the simultaneous comparison of the data extracted from each header signal with the reference data stored in memory.

Abstract: A data storage system is described that simultaneously stores incoming data in a plurality of different digital formats linked together to permit economical accessibility and browsing of stored content by providing user access to reduced-resolution versions of stored format. Synchronization information correlates the same content stored in different digital formats to provide a means to reflect an edit of content in one format to the content stored in the other formats without manual editing of content in each format.

Abstract: Image information is stored into a memory device (FMORG) which is controlled in such a manner that only image information from a movement phase different from the movement phase of the image information already stored in the memory device (FMORG), is stored into the memory device (FMORG), whereby the memory device (FMORG) provides image information from a movement phase which differs from a movement phase of the image information by a fixed number of movement phases, even when the image information contains repeated movement phases.