Abstract: Provides methods and apparatus to reduce effects on playback of moving picture data caused by variations in data transmission rate that occur on a communication line, a receiving and playing back apparatus includes a receiver for receiving moving picture data transmitted over a communication line; playback modules for playing back the received moving picture data; buffer B for temporarily storing the moving picture data received by the receiver and outputting the stored moving picture data at a desired speed; and buffer A for providing the playback modules with moving picture data required for playback processing.

Abstract: A system for transferring video data includes a difference detector for detecting difference information between current field information and preceding field information obtained from an entered interlaced video signal, and an interpolator for generating current display frame information by interpolation based upon the current field information with regard to an area in which a difference value between the fields exceeds a predetermined threshold value. The interframe difference between the current display frame information and preceding display frame information is detected by the difference detector, and only the interframe difference is transferred to a system bus so that a frame display is presented on non-interlacing display means.

Abstract: A play to air controller station system in a distributed object television broadcast studio. In one embodiment, a play to air control workstation is used to control a variety of resources in a broadcast studio system interconnected by a communications network. The resources of the broadcast studio system include a transmitter unit, various media source devices such as tape decks and file servers, a network routers unit, and various decoders and encoders. The broadcast studio system is managed as a network distributed object system where an all physical devices are attached to the network either by containing appropriate software within themselves, or by attaching themselves to a computer proxy that is on the network and is able to control their functionality. The control system includes one or more device objects configured to store, route and transmit selected video segments to be aired from the television broadcast studio.

Abstract: For a possible flexible adaptation to changing ambient conditions, a circuit arrangement comprising an integrated circuit in which a microprocessor is provided which controls an index generator provided in the integrated circuit for teletext and/or on-screen display functions and which performs control functions of a television apparatus by means of a control interface provided in the integrated circuit is characterized in that a storage interface for a read-only memory outside the integrated circuit is provided in the integrated circuit, and in that the read-only memory comprises at least a part of the program code for the microprocessor and at least a font for the teletext function and possible further index functions.

Abstract: A frame memory is provided which has five fields each having N slots, and three additional slots. Each slot has a storage capacity to store eight image lines. Four fields of the five fields serve to store motion compensation reference frames. The remaining one field and the three additional slots are used for B-picture interlace conversion. Disposed in a control unit are a slot control memory, a write slot pointer, and a read slot pointer. For an image output unit to acquire information from the frame memory in a correct slot order, the contents of the slot control memory are updated at the time of performing write operation to enter information into the frame memory by a bit stream analysis unit.

Abstract: A liquid crystal display control apparatus includes a display on/off data generation circuit for generating plural display on/off data per pixel corresponding to M (M>N, M and N being integers) frame periods of a video output signal in N frame periods of a video input signal on a unit pixel basis in response to gray-scale data of pixel units included in the video input signal, a write control circuit for writing display on/off data per pixel corresponding to M frames of the video output signal generated by the display on/off data generation circuit into a frame memory during N frame periods of the video input signal, and a read control circuit for sequentially reading out, from the frame memory, display on/off data corresponding to M frames of the video output signal written in the frame memory in synchronism with one display scan period of the video output signal, thereby the data written in the frame memory is not gray-scale data but display on/off data of one bit, therefore, a data bus width at a time o

Abstract: A television based on an operating system, including: a first memory storing a boot loader program, the boot loader program performing a hardware basic test and a booting; a television signal generating portion outputting a television broadcast; a second memory storing a MPEG control program and preset channel information, the MPEG control program driving the television signal processing portion to output a video signal corresponding to a received television broadcast corresponding to the stored preset channel information; and a central processing unit executing the boot loader program, executing the MPEG control program after the hardware basic test of the boot loader program and loading the operating system onto a random access memory after the MPEG control program drives the television signal processing portion to output the video signal corresponding to the received television broadcast corresponding to the stored preset channel information.

Abstract: Device and method for transposing a matrix of video signals, is disclosed, the device including a memory part, a write control circuit for shifting and writing rows of the matrix of video signals on the memory part by any one unit either of a row unit or column unit, and a read control circuit for shifting and reading the matrix of video signals stored in the memory part by one unit different from the unit in the writing either of the row unit or the column unit,with rows of a matrix of video signal received at the next time written on a portion of the memory part emptied due to the shift in the reading.

Abstract: A memory allocation method and apparatus is disclosed in which the macro blocks are grouped into a plurality block sets and stored in the memory as block set. By grouping and storing the macro blocks, an efficient reading of the data is achieved.

Abstract: A scan format converter for converting a video format by bi-sigmoid interpolation. In the scan format converter, a memory controller has a look-up table at which first and second displacement values for pixel points of a video format to be converted are stored, controls transmission of color signals input from an external device, and reads the first and second displacement values for the pixel points of the color signals from the look-up table. A mode detector detects horizontal and vertical sync signals input from the external device and outputs a video format detection signal representing a mode of the currently input video format to the memory controller. A memory temporarily stores the color signals.

Abstract: A digital TV display device and method is disclosed including a display control unit providing selection signals, a look-up table unit having at least two look-up tables wherein at least one of the look-up tables is operative in a read mode and the other is operative in a write mode in response to the selection signals, and a look-up table selection unit forwarding a data read from the at least one look-up table operative in the read mode in response to the selection signals for displaying.

Abstract: A device for transferring serial data includes a first temporary memory for temporarily storing the serial data supplied from an input terminal; a first-memory for storing the data supplied from the first temporary memory; a second temporary memory for temporarily storing the serial data supplied from the input terminal; a second memory for storing the data supplied from the second temporary memory; a first transfer state detecting circuit for generating a first control signal indicative of that the serial data supplied from the input terminal is being transferred, a second transfer state detecting circuit for generating a second control signal indicative of that the serial data supplied from the input terminal is being transferred; a control circuit for deciding that the first and the second control signal have not arrived in response to the arrival of a transfer command signal, thereby transferring the data from the first temporary memory to the first memory and transferring the data from the second tempora

Abstract: There is provided a display apparatus capable of assuredly conveying communicative information to viewers, the display apparatus comprising the following: display means for displaying video picture; switching means for turning power-source ON and OFF; and controlling means for controlling the display means to display communicative information thereon in place of the video picture during a period after the switching means executes an operation to turn off the power source until the power source is actually turned off.

Abstract: An image processing device comprises an SIMD (Single Instruction stream Multiple Data stream) calculating unit (101) for performing operations, such as motion compensation, motion prediction, DCT (Discrete Cosine Transform) processing, IDCT (Inverse Discrete Cosine Transform) processing, quantization, and reverse quantization by means of a pipeline operation unit that can be program-controlled by an outside unit, a VLC (Variable Length Code) processing unit (102) for performing variable-length encoding processing and variable-length decoding processing according to a given encoding method, an external data interface (103) for performing a data transfer between the image processing device and an outside unit, and a processor (105) for decoding an instruction held by an instruction memory (104), and for performing a programmed control operation on the SIMD calculating unit (101), the VLC processing unit (102), and the external data interface (103).

Abstract: A video memory system for storing ATSC video image data is configured as three channels, each channel having two banks and each bank including a plurality of memory rows. The exemplary memory system includes a buffer area for holding bit-stream data and six field buffer areas. The field buffer areas are arranged in pairs to form a three frame buffer areas, such that the buffer areas for the two fields in a given frame are allocated in respectively different banks. The video memory system includes an output memory controller which receives macroblocks of decoded image data and divides the received macroblocks into respective upper and lower half-macroblocks, the upper half-macroblock being stored in one field buffer of the frame and the lower half-macroblock being stored in the other field buffer of the frame.

Abstract: This invention discloses a method for accessing Dynamic Random Access Memory (DRAM) to store and retrieve data words associated with a two dimensional image. The DRAM includes two separate banks, a first bank and a second bank. Each bank is capable of operating in page mode to read and write the data words. The two dimensional image is organized in a two dimensional grid pattern of cells, each cell containing an M by N matrix of pixels. The words associated with each cell occupy one page or less of a bank. Each cell is assigned a particular one of the two banks so that all data words associated with that particular cell are read from and written to one particular page of that particular bank. The assignment of banks to cells is done such that each cell is associated with a different bank than any bordering cell which is also either in the same row or in the same column.

Abstract: An image processing apparatus in which a time base corrector and an image coding apparatus are integrated so as to use a common memory, thereby realizing a simple circuit arrangement. The apparatus performs control of writing each line of input image data to an image memory in turn while reading image data from the image memory in predetermined coding units, in the following manner: when a picture of the image data has been written, if the number of data units, each corresponding to the coding unit, is equal to or below a first threshold, then a picture is skipped in the image data writing operation, and when a picture of the image data has been read, if the number of written lines is equal to or below a second threshold, then the same picture is again read in the image data reading operation.

Abstract: A system for interpolating half-pels from a pixel array stores pixel data for each pixel in one of a plurality of different memory areas based on a location of the pixel within the pixel array, and determines a specific address in each one of the plurality of memory areas based on a target pixel in the pixel array. The system determines each specific address based on a location of the target pixel in the pixel array. The system also reads, from each the plurality of memory areas, pixel data from determined specific addresses and determines a value of at least one half-pel for the target pixel based on the read pixel data.

Abstract: An arrangement which utilizes the system memory to store the wave tables used in the generation of high quality sound, and a direct memory access controller to rapidly transfer the portions of the wave tables stored in memory using the system bus so that a sound card may manipulate high quality sounds from wave tables stored directly in system memory without overloading the system bus and without the need for substantial additional memory on the sound card.

Abstract: A video decoder for decoding data at a high rate uses a plurality of slower slice decoders. A common memory is shared by all slice decoders drastically reducing storage requirements of individual decoders. Slices are allocated to decoders optimally in response to busy signals providing improved performance over known methods. The invention decodes HDTV signals using a plurality of ordinary television resolution decoders. Multiple data streams are also decoded.

Abstract: Frame-rate control electronic provides gray-scale display control algorithm for STN LCD devices and constant brightness display with randomized pattern algorithm. Even distribution control of phase number reduces screen flicker and stabilizes gray-scale display. Randomized and scrambled phase number control eliminates screen beating artifacts, such as when image includes dither and checker patterns. Programmable parameters, such as tuning value, phase number matrices, and frame offset numbers, may be chosen flexibly to optimize conditions to certain display.

Abstract: A system and method of controlling a memory of an HDTV video decoder is disclosed which has a video bit stream write buffer, a bit stream read buffer, a motion compensate buffer, a store buffer and a display buffer and outputs request signals to read/write a data from/into an external memory every time it is needed in order to decode an input video bit stream. The method includes the steps of prioritizing the request signals output and sending an authorization signal in response to each of the request signals.

Abstract: The memory (MM) is addressed, depending on the format, with address words (MDC) formed at least from the high-order bits of the identifier (ID) of each cue, and possibly padded out with check or selection words (MS) making it possible either to designate consecutive addresses or to select some of the latter from each memory cell (CM) depending on the low-order bits of the identifier. This allows continuous addressing of the memory irrespective of the format used, thereby optimizing the memory size and avoiding a structural or software modification of the addressing system with each change of format.

Abstract: Television receiver furnished with a memory (21, 22, 23) for receiving service data comprising a processing module (11) which correlates usage criteria received together with the service data and storage criteria characterizing the memory or memories of the receiver. By correlating the two criteria, the module determines the conditions of storage.

Abstract: A receiver arranged to receive and store broadcast data transported by elementary stream of a multiplexed and modulated digital television signal in a rewritable memory during a low power consumption mode for later recall by a user of the receiver. For recall, the receiver is fully energized, and the receiver is further arranged to transfer the broadcast data stored in the rewritable memory to a receiver storage device for further processing of the data under control of the user.

Abstract: One frame of an image having 1312 pixels in the horizontal direction thereof is divided into 192 pixels at a time in the horizontal direction to obtain a plurality of image areas. The one frame of image data is subjected to synchronization processing repeatedly using a line memory that is capable of storing 192 pixels of data.

Abstract: A predictor provides as a pixel block of a current image a set of p target pixels of the preceding image so that each target pixel corresponds in the image to the adjacent pixels of the current pixel shifted by a predetermined motion vector. The predictor includes a search memory, each cell of which is independently addressable in read/write mode; three write decoders for simultaneously addressing in write mode three cells of three portions of the memory; p read decoders for simultaneously addressing in read mode p cells of p distinct sub-portions of the memory; and for controlling the write decoders so that p successive writings of data of the same nature corresponding to p adjacent points in the image are achieved in each of the p sub-portions.

Abstract: A ping-pong A/D converter which produces an output at alternate times on alternate memories.

Abstract: A conversion unit having a bidirectional conversion function of converting analog video signals into digital image data and vice versa and a processing unit having a function of encoding image data and of decoding encoded data are provided. A data transmission control unit switches the flow direction of each of image data and encoded data in response to an encoder/decoder switch signal. A process control unit performs switching of the receiving/transmitting of a control signal such as a transmission clock signal relating to encoded data in response to a master/slave set signal.

Abstract: The invention relates to an architecture making it possible to store and transfer still or moving video images, the said architecture comprising at least one input circuit (E1, E2, . . . , En) allowing access for data intended to make up video images, a memory area (M) making it possible to store video images, at least one video image output circuit (S1, S2, . . . , Sj) and a video bus (B) intended to provide for the transfer of information between the memory area (M), the input circuit and the output circuit, characterized in that the memory area (M) is a general-purpose memory and in that the video bus (B) has a width L greater than or equal to the width of the memory area (M).The general-purpose memory is operated in a centralized manner by a control circuit (CTRL).The invention applies to computer platforms dedicated to the transfer of Broadcast quality images or alternatively to video devices for built-up image animation.

Abstract: An MPEG decoder operates in 2.5 frame store mode, and has an efficient memory management which allows a B picture to be stored and displayed while simultaneously making use of a portion of the frame store memory. The video frame is treated as a grid, having rows of 8.times.8 pixel blocks. The pixel blocks are manipulated in three FIFOs which are cross-connected in a closed loop. Two processes operate on the memory so arranged: (1) a video reconstruction process which writes data into the memory, and (2) a display process, which accesses the memory and writes the video frame into another, external memory in a rastered format. One of the three cross-coupled FIFOs is designated for write-back, and the other two for reading 2:1 interlaced raster data. The two FIFOs utilized for the raster operation are allocated to the alternate lines of the picture.

Abstract: For compatible transmission of a television picture having an aspect ratio of 16:9 within a 4:3 system, transmission is effected in the letterbox format in accordance with the PALplus system specification. The receiver reconstructs the original picture with the aid of vertical filters and is able, furthermore, to suppress crosstalk interference from the luminance signals in the chrominance signals. To further improve the picture quality, the picture is displayed at a frame frequency of 100 Hz. For this purpose, the picture supplied at 50 Hz with line interlacing must be converted to a frame frequency of 100 Hz. Known concepts for PALplus decoding and 100 Hz conversion carry out these processes separately and in doing so require a great deal of memory space.

Abstract: An address generating and mapping device of a video capture system includes: a microprocessor having a counter counted by being synchronized with a horizontal synchronizing signal of a video signal, an address port for outputting an address to be used when reading from a memory, and a counter port for outputting the counter value and a bank selection signal by using predetermined higher bits among the counter output as the bank selection signal for selecting data banks of the memory; a counter for performing a predetermined operation according to a signal for selecting a mode, when a mode for generating an address necessary for storing the video signal is referred to as an address generating mode and a mode for mapping an address necessary for accessing the memory is referred to as an address mapping mode; multiplexers for outputting a counter value from the microprocessor to higher addresses of the memory when the mode selection signal is the address generating mode and outputting the addresses output from t

Abstract: A secure video content processor ("SVCP") which receives encrypted digital video information and converts it into analog information for a monitor while preventing unauthorized access to the intermediate unencrypted digital data. The SVCP uses hardware envelopes to prevent unauthorized access to the decrypted digital stream. When a need arises to transmit digital data outside the hardware envelope, the digital data is encrypted and then decrypted when it re-enters a hardware protected section of circuitry.

Abstract: A method of reducing the memory required for decompression of a compressed frame by storing frames in a compressed format using DCT compression and decoders for implementing such a method are disclosed. The decoder is coupled to a memory where the frame can be stored. The decoder includes a decoder module having a parser, a block decoder module and a motion compensation engine. The decoder module is coupled to a DCT encoder module, which has an output coupled to the memory. The decoder also includes a stored DCT decoder module, which has an input coupled to the memory, a first output coupled to the motion compensation module and a second output that functions as an output of the decoder. In operation, any prediction frames needed for motion compensation decompression of the compressed frame are decompressed in the stored DCT decoder module. The compressed frame is decompressed in the decoder module to obtain a decompressed frame.

Abstract: The horizontal address and the vertical address of a picture image are arrayed at the lower and upper order sides, respectively, and allocated to a lower order side column address and an upper order side column address of the synchronous DRAM employed as a picture memory, respectively. A bank switching address is allocated between the upper most bit of the horizontal address and the lower most bit of the row address to enable data to be read continuously to achieve high-speed accessing and improve the utilization efficiency of the data bus.

Abstract: An apparatus for controlling a display memory for storing decoded picture data is disclosed, that comprises a data dividing portion for dividing decoded picture data as one macroblock in a vertical direction, a write address generator for generating the binary value of a write address necessary for writing the divided picture data to the display memory, a slice counter for counting the number of slice lines of picture data that has been written to the display memory, a rotate-shifter for rotating and shifting the binary value of the generated write address to the left by a first bit number corresponding to the number of slice lines counted, a means for writing the divided picture data to the display memory corresponding to the write address that has been rotated and shifted, a read address generator for generating the binary value of a read address necessary to read picture data from the display memory, a rotate-shifter for rotating and shifting the binary value of the generated read address to the left by a

Abstract: A method and apparatus for draining video data from a planarized video buffer in a video camera. The method includes the steps of reading a first sequence of video data from a first plane of the planarized image buffer starting at a buffer address indicated by a first pointer, and then reading a second sequence of video data from a second plane of the planarized image buffer starting at a buffer address indicated by a second read pointer. The apparatus includes an address generation unit and a sequence counter. The address generation unit includes a number of read pointers each configured to indicate a memory location within a different data plane of a video buffer. The address unit is configured to address a sequence of memory locations in a video buffer starting at a location indicated by an active one of the read pointers.

Abstract: A device for reversing an image of an object includes selector for selecting a reverse mode and control signal generator for generating a plurality of control signals. The control signal generator outputs a down-counting signal when the reverse mode is selected. A memory stores image data when the memory receives a store-enable control signal from the control signal generator and outputs the stored image data when the memory receives an output-enable control signal from the control signal generator. The device also includes an address generator for generating an address at which the image data is stored in the memory according to a control signal received from the control signal generator. During the reverse mode, the address generator generates an address to sequentially access the memory, beginning with a last address of the memory according to the down-counting signal.

Abstract: A coding data is performed in decoding by a stream decoding circuit, an IDCT circuit and an MC circuit. An AGU stores decoding data from the MC circuit to a memory. Regarding the decoding data of a B picture, the AGU writes only the decoding data which are necessary for image display, to a B picture region. Thus, a room occurs in a memory capacity. It is possible to hold the decoding data of the B picture through 2 field periods of time. It is possible to read twice the same decoding data, for display processing. Thus, frame interpolation processing is made possible, and it is possible to obtain a magnified image having high image quality.

Abstract: An electronic endoscope in which images of an object to be viewed are picked-up in a field-sequential system by a solid-state image pickup device. The electronic endoscope includes a primary converter for converting different color image signals picked-up by the solid-state image pickup device and successively output therefrom, into digital image signals. A single memory temporarily stores the digital image signals in a point-sequential system. A secondary converter converts the digital image signals successively read from the single memory, into analog image signals. A delay delays a part or all of the analog image signals by different delay times to synchronize the color image signals.

Abstract: An information processing method used for compressing or decoding picture data wherein, in securing an area in which to store restored picture data, pre-set processing can be performed speedily without producing caching errors. Storage sites on a data memory are allocated to luminance signals and to associated chroma signals so that the luminance signals and the associated chroma signals will be copied in different locations in a data cache. The luminance signals and the associated chroma signals so allocated are stored in the data memory. For decoding, plural picture data related with one another are allocated to different locations in the data memory so that the picture data will be copied indifferent addresses in the data memory.

Abstract: A motion picture decoder uses a synchronous dynamic random access memory (SDRAM) as a frame memory in which the SDRAM is used, to store one frame of a video signal. By using an SDRAM which can operate at high speed, one frame of motion picture data is appropriately recorded in the SDRAM to enable rapid processing and complicated predictions of the motion compensation using the frame memory.

Abstract: Method and device for enabling high-speed write/read operation of image information in units of blocks, so as to fully meet the demand on high-speed operation of MPEG, etc. Eight memory arrays MA1-MA8 are parallelly-connected in image memory unit 10; hence, in each memory array MAi, image can be written/read individually under control of write address generating circuit 12, memory array control logic 14, and read address generating circuit 16. The input/output terminals of memory arrays MA1-MA8 are connected to half-pel operation circuit 24 through eight data registers DREG1-DREG8 of input/output buffer 18, eight row selectors YSEL1-YSEL8 and column selector XSEL of selector circuit 20, and data bus 22.

Abstract: Signal processing apparatus comprises a control read only memory storing:(i) two or more sets of signal processing parameter data to control signal processing operations of the apparatus; and(ii) configuration data specifying one of the sets of signal processing parameter data stored in the control read only memory;a control read/write memory capable of storing:(i) at least one set of signal processing parameter data; and(ii) configuration data capable of specifying a set of signal processing parameter data stored in the control read only memory or a set of signal processing parameter data stored in the control read/write memory;and control logic, responsive to an input selection signal specifying whether the configuration data in the control read only memory or the configuration data in the read/write memory should be selected for use, for controlling the signal processing apparatus to perform signal processing operations in accordance with the signal processing parameter data specified by the selected confi

Abstract: A method for creating a video connection between a video source for transmitting frames of video data and a video sink for receiving the frames. The video source may be a file, a camera, a computer network, and a telephony interface. The video sink may be a file, a visual display device, a computer network, and a telephony interface. The video source has a recycle framehandler function for recycling used buffers and the video sink has a process framehandler function for processing received frames. A video stream object is created having data members that include a reference to the video sink and a reference to the video source, as well as several member functions. The member functions are used to query the video sink to obtain a reference to the process framehandler function and to then provide the reference to the video source. The member functions are also used to query the video source to obtain a reference to the recycle framehandler function, which is then provided to the video sink.

Abstract: A video decoder system for reconstructing, storing and retrieving bidirectionally predictive-coded (B) frames for display including pull-down conversion includes a reconstruction unit for reconstructing the frames, where the reconstruction unit reconstructs the top-upper field of every other frame twice. The frame is conceptually divided into four sections, including top-upper, top-lower, bottom-upper and bottom-lower sections. A memory having only three segments for storing pixel data is provided, where each segment is sized to store any one of the frame sections. A segmentor receives and separates the pixel data according to the top and bottom fields for each section of each frame, and stores pixel data from the top field into one segment pixel data from the bottom field into another segment. The segrnentor initially selects any two segments for the upper half of the first frame, and then selects a segment being retrieved for display and the third segment for the bottom half of the first frame.

Abstract: An audio and video recording and reproduction apparatus and method is described, which uses a movable storage memory such as a memory card, so that audio and video signals are easily accessed without separate editing devices. The apparatus uses a separable memory so that a deck is unnecessary, allowing small, lightweight constructions, and a compression algorithm results in longer playing time, while read/write operations robust to noise are achieved. Also, data desired by the user is easily accessible, and applications as a substitute for magnetic or disk media are also possible.

Abstract: An image processing apparatus, for an image recording and reproducing system, comprises a means for writing a given field image signal in a field memory, and a means for reading out the field image signal written in the field memory. The reading means reads out individual lines in sequence in a first field of the field image signal and also reads out a plurality of lines in a second field of the field image signal concurrently.

Abstract: A broadcast recording and playback device employing a "circular buffer" which constantly records one or more incoming audio or video program signals and a microprocessor for accessing the memory to read a playback signal from the circular buffer to display programming material delayed from its receipt by a selectable delay interval. The circular buffer is implemented by a digital memory. Subsystem comprising the combination of a semiconductor RAM memory and a disk memory operated under the control of a microprocessor such that incoming signals are constantly recorded as received while, at the same time, delayed signals are being read from the memory subsystem at a different memory location selected by a microprocessor to provide a user-selected time delay.