Highly physical ion resistive spacer to define chemical damage free sub 60nm MRAM devices

A magnetic tunneling junction (MTJ) structure comprises a pinned layer on a bottom electrode. a barrier layer on the pinned layer, wherein a second metal re-deposition layer is on sidewalls of the barrier layer and the pinned layer, a free layer on the barrier layer wherein the free layer has a first width smaller than a second width of the pinned layer, a top electrode on the free layer having a same first width as the free layer wherein a first metal re-deposition layer is on sidewalls of the free layer and top electrode, and dielectric spacers on sidewalls of the free layer and top electrode covering the first metal re-deposition layer wherein the free layer and the top electrode together with the dielectric spacers have a same the second width as the pinned layer wherein the dielectric spacers prevent shorting between the first and second metal re-deposition layers.

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Description
TECHNICAL FIELD

This application relates to the general field of magnetic tunneling junctions (MTJ) and, more particularly, to methods for preventing shorts and sidewall damage in the fabrication of sub 60 nm MTJ structures.

BACKGROUND

Fabrication of magnetoresistive random-access memory (MRAM) devices normally involves a sequence of processing steps during which many layers of metals and dielectrics are deposited and then patterned to form a magnetoresistive stack as well as electrodes for electrical connections. To define the magnetic tunnel junctions (MTJ) in each MRAM device, precise patterning steps including photolithography and reactive ion etching (RIE), ion beam etching (IBE) or their combination are usually involved. During RIE, high energy ions remove materials vertically in those areas not masked by photoresist, separating one MTJ cell from another. However, the high energy ions can also react with the non-removed materials, oxygen, moisture and other chemicals laterally, causing sidewall damage and lowering device performance. To solve this issue, pure physical etching techniques such as pure Ar RIE or ion beam etching (IBE) have been applied to etch the MTJ stack. However, due to the non-volatile nature, pure physically etched conductive materials in the MTJ and bottom electrode can form a continuous path across the tunnel barrier, resulting in shorted devices. A new approach to remove these two kinds of sidewall damage is thus needed for the future sub 60 nm MRAM products.

Several patents teach two-step methods of etching MTJ stacks, including U.S. Pat. No. 9,087,981 (Hsu et al), U.S. Pat. No. 9,406,876 (Pinarasi), and U.S. Pat. No. 9,728,718 (Machkaoutsan et al), but these methods are different from the present disclosure.

SUMMARY

It is an object of the present disclosure to provide a method of forming MTJ structures without chemical damage on the MTJ sidewalls or shorting of MTJ devices.

Another object of the present disclosure is to provide a method of forming MTJ structures having chemical damage free MTJ sidewalls and eliminating conductive metal re-deposition induced shorted devices.

Another object of the present disclosure is to provide a method of forming MTJ structures having chemical damage free MTJ sidewalls and eliminating conductive metal re-deposition induced shorted devices using a spacer assisted pure physical etch.

In accordance with the objectives of the present disclosure, a method for fabricating a magnetic tunneling junction (MTJ) structure is achieved. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer. A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and the free layer not covered by the hard mask are etched, stopping at or within the barrier layer. Thereafter, the hard mask, top electrode layer, and free layer are encapsulated with an encapsulation layer. A spacer layer is deposited over the encapsulation layer and the spacer layer is etched away on horizontal surfaces leaving spacers on sidewalls of the encapsulation layer wherein sidewalls of the free layer are covered by a combination of the encapsulation layer and spacers. Thereafter, the barrier layer and pinned layer are etched to complete formation of the MTJ structure.

Also in accordance with the objectives of the present disclosure, a magnetic tunneling junction (MTJ) structure comprises a pinned layer on a bottom electrode. a barrier layer on the pinned layer, wherein a second metal re-deposition layer is on sidewalls of the barrier layer and the pinned layer, a free layer on the barrier layer wherein the free layer has a first width smaller than a second width of the pinned layer, a top electrode on the free layer having a same first width as the free layer wherein a first metal re-deposition layer is on sidewalls of the free layer and top electrode, and dielectric spacers on sidewalls of the free layer and top electrode covering the first metal re-deposition layer wherein the free layer and the top electrode together with the dielectric spacers have a same second width as the pinned layer wherein the dielectric spacers prevent shorting between the first and second metal re-deposition layers.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings forming a material part of this description, there is shown:

FIGS. 1 through 8 illustrate in cross-sectional representation steps in a preferred embodiment of the present disclosure.

 DETAILED DESCRIPTION

In the present disclosure, a spacer assisted pure physical etch can create chemical damage free MTJ sidewalls and also eliminate conductive metal re-deposition induced shorted devices. More specifically, the free layer is physically etched by pure Ar RIE or IBE, then covered by a spacer. Next, the pinned layer is physically etched using the spacer as a hard mask. The spacer material can be made of carbon or TaC, which is highly resistant to this type of etch, thus ensuring that enough of the spacer remains to protect the free and barrier layers. This method is particularly useful for high density sub 60 nm MRAM devices, where chemical damage and re-deposition on the MTJ sidewall become very severe for these smaller MRAM chips.

In a typical MRAM fabrication process, the whole MTJ stack consisting of free, barrier, and pinned layers is patterned by one single step etch, either by chemical RIE or physical IBE. It therefore creates either chemical damage or physical shorts on the MTJ sidewall. However, in the process of the present disclosure, we firstly etch the free layer by pure Ar RIE or IBE, cover it with a highly physical etch resistant spacer, and then etch the pinned layer by pure Ar RIE or IBE using the spacer as a hard mask. By this method, both issues are solved simultaneously, greatly enhancing the device performance.

The preferred embodiment of the present disclosure will be described in more detail with reference to FIGS. 1-8. FIG. 1 illustrates a bottom electrode layer 12 formed on a semiconductor substrate, not shown. Now, the MTJ stack, comprising at least a pinned layer 14, a tunnel barrier layer 16, and a free layer 18, are deposited on the bottom electrode. A top electrode 20 comprising Ta, TaN, Ti, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni or their alloys is deposited over the MTJ stack to a thickness h1 of 10-100 nm, and preferably ≥50 nm. A dielectric hard mask 22 of SiO2, SiN, SiON, SiC or SiCN is deposited on the top electrode to a thickness of ≥20 nm. Finally a photoresist mask 24 is formed over the hard mask 20 forming pillar patterns with size d1 of approximately 70-80 nm and height h2 of ≥200 nm.

Now, as shown in FIG. 2, the hard mask 22 is etched by a fluorine carbon based plasma such as CF4 or CHF3 alone, or mixed with Ar and N2. O2 can be added to reduce the pillar size further to d2 of about 50-60 nm.

Next the top electrode is etched by RIE or IBE, followed by a pure Ar RIE or IBE etch of the free layer. If RIE is used to etch the top electrode, the top electrode and free layer etching must be in separate steps since RIE causes chemical damages and cannot be applied to the free layer. If IBE is used, the top electrode and free layer can be etched by one single etch step using the same recipe. The free layer etch step can stop at the interface between the free layer 18 and the tunneling barrier 16 or within the tunneling barrier. Because of the nature of a physical etch, there is no chemical damage after this etching step, but only a thin layer of conductive metal re-deposition 26 on the free layer's sidewall, as shown in FIG. 3.

The photoresist 24 is stripped away by oxygen alone or mixed with N2 or H2O. Then, as illustrated in FIG. 4, an encapsulation layer 28, made of Al2O3, SiON, or SiN, is deposited over the partially etched MTJ stack and the bottom electrode by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) to a thickness of 5-30 nm. The deposition may be either in-situ or ex-situ. This non-conductive encapsulation layer will protect the free layer from shorting by encapsulating the conductive metal re-deposition 26.

Now, as shown in FIG. 5, a spacer material layer 30 is deposited over the encapsulation layer 28. The spacer material 30 is carbon, TaC, or Al which has a very low etch rate under physical etching. The spacer material layer 30 is deposited in-situ or ex-situ by CVD, PVD, or ALD to a thickness of 10-30 nm.

Next the portion of the spacer layer 30 that is on horizontal surfaces is etched away by RIE, leaving spacers 32 having a thickness of 5-20 nm only on the sidewalls of the pattern, as shown in FIG. 6. Dependent on the material that is used for the spacer, different plasmas can be used for this step. For example, O2 can be applied for carbon, fluorine carbon such as CF4 or a Halogen such as Cl2 can be used for TaC, and a Halogen such as Cl2 can be used for Al.

Referring to FIG. 7, using the spacer 32 left on the encapsulated free layer sidewall as a self-aligned hard mask, the barrier layer 16 and pinned layer 14 are etched by the same type of physical etch as was used to etch the free layer. By doing this, one can again avoid forming any chemical damage layer but only generate a thin layer of conductive metal re-deposition 34 on the pinned layer's sidewall. Since the pinned layer is thin, the re-deposition from it would not cover the whole spacer but at most the bottom portion of the spacer 32. Here it should be noted that, as shown in Table 1, carbon's IBE etch rate is only ˜60 A/s, much lower than those commonly used metals in the MTJ hard mask and stack, which are usually larger than 200 A/s. That is, the spacer's etch rate would be ≤⅓ the etch rate of the pinned layer. Therefore after this etch step, enough of the spacer 32, ≥1 nm, would remain to protect the encapsulated free layer.

TABLE 1 Summary of various materials' IBE etch rate in Angstroms/minute (from http://www.microfabnh.com/ion beam etch rates.php) Etch Rate Etch Rate Material (A/min) Material (A/min) Ag 1050 NiCr 309 Al 48 Pb 1517 Au 630 PbTe 2199 AZ 1350 117 Pd 642 C 64 Rb 2333 CdS 1283 Re 303 Co 262 Rh 420 Cr 309 Riston 14 146 Cu 513 Ru 356 Fe 204 Sb 1889 Si 216 Ni80Fe2O 292 SiC 204 Ni 309 SiO2 192 Zr 332 Hf 385 Ta 245 InSb 887 Ta2O5 350 Ir 344 TaC 87 Ge 537 TaN 233 Mg 131 Ti 192 Mn 507 Ti or TiW 195 Mo2C 163 W 198 Nb 274 Y 554 Ni 309 Zr 332

The re-deposition from the free and pinned layer etches, 26 and 34, respectively, are separated by the encapsulation 28 and spacer 32 materials, without forming a continuous path to short the devices. This approach is of particular use for sub 60 nm MRAM devices where the spacer has to be thin enough to maintain the pattern geometry for the self-aligned etch, but still be capable of protecting the previously defined free layer. Another benefit of this spacer etch is that the pinned layer has a larger volume than the free layer, about 50-60 nm for the pinned layer and about 40-50 nm for the free layer, so that the pinned layer has strong enough pinning strength to stabilize the magnetic state in the free layer.

After the pinned layer etch, the whole device can be filled with dielectric material 36 and flattened by chemical mechanical polishing (CMP) to expose the top electrode 20, as shown in FIG. 8. The remaining spacer 32 on the sidewall can stay within the structure without affecting the device integrity and device performance. A top metal contact 38 contacts the top electrode 20.

The process of the present disclosure employs a physical etch to eliminate chemical damage on the MTJ sidewall and prevents the conductive re-deposition from shorting the devices. It has been considered to be difficult to achieve these two results simultaneously, but the process of the present disclosure provides these results.

The process of the present disclosure will be used for MRAM chips of size smaller than 60 nm as problems associated with chemically damaged sidewalls and re-deposition from the bottom electrode become very severe for these smaller sized MRAM chips.

Although the preferred embodiment of the present disclosure has been illustrated, and that form has been described in detail, it will be readily understood by those skilled in the art that various modifications may be made therein without departing from the spirit of the disclosure or from the scope of the appended claims.

Claims

1. A method comprising:

depositing a magnetic tunneling junction (MTJ) stack on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer;
depositing a top electrode layer on the MTJ stack;
depositing a hard mask on the top electrode layer;
first etching the top electrode layer and the free layer of the MTJ stack not covered by the hard mask;
thereafter encapsulating the hard mask, the top electrode layer, and the free layer with an encapsulation layer;
depositing a spacer layer over the encapsulation layer and etching away the spacer layer on horizontal surfaces leaving spacers on sidewalls of the encapsulation layer wherein sidewalls of the free layer are covered by a combination of the encapsulation layer and the spacers; and
thereafter second etching the barrier layer and the pinned layer to form a MTJ structure, wherein a topmost surface of the MTJ structure is covered by the encapsulation layer after the second etching, the topmost surface of the MTJ structure faces away from the bottom electrode.

2. The method according to claim 1 wherein the first etching comprises a pure Ar RIE or IBE etching and wherein the first etching stops at a boundary between the free layer and the barrier layer or the first etching stops within the barrier layer.

3. The method according to claim 1 wherein the encapsulation layer comprises Al2O3, SiON, or SiN, in-situ or ex-situ deposited over partially etched the MTJ stack and the bottom electrode by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) to a thickness of 5-30 nm.

4. The method according to claim 1 wherein the depositing the spacer layer comprises depositing carbon, TaC, or Al in-situ or ex-situ by CVD, PVD, or ALD to a thickness of 10-30 nm.

5. The method according to claim 1 wherein the etching away the spacer layer comprises etching with:

O2 if the spacer layer comprises carbon;
a fluorine carbon or a halogen if the spacer layer comprises TaC; and
a halogen if the spacer layer comprises Al wherein the spacers have a thickness of 5-20 nm.

6. The method according to claim 1, wherein the second etching comprises a pure Ar RIE or IBE etching, and

wherein an etch rate of the spacers is ≤⅓ an etch rate of the pinned layer wherein after the second etching a thickness ≥1 nm of the spacers remains to protect encapsulated the free layer.

7. The method according to claim 1 after the second etching further comprising:

covering the MTJ structure with a dielectric layer;
flattening the dielectric layer by chemical mechanical polishing (CMP) to expose the top electrode layer; and
forming a top metal contact to the top electrode layer.

8. The method according to claim 1, further comprising forming a patterned material layer on the hard mask, and

wherein the topmost surface of the MTJ structure is formed of the patterned material layer such that the encapsulation layer physically contacts a top surface of the patterned material layer, the top surface of the patterned material layer faces away from the bottom electrode.

9. The method according to claim 1 wherein there is no chemical damage to sidewalls of the free layer and wherein a first layer of conductive metal re-deposition is formed on the sidewalls of the free layer.

10. The method according to claim 9 wherein there is no chemical damage to sidewalls of the barrier layer and he pinned layer and wherein a second layer of conductive metal re-deposition is formed on the sidewalls of the barrier layer and the pinned layer and wherein the second layer of conductive metal re-deposition does not contact the first layer of conductive metal re-deposition because the first and second conductive metal re-deposition layers are separated by the encapsulation layer and the spacers.

11. A method for fabricating a magnetic tunneling junction (MTJ) structure comprising:

depositing a MTJ stack on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer;
depositing a top electrode layer on the MTJ stack;
depositing a hard mask on the top electrode layer;
first physical etching the top electrode layer and the free layer of the MTJ stack not covered by the hard mask wherein there is no chemical damage to sidewalls of the free layer and wherein a first layer of conductive metal re-deposition is formed on the sidewalls of the free layer;
thereafter encapsulating the hard mask, the top electrode layer, and the free layer with an encapsulation layer;
depositing a spacer layer over the encapsulation layer and etching away the spacer layer on horizontal surfaces leaving spacers on sidewalls of the encapsulation layer wherein sidewalls of the free layer are covered by a combination of the encapsulation layer and the spacers; and
thereafter second physical etching the barrier layer and the pinned layer to complete formation of the MTJ structure wherein there is no chemical damage to sidewalls of the barrier layer and the pinned layer and wherein a second layer of conductive metal re-deposition is formed on the sidewalls of the barrier layer and the pinned layer and wherein the second layer of conductive metal re-deposition does not contact the first layer of conductive metal re-deposition because the first and second conductive metal re-deposition layers are separated by the encapsulation layer and the spacers.

12. The method according to claim 11 wherein the first etching comprises a pure Ar RIE or IBE etching and wherein the first etching stops at a boundary between the free layer and the barrier layer or the first etching stops within the barrier layer.

13. The method according to claim 11 wherein the encapsulation layer comprises Al203, SiON, or SiN, in-situ or ex-situ deposited over partially etched the MTJ stack and the bottom electrode by chemical vapor deposition (CVO), physical vapor deposition (PVO), or atomic layer deposition (ALO) to a thickness of 5-30 nm.

14. The method according to claim 11 wherein the depositing the spacer layer comprises depositing carbon, TaC, or Al in-situ or ex-situ by CVO, PVO, or ALO to a thickness of 10-30 nm.

15. The method according to claim 11 wherein the etching away the spacer layer comprises etching with:

O2 if the spacer layer comprises carbon;
a fluorine carbon or a halogen if the spacer layer comprises TaC; and
a halogen if the spacer layer comprises Al wherein the spacers have a thickness of 5-20 nm.

16. The method according to claim 11 after the second etching further comprising:

covering the MTJ structure with a dielectric layer;
flattening the dielectric layer by chemical mechanical polishing (CMP) to expose the top electrode layer; and
forming a top metal contact to the top electrode layer.

17. The method according to claim 11 wherein the second etching comprises a pure Ar RIE or IBE etching.

18. The method according to claim 17 wherein an etch rate of the spacers is ≤⅓ an etch rate of the pinned layer wherein after the second etching a thickness ≥1 nm of the spacers remains to protect encapsulated the free layer.

19. A method comprising:

forming a pinned layer on a bottom electrode layer;
forming a tunnel barrier layer on the pinned layer;
forming a free layer on the tunnel barrier layer;
patterning the free layer, wherein a first metal re-deposition layer is formed on a sidewall of the free layer during the patterning of the free layer;
forming an encapsulation layer directly on the tunnel barrier layer and the first metal re-deposition layer;
forming a spacer material directly on the encapsulation layer;
removing a first portion of the spacer material to expose a portion of the encapsulation layer, wherein a second portion of the spacer material remains after the removing of the first portion of the spacer material; and
patterning the tunnel barrier layer and the pinned layer while using the second portion of the spacer material layer as a mask.

20. The method of claim 19, wherein a second metal re-deposition layer is formed directly on the encapsulation layer, the tunnel barrier layer, and the pinned layer from the patterning of the tunnel barrier layer and the pinned layer.

Referenced Cited
U.S. Patent Documents
9087981 July 21, 2015 Hsu et al.
9406876 August 2, 2016 Pinarbasi
9728718 August 8, 2017 Machkaoutsan et al.
20110235217 September 29, 2011 Chen
20150255507 September 10, 2015 Pakala
20150340593 November 26, 2015 Lu
20170084828 March 23, 2017 Hsu
20190341090 November 7, 2019 Annunziata
Patent History
Patent number: 10964887
Type: Grant
Filed: May 22, 2018
Date of Patent: Mar 30, 2021
Patent Publication Number: 20190363249
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Hsinchin)
Inventors: Yi Yang (Fremont, CA), Dongna Shen (San Jose, CA), Yu-Jen Wang (San Jose, CA)
Primary Examiner: Marcos D. Pizarro
Assistant Examiner: Antonio B Crite
Application Number: 15/986,244
Classifications
Current U.S. Class: Having Tunnel Junction Effect (360/324.2)
International Classification: H01L 43/12 (20060101); H01L 43/02 (20060101); H01L 43/08 (20060101); H01F 41/34 (20060101); H01F 10/32 (20060101); H01F 41/30 (20060101); G11C 11/16 (20060101);