Data Clocking Patents (Class 360/51)
  • Patent number: 8411385
    Abstract: Various embodiments of the present invention provide systems and methods for timing recovery. As an example, timing recovery circuits include: a first digital interpolation circuit, a second digital interpolation circuit, a phase selection circuit, and a sampling clock rotation circuit. The first digital interpolation circuit is operable to receive a data input and to provide a first interpolated output corresponding to a first phase, and the second digital interpolation circuit is operable to receive the data input and to provide a second interpolated output corresponding to a second phase. The phase selection circuit operable to select the first phase for processing, and the sampling clock rotation circuit is operable to move a sampling clock away from the first phase.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: April 2, 2013
    Assignee: LSI Corporation
    Inventor: Viswanath Annampedu
  • Publication number: 20130077188
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide clock generation systems that include: a first clock multiplier circuit, a second clock multiplier circuit, a modulus accumulator circuit, and a data clock phase control circuit. The first clock multiplier circuit is operable to multiply a reference clock by a first multiplier to yield a first domain clock, and the second clock multiplier circuit is operable to multiply the reference clock by a second multiplier to yield a second domain clock. The modulus accumulator circuit is operable to yield a value indicating a fractional amount of the second domain clock that an edge of the second domain clock is offset from a trigger signal. The data clock phase control circuit is operable to phase shift the second domain clock by a phase amount corresponding to the fractional amount.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Inventor: Jeffrey P. Grundvig
  • Patent number: 8405925
    Abstract: A method for randomizing data to mitigate false VFO detection is described. In one embodiment, such a method includes simultaneously receiving multiple input data streams. Each input data stream is associated with a different track on a magnetic tape medium. The input data streams are simultaneously scrambled to produce multiple randomized data streams. The input data streams are scrambled such that different bit patterns are produced in the randomized data streams even where corresponding bit patterns in the input data streams are identical. The randomized data streams are simultaneously written to their associated data tracks on the magnetic tape medium. A corresponding apparatus is also described.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Roy Daron Cideciyan, Thomas Mittelholzer, Paul J. Seger, Keisuke Tanaka
  • Patent number: 8405924
    Abstract: A method and apparatus are disclosed for detecting an address mark in a data stream having a preamble followed by the address mark. The end of the preamble is detected in the data stream, which is then used to open a window to search for the address mark. If the address mark is not detected during the window, the search for the address mark is restarted. The window can have a duration based on a length of the address mark. The address mark can be, for example, a servo address mark following a servo preamble or a read address mark following a read preamble. The preamble can have a 2T pattern and the preamble can be detected by determining if energy associated with a 2T frequency is greater than energy associated with a non-2T frequency. The end of the preamble can be performed by an EndOf2T detector that detects a break in an expected bit pattern.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: March 26, 2013
    Assignee: Agere Systems LLC
    Inventor: Viswanath Annampedu
  • Patent number: 8405928
    Abstract: Methods, apparatuses, and systems implementing analog techniques to decode signals extracted from servo wedges of computer-readable storage media. A digital representation of at least a portion of a repeatable runout (RRO) signal derived from an analog signal read from a computer-readable storage medium is obtained. An estimate of a magnitude of the RRO signal is determined based on the digital representation. An error signal is generated to represent a difference between the estimate of the magnitude and a specified level of the magnitude of the RRO signal, and a gain value is configured, based on the error signal, for decoding a signal from the computer-readable storage medium.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: March 26, 2013
    Assignee: Marvell International Ltd.
    Inventors: Zaihe Yu, Zining Wu, Michael Madden
  • Patent number: 8405332
    Abstract: Systems, methods and computer program products for reducing or removing current spikes generated during a current recirculation period associated with phase switching in a spindle motor are described. In some implementations, the duty cycle of the drive signals applied to the windings of the spindle motor can be adjusted to reduce or eliminate the current surge resulting from current recirculation. In some implementations, the duty cycle of the drive signals during spin-up can be reduced based on a current limit, and the reduced duty cycle can then be used to drive the spindle motor taking into account of current surges in the supply current.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: March 26, 2013
    Assignee: Marvell International Ltd.
    Inventors: Ravishanker Krishnamoorthy, Foo Leng Leong
  • Patent number: 8400891
    Abstract: An apparatus includes a read/write head disposed on a slider, a control circuit disposed on the slider, and an adjustable delay line disposed on the slider. The adjustable delay line delays transmission of aligned write data to the read/write head by an adjustable delay. The adjustable delay is controlled by the control circuit a function of read synchronization data provided by the read/write head.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: March 19, 2013
    Assignee: Seagate Technology LLC
    Inventor: Mark Anthony Gubbins
  • Patent number: 8396109
    Abstract: An adaptive receiver equalizes incoming data expressed as a series of symbols, the degree of equalization being adjusted by some adaptive control logic. An amplitude detector samples the amplitude of the eye openings of incoming symbols and conveys the resulting measures of eye amplitude to the adaptive control logic. The control logic experiments with different equalization settings while monitoring the resulting eye amplitude to find the equalization setting that provides incoming data eyes of the highest amplitude. A data filter may be included to enable the amplitude detector only in response to particular incoming data patterns.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: March 12, 2013
    Assignee: Rambus Inc.
    Inventor: Ramin Farjad-rad
  • Patent number: 8395858
    Abstract: Methods and apparatus are provided for performing interpolated timing recovery using a frequency and phase estimate. An analog signal representing a sector is asynchronously sampled and stored in a storage device. A retiming circuit reads the stored samples and, based on first portions of first and second timing portions of the sector, determines phase adjustments. The retiming circuit generates a signal representing the samples at the adjusted phase and determines sample shift adjustments based on the generated signal and second portions of the first and second timing portions. The retiming circuit computes start and end indices of the sector in the buffer based on the sample shift adjustment and phase adjustment. The start and end indices may be used to compute a frequency estimate. The frequency estimate and a phase adjustment is used to interpolate the asynchronous samples at the appropriate frequency and phase.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: March 12, 2013
    Assignee: Marvell International Ltd.
    Inventors: Ke Han, Nitin Nangare, Zining Wu, Gregory Burd, Michael Madden
  • Patent number: 8379339
    Abstract: A system and method involving a read channel pipeline having a plurality of vector sequencers that may be used to control the processing blocks. In one embodiment, a read channel pipeline may include processing blocks that may be controlled a command word provided by vector sequencers. Incoming data may be delineated by identifying an early period, a steady-state period, and a trailing period. Instead of controlling these blocks with a static state machine controller, a plurality of vector sequencers are coupled to the plurality of processing blocks. Thus, a first vector sequencer may control the processing blocks during the early period and the steady state period, but then hand off control to a second vector sequencer for the trailing period. Using vector sequencers for implementing command words allows for greater programming flexibility once the device has been manufactured and deployed for use.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: February 19, 2013
    Assignee: STMicroelectronics, Inc.
    Inventors: Sivagnanam Parthasarathy, Alessandro Risso, Dillip Dash
  • Patent number: 8379498
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, an inter-track interference signal estimator circuit, and a sync mark detector circuit. The data buffer is operable to store a previous track data set that includes a first sync pattern. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The current track data set includes a second sync pattern. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: February 19, 2013
    Assignee: LSI Corporation
    Inventors: George Mathew, Ming Jin, Shaohua Yang, Erich F. Haratsch
  • Publication number: 20130033777
    Abstract: A system and method of establishing write timing in a disk drive using bit patterned media and a magnetic head with read-write offset in which servoing and writing occur on different tracks with timing offsets. Initially, the distance between the servoing and writing tracks is determined for each track/head position in accordance with head geometry and skew angle. The relative timing errors are then measured by iteratively writing data at timing offset increments to determine the optimal timing offset for the servoing/writing track pair, and then writing the offset to sync fields on the servoing tracks of the disk.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 7, 2013
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Toshiki Hirano, Xiaotian Sun
  • Publication number: 20130021690
    Abstract: Various embodiments of the present invention provide systems and methods for calculating and/or modifying fly height. For example, a circuit for calculating fly height is disclosed that includes: a first pattern detector circuit, a second pattern detector circuit, a first pattern fly height calculation circuit, a second pattern fly height calculation circuit, a first averaging circuit, a second averaging circuit, and a combining circuit.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 24, 2013
    Inventors: Haitao Xia, George Mathew, Ming Jin, Shaohua Yang
  • Publication number: 20130010383
    Abstract: Embodiments described herein provide for patterned media concentric zones with an alternating series of concentric servo zones and overlap zones. The overlap zones facilitate the writing of servo data between servo zones of different servo frequency. The overlap zones may be dual frequency zones. The dual frequency zones have a first set of overlap patterns with the substantially identical pattern as the bordering lower frequency servo zone and a second set of overlap patterns with the substantially identical pattern as the bordering higher frequency servo zone. A bootstrap zone can be included near the inner diameter to assist initial servo writing. Alternatively the overlap zones are bootstrap zones. Such bootstrap zones have both bootstrap patterns and overlap patterns, the overlap patterns have the substantially identical pattern as a bordering servo zone. Bootstrap patterns only require DC magnetization for servo operability.
    Type: Application
    Filed: July 6, 2011
    Publication date: January 10, 2013
    Inventors: Keiichiro Nonaka, Kei Yasuna, Masahito Kobayashi
  • Publication number: 20130010382
    Abstract: Embodiments described herein provide for patterned media concentric zones with an alternating series of concentric servo zones and overlap zones. The overlap zones facilitate the writing of servo data between servo zones of different servo frequency. The overlap zones may be dual frequency zones. The dual frequency zones have a first set of overlap patterns with the substantially identical pattern as the bordering lower frequency servo zone and a second set of overlap patterns with the substantially identical pattern as the bordering higher frequency servo zone. A bootstrap zone can be included near the inner diameter to assist initial servo writing. Alternatively the overlap zones are bootstrap zones. Such bootstrap zones have both bootstrap patterns and overlap patterns, the overlap patterns have the substantially identical pattern as a bordering servo zone. Bootstrap patterns only require DC magnetization for servo operability.
    Type: Application
    Filed: July 6, 2011
    Publication date: January 10, 2013
    Inventors: Keiichiro Nonaka, Kei Yasuna, Masahito Kobayashi
  • Publication number: 20130003214
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a servo address mark count circuit, a user sync mark count circuit, and an offset calculation circuit. The servo address mark count circuit is operable to provide: a first count corresponding to a first servo address mark within a first track of a storage medium, a second count corresponding to a second servo address mark within the first track, a third count corresponding to a third servo address mark within a second track of the storage medium, and a fourth count corresponding to a fourth servo address mark within the second track. The user sync mark count circuit is operable to provide: a fifth count corresponding to a first user sync mark within the first track, and to provide a sixth count corresponding to a second user sync mark within the second track.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventors: Jeffrey P. Grundvig, Jason D. Byrne, Jefferson Singleton
  • Publication number: 20130003215
    Abstract: A given reference pattern is written on bit patterned media that has an initial reference pattern already disposed thereon. A write phase and frequency is detected based on the initial reference pattern and the given reference pattern is written on the bit patterned media at the detected write phase and frequency.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: David Erich Tetzlaff, Puskal P. Pokharel, Rene Johannes Marinus van de Veerdonk
  • Patent number: 8345373
    Abstract: Various embodiments of the present invention provide systems and methods for phase offset based spectral aliasing compensation. For example, a circuit for spectral aliasing reduction is disclosed that includes a phase shift circuit operable to phase shift an analog input signal and to provide a phase shifted analog signal; a first analog to digital converter circuit operable to provide a first series of digital samples corresponding to the analog input signal at a sampling frequency; a second analog to digital converter circuit operable to provide a second series of digital samples corresponding to the phase shifted analog signal at the sampling frequency; and an averaging circuit operable to average the first series of digital samples with the second series of digital samples to yield an average output.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: January 1, 2013
    Assignee: LSI Corporation
    Inventors: George Mathew, Yuan Xing Lee, Hongwei Song
  • Patent number: 8345369
    Abstract: Various embodiments of the present invention provide systems and methods for identifying a reproducible location on a storage medium. As an example, a circuit is discussed that includes a data storage circuit, a pattern comparison circuit, and a threshold comparison circuit. The data storage circuit is operable to store a first set of data samples corresponding to a region of interest. The pattern comparison circuit is operable to compare a subset of the first set of data samples with a subset of a second set of data samples corresponding to the region of interest. The pattern comparison circuit is operable to yield a match value corresponding to a degree of similarity between the first set of data samples with the subset of a second set of data samples. The threshold comparison circuit is operable to indicate an anchor point based at least in part on the magnitude of the match value relative to a threshold value.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: January 1, 2013
    Assignee: LSI Corporation
    Inventors: Haitao Xia, Shaohua Yang, George Mathew
  • Patent number: 8339728
    Abstract: Example embodiments may provide a magnetic memory device. The example embodiment magnetic memory devices may include a plurality of memory tracks, bit lines, connectors, a first input portion, and/or selectors. The memory track(s) may be stacked on a substrate to form a multi-stack. A plurality of magnetic domains may be formed in the memory track so that a data bit may be represented by a magnetic domain and may be stored in an array. The bit line(s) may be formed along respective memory tracks. The connector(s) may form a magnetic tunnel junction (MTJ) cell with one data bit region of the memory track. The first input portion may be electrically connected to each memory track and may input a magnetic domain motion signal to move data stored on a data bit region of the memory track to an adjoining data bit region. The selector(s) may select a memory track from a plurality of memory tracks on which a reading and/or writing operation may to be performed.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: December 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kee-won Kim, Tae-wan Kim, Young-jin Cho, In-jun Hwang
  • Patent number: 8339723
    Abstract: A length of a separator to be skipped on the storage disk is compared with a threshold. The threshold is associated with a maximum value for which a timing loop is able to be paused without causing the timing loop to have inaccurate timing. If the length is greater than the threshold, a first split sector format is assigned to the split sector and that information is recorded. In such cases, a first portion and a second portion both include synchronization information. If the length is less than the threshold, a second split sector format is assigned to the split sector and that information is recorded. In such cases, the first portion includes synchronization information and the second portion of the split sector excludes synchronization information.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: December 25, 2012
    Assignee: Link—A—Media Devices Corporation
    Inventors: Kwok W. Yeung, Kin Ming Chan
  • Patent number: 8339722
    Abstract: Systems, methods and computer program products for estimating a position of a head in relation to a storage medium are described. A read channel can be used to receive a readback signal containing servo information obtained from a storage medium, and to demodulate the received servo information including position error signals to deduce a position of a read/write head in relation to the storage medium. The read channel can demodulate the received servo information to obtain amplitude and/or phase information. In some implementations, digital sampled values can be generated based on the readback signal, and the digital sampled values can be integrated using an integrator to obtain accurate and reliable amplitude and phase information that are used to determine the position of the read/write head.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: December 25, 2012
    Assignee: Marvell International Ltd.
    Inventors: Zining Wu, Michael Madden
  • Patent number: 8331051
    Abstract: A disc drive system provides increased reliability by detecting and correcting errors associated with bit-patterned media. Write synchronization errors associated with bit-patterned media are addressed by including data storage for temporarily storing data that is being written to the disc drive. The data is read from both the disc drive and the storage medium and compared to detect write synchronization errors. The disc drive system utilizes the identified write synchronization errors for at least one of timing recovery, equalizer training detection, error correction code application, and error recovery.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: December 11, 2012
    Assignee: Seagate Technology LLC
    Inventors: Michael L. Mallary, Mehmet F. Erden, Ching He, Venkata S. Chilaka
  • Patent number: 8331050
    Abstract: A write clock synchronization system includes a channel module that reads a servo section of a bit-patterned magnetic medium to determine a preamble signal based on the servo section. An initial phase estimating system estimates an initial phase of the preamble signal based on servo clock samples of the preamble signal and estimates an initial phase of the preamble signal based on write clock samples of the preamble signal. A phase determination module estimates a phase of the write clock signal based on the initial phase of the preamble signal estimated using the servo clock samples and the initial phase of the preamble signal estimated using the write clock samples. A phase error module estimates a phase error based on the phase of the write clock signal. The channel module writes data to discontinuous bit islands of the bit-patterned magnetic medium based on the phase error.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: December 11, 2012
    Assignee: Marvell International Ltd.
    Inventors: Qiyue Zou, Xueshi Yang, Gregory Burd
  • Publication number: 20120293885
    Abstract: According to one embodiment, a position demodulator includes a demodulator, a phase corrector, and a position demodulating module. The demodulator demodulates a first demodulated signal and a second demodulated signal having a phase difference of 90 degrees from the first demodulated signal as a result of discrete Fourier transform operation on a read signal of a null servo pattern recorded in a servo area of a medium read out by a head. The phase corrector carries out correction to tilt respective vectors of the first demodulated signal and the second demodulated signal represented on a phase plane by a predetermined angle. The position demodulating module demodulates a positional signal for determining the position of the core of the head based on the first demodulated signal and the second demodulated signal corrected by the phase corrector.
    Type: Application
    Filed: February 9, 2012
    Publication date: November 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuhiko KOSUGI, Kazuhiko Takaishi, Takeshi Hara, Hiroshi Oyabu
  • Publication number: 20120293886
    Abstract: A tape drive receives multiple write requests for data pieces and a synchronization request corresponding to the write requests from a device, performs a synchronization process, and returns a completion status of the synchronization request. The tape drive includes a write controller that stores data pieces transferred from the device in the buffer, according to a first write request, receives a first synchronization request and then a subsequent write request for at least one data piece, and returns the completion status when processing for the first synchronization request is completed and the subsequent write request is received with a command queuing function.
    Type: Application
    Filed: May 17, 2012
    Publication date: November 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Atsushi Abe, Katsuhiko Hagiwara
  • Patent number: 8315003
    Abstract: In an implementation, a media drive comprises bit patterned magnetic media and one or more modules. The one or more modules are to cause data to be written on the bit patterned magnetic media in a data sector that includes a synchronization mark disposed between data blocks of the data sector.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: November 20, 2012
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Patent number: 8300342
    Abstract: Embodiments of the present invention relate to the detection of synchronization marks in data storage and retrieval. To detect a synchronization mark, embodiments of the present invention require both pattern matching and proper phase alignment, following a repeating synchronization field. According to one particular embodiment, proper phase alignment following a repeated four bit synchronization field, is utilized in conjunction with pattern matching, to identify a synchronization mark. By allowing a synchronization mark to be identified only with proper phase alignment at the earliest possible occurrence of the synchronization mark, accuracy of synchronization mark detection may be improved.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: October 30, 2012
    Assignee: HGST Netherlands B.V.
    Inventors: Richard Leo Galbraith, Weldon Mark Hanson, Travis Roger Oenning, Todd Carter Truax
  • Patent number: 8300343
    Abstract: According to one embodiment, a disk drive having a magnetic disk of the bit pattern media type is provided. The disk drive has a reproduction module configured to reproduce a signal from a measurement area provided on the magnetic disk and holding groups of phase-shift measuring bits, a measurement module configured to measure a phase shift that a write clock signal has with respect to data recording bits held in a data record area provided on the magnetic disk, when the signal reproduced by the reproduction module is indefinite, and a recording module configured to record data that corresponds to the data recording bits, by using the write clock signal adjusted by the phase shift.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: October 30, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Mutoh
  • Patent number: 8300344
    Abstract: In an implementation, a media drive includes bit patterned magnetic media and a module. The module is to cause data encoded by one or more error correction codes to be written on the bit patterned magnetic media with a constraint that is configured to be used to synchronize the data if a bit insertion or deletion occurs.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: October 30, 2012
    Assignee: Marvell International Ltd.
    Inventors: Xueshi Yang, Gregory Burd
  • Patent number: 8301886
    Abstract: An authentication method for authenticating an article in a device includes the steps of (a) reading an identification number stored on the article, (b) reading an authentication number stored on the article, (c) determining an input number based at least in part on the identification number, (d) applying an authentication function to the input number to calculate an output number, (e) determining that the article is authentic only if the authentication number corresponds to the output number, and (f) permitting use of the article in the device if the article is authentic, and disabling use of the article in the device if the article is not authentic.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: October 30, 2012
    Assignee: ZIH Corp.
    Inventors: Clive P. Hohberger, Boris Y. Tsirline
  • Patent number: 8289645
    Abstract: According to one embodiment, there is provided a magnetic disk apparatus having a magnetic disk having magnetic dot lines each including magnetic dots arrayed at equal intervals in a down track direction, and a read/write head which uses a plurality of adjacent magnetic dot lines as one track and sequentially performs read and write on the magnetic dots included in the magnetic dot lines constituting the track, in which the magnetic dots included in each of the magnetic dot lines in each track of the magnetic disk are displaced in the down track direction from the magnetic dots included in the adjacent dot line in the track depending on a possible skew angle between the read/write head and the track so that the magnetic dots are sequentially accessed by the read/write head.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: October 16, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Sakurai, Akira Kikitsu, Kazuto Kashiwagi
  • Patent number: 8289643
    Abstract: A method and disk drive for calibrating a phase of a clock in the disk drive. The phase of the clock in the disk drive is changed such that a rate of change for the phase is substantially constant. A pattern of data is written to a magnetic material in the disk drive after the rate of change for the phase becomes substantially constant and while changing the phase of the clock. A selected phase of the clock at which the pattern of data that is written on the magnetic material has a desired quality is identified using the rate of change for the phase, a first point in time at which a timing mark on the magnetic material is read, a second point in time at which the timing mark is read, and a third point in time at which the pattern of data has the desired quality.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: October 16, 2012
    Assignee: LSI Corporation
    Inventors: Jeffrey Paul Grundvig, Joseph H. Havens
  • Patent number: 8284510
    Abstract: Embodiments of the present disclosure provide a method including recording time stamps for a repeating characteristic of a spindle back electromotive force (BEMF) signal and comparing one or more of the recorded time stamps for the repeating characteristic of the spindle BEMF signal with an expected value for the one or more recorded time stamps to detect a timing error associated with writing a servo pattern on a machine readable medium of a self-servo write (SSW) system. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: October 9, 2012
    Assignee: Marvell International Ltd.
    Inventors: David Rutherford, Man Cheung
  • Patent number: 8279727
    Abstract: In one embodiment the present invention includes a circuit comprising a switch and a switch driver. The switch is configured to provide synchronous rectification switching of a back-EMF voltage. The synchronous rectification switching produces a source voltage. The switch driver is configured to receive the back-EMF voltage and the source voltage. The switch driver provides a control signal to a control terminal of the switch. The control signal has a frequency. The frequency is used to control an amount of the synchronous rectification switching. Accordingly, the frequency reduces a dissipated power associated with the synchronous rectification switching.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: October 2, 2012
    Assignee: Marvell International Ltd.
    Inventors: Siew Yong Chui, Rudy Kurniawan, Cheng Yong Teoh
  • Patent number: 8279546
    Abstract: Systems and methods for detecting and designing enhanced disk sync marks using correlation detection are disclosed. The enhanced sync marks provide better noise immunity and higher detection rates over traditional Viterbi-based detection schemes even with a shorter sync mark length. The disk sync mark may provide optimal noise immunity for a particular target polynomial or a plurality of common target polynomials. The minimum Euclidean distance between a candidate sync mark and a plurality of right-shifted versions of the candidate sync mark is computed and compared with other candidate sync marks. The sync mark with the largest minimum Euclidean distance is then selected as the optimal mark. Systems and methods are also disclosed for detecting and designing a disk sync mark using correlation detection when the polarity of the disk is unknown or time-varying.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: October 2, 2012
    Assignee: Marvell International Ltd.
    Inventors: Ke Han, Zining Wu, Michael Madden
  • Patent number: 8274749
    Abstract: A control module for a rotating storage medium. The control module includes: a memory, a buffer control module, and a disk formatter module. The memory is configured to store a data wedge format table including a plurality of entries. The buffer control module is configured to maintain a queue, wherein each of a plurality of entries of the queue is based on a corresponding one of the plurality of entries of the data wedge format table, and wherein each of the plurality of entries of the queue includes a servo number. The disk formatter module is configured to compare the servo numbers of the plurality of entries of the queue to present servo information, wherein the present servo information is based on a present position of a read/write device in relation to the rotating storage medium.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: September 25, 2012
    Assignee: Marvell International Ltd.
    Inventors: Daniel R. Pinvidic, Lim Hudiono, Stanley K. Cheong
  • Patent number: 8274750
    Abstract: A read and write system comprising a mark detection module, an offset estimation module, and a frequency adjustment module. The mark detection module is configured to generate (i) a first mark indicator when first servo data is read from a storage medium, and (ii) a second mark indicator when second servo data is read from the storage medium. The offset estimation module is configured to estimate at least one of a first distance or an offset angle based on (i) a first location of the storage medium, and (ii) a period between times when the first mark indicator and the second mark indicator are generated. The frequency adjustment module is configured to adjust a sampling frequency at which user data is read from the storage medium based on the at least one of the first distance or the offset angle.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: September 25, 2012
    Assignee: Marvell International Ltd
    Inventor: Michael Madden
  • Publication number: 20120229929
    Abstract: According to one embodiment, a magnetic recording medium includes: a data area where a plurality of first magnetic dots are placed at predetermined positions to record information, the data area being formed on a surface of the magnetic recording medium; a servo area where a plurality of second magnetic dots for specifying the positions of the first magnetic dots are placed at predetermined positions, the servo area being formed on a surface of the magnetic recording medium; and servo address marks being doubly formed in the servo area, and subdivision being performed while boundary positions of second magnetic dots of one of the servo address marks and boundary positions of second magnetic dots of another one of the servo address marks are different from each other in a radial direction.
    Type: Application
    Filed: February 22, 2012
    Publication date: September 13, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruhiko IZUMI
  • Patent number: 8264388
    Abstract: A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 11, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Hanan Cohen, Simon Pang
  • Patent number: 8254049
    Abstract: Various embodiments of the present invention provide systems and methods for synchronizing data processing. As one example, a method for synchronizing data processing is disclosed that includes receiving a data input, and sampling the data input at a sample period to generate a sample set. A first pattern is received and a first periodic boundary associated with the first pattern is identified. In one particular case, the first pattern is a preamble pattern included as sector data on a storage medium, and the first periodic boundary is a 4T boundary. Further, a second pattern is detected in the sample that is used to establish a second periodic boundary. In one particular case, the second pattern is a SAM pattern included as sector data on a storage medium, and the second periodic boundary is a 1T boundary. Based at least in part on the first periodic boundary and the second periodic boundary, a time to transmit or assert a data-found signal is determined.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: August 28, 2012
    Assignee: Agere Systems Inc.
    Inventor: Viswanath Annampedu
  • Patent number: 8243381
    Abstract: Various embodiments of the present invention provide systems and methods for sector address mark detection. As an example, data detection systems are disclosed that include a sector address mark detection circuit and a sector address mark quality detection circuit. The sector address mark detection circuit receives a data stream and identifies a sector address mark in the data stream. The sector address mark quality detection circuit receives a first sample and a second sample from the data stream corresponding to the sector address mark, and determines a quality of the sector address mark based at least in part on the first sample and the second sample. In various cases, one or more of the samples of the sector address mark up to all of the samples of the sector address mark may be used.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: August 14, 2012
    Assignee: Agere Systems Inc.
    Inventors: Viswanath Annampedu, Venkatram Muddhasani
  • Patent number: 8238051
    Abstract: Real time monitoring inconsistent operations in a hard disk drive, wherein the hard disk drive comprises a magnetic disk, a controller and a channel clock. A timing signal from the channel clock is measured in real time in the controller. Time intervals between sector identifier marks of the magnetic disk are detected using the timing signal from the channel clock during reading and writing operations of the hard disk drive in the controller. An inconsistency in the drive operations is detected in the controller based on changes in the time intervals between the sector identifier marks is detected during operation of the hard disk drive. The detection of the inconsistency in the drive operations is responded to.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: August 7, 2012
    Assignee: Hitachi Global Storage Technologies, Netherlands B.V.
    Inventors: Peter M. Baumgart, Robert E. Eaton, Bernhard E. Knigge
  • Patent number: 8237597
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is discussed that includes an analog to digital converter circuit, a digital filter circuit, a data detector circuit, a mimic filter circuit, and a sample clock generation circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples. The digital filter circuit is operable to receive the digital samples and to provide a filtered output. The data detector circuit is operable to perform a data detection process on the filtered output to yield a detected output. The mimic filter circuit is operable to receive the digital samples and to provide a mimicked output. The sample clock generation circuit is operable to provide a sample clock based at least in part on the detected output and the mimicked output.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: August 7, 2012
    Assignee: LSI Corporation
    Inventors: Jingfeng Liu, Haotian Zhang, Hongwei Song
  • Patent number: 8238052
    Abstract: According to one embodiment, a disk drive comprising a magnetic disk of bit-patterned type is provided. The disk drive has a reproduction module, a measurement module, and a recording module. The reproduction module outputs a reproduced signal corresponding to the phase-shift measuring bits provided on the magnetic disk. The measurement module determines that the phase shift corresponding to the phase-shift measuring bits is the phase shift of a write clock signal if the reproduced signal is determined to be indefinite on the basis of the quantization value of the reproduced signal. The recording module records data corresponding to the data recording bits, by using the write clock signal adjusted by the phase shift.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: August 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Mutoh
  • Publication number: 20120194938
    Abstract: According to one embodiment, a method of writing initial clock patterns to a disk in a magnetic disk drive is disclosed. The method can write a first timing mark in a location on a circumference of a disk using a head based on a first clock signal corresponding to a frequency of oscillation of an oscillator. The method can adjust the frequency of oscillation of the oscillator or a rotational speed of a spindle motor by detecting, as a first timestamp, a time interval at which the first timing mark is read by the head from the disk so as to coincide with a second timestamp targeted by the first timestamp. In addition, the method can write the initial clock patterns to the disk based on a second clock signal corresponding to the adjusted frequency of oscillation or the adjusted rotational speed after the adjustment.
    Type: Application
    Filed: December 6, 2011
    Publication date: August 2, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: NOBUYUKI SUZUKI
  • Publication number: 20120194939
    Abstract: A patterned medium inspection method according to the present invention includes a timing computation process including a read process reading the reproduced signal of a patterned medium under inspection and a computation process computing the signal interval values from the patterned medium reproduced signal read in the read process, and a judgment process judging the quality of the patterned medium using the reproduced signal interval values computed in the computation process.
    Type: Application
    Filed: December 12, 2011
    Publication date: August 2, 2012
    Inventors: Takuma NISHIMOTO, Masami Makuuchi, Yoshihiro Sakurai, Kunihito Higa, Fujio Onishi
  • Patent number: 8233228
    Abstract: In described embodiments, effects of frequency and phase error introduced at the outer diameter or inner diameter of the disk when a read head is used to maintain timing lock while the write head is used to write new data might be eliminated with a simple compensation circuit. Compensation circuits, modules or methods receive as input information i) write head radial position (e.g., from a wedge number that indicates the circumferential position of the heads), and ii) read head and write head relative physical offset. The timing error is measured by the system and might be automatically adjusted by the appropriate amount in order to reduce or to eliminate the differential head error when a write event (as opposed to a read event) is activated.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: July 31, 2012
    Assignee: LSI Corporation
    Inventors: Jeffrey Grundvig, Richard Rauschmayer
  • Patent number: 8223452
    Abstract: A system includes a self-servo-write (SSW) module, a read module, and a write module. The SSW module writes servo spirals on a magnetic medium of a hard disk drive (HDD) via a write head of the HDD. The read module reads the servo spirals via a read head of the HDD and generates read signals. The write module writes non-servo data on the magnetic medium via the write head based on the read signals before the SSW module writes servo wedges on the magnetic medium.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: July 17, 2012
    Assignee: Marvell International Ltd.
    Inventors: Jerome F. Richgels, Henri Sutioso, Allen Cheng Wu Hu, Scott A. Hughes
  • Patent number: 8212697
    Abstract: An arrangement is disclosed for offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain. The arrangement comprises the time-interleaved analog-to-digital converter, an analog offset estimation and compensation unit adapted to estimate a mean offset for the plurality of computing channels, a digital offset estimation and compensation unit adapted to estimate a residual computing channel specific offset for each of the plurality of computing channels, and offset compensation means. The offset compensation means are adapted to perform offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain, and to perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: July 3, 2012
    Assignee: CSR Technology Inc.
    Inventors: Christer Jansson, Rolf Sundblad