Abstract: Embodiments of the invention make it possible to conduct stable recording on a magnetic disk, even in case of changes in flying height due to thermal protrusion. In one embodiment, a compensatory recording current value A2 is used when a first section of user data is recorded in the required number of data sectors from the data sector of the starting address for recording the user data to the data sector of an intermediate address. A recording current value A3 smaller than the compensatory recording current value is used when a second section of user data is recorded in the data sectors existing from the data sector of the intermediate address towards the ending address.

Abstract: A write driver circuit for a magnetic storage medium includes a first write driver sub-circuit that has an output that communicates with a first node of a write head. The first write driver circuit includes a first driver circuit and a first feedback path between the input and the output of the first driver circuit. A second write driver sub-circuit has an output that communicates with a second node of the write head. The second write driver sub-circuit includes a second driver circuit and a second feedback path between the input and the output of the second driver circuit. The write driver circuit has a substantially constant output impedance during operation, balanced differential and common mode resistances, and a substantially constant common mode voltage across the write head during operation.

Abstract: An amplifier system with feedback current cancellation comprises an amplifier with an input, an output, and at least one stage. A feedback network communicates with the input and output of the amplifier. A feedback current cancellation module that provides a first current at the input of the amplifier that substantially cancels a second current provided at the input of the amplifier by the feedback network.

Abstract: A broadband transmission path apparatus connects a head IC and a head in a suspension. Either one of the head IC and the head is assumed as a transmission terminal and the other is assumed as a reception terminal to divide a required transmission frequency band into at least two, one of which is assumed as a low band transmission path for low frequency transmission band and the other of which is assumed as a high band transmission path for high frequency transmission band. The high band transmission path forms a resonant circuit by a resistor component, an inductance component and a capacitor component of the transmission path itself, and realizes the high frequency transmission band characteristic by a resonant frequency characteristic of the resonant circuit.

Abstract: A head IC adjusts an amplitude level of a read signal of a head to adjust dispersion of the output characteristic of the head and to adjust the read signal within the input dynamic range of the AGC of a read channel. An AGC amplifier is installed in a head IC connected to a read channel and a feedback response speed of an AGC circuit of the head IC is set to be sufficiently slower than a feedback response speed of an AGC circuit of the read channel. Also a peak hold circuit and an amplitude limiting circuit are installed in the head IC, and gain is adjusted with a holding value of the peak hold circuit. An initial gain can therefore be stably adjusted at high-speed without being influenced by signals having a small amplitude on the medium.

Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

Abstract: An apparatus, system, and method are disclosed for measuring magnetoresistive head assembly resistance. A measurement module measures a reference voltage across a reference resistance while applying a reference current to the reference resistance. In addition, the measurement module measures a test voltage across a first biasing resistor, a MR head assembly, and a second biasing resistor connected in series while applying the reference current to the first biasing resistor, the MR head assembly, and the second biasing resistor. A computation module calculates the MR head assembly resistance from the reference voltage, the test voltage, the reference resistance, and the resistances of the first and second biasing resistors.

Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a pair of current sources, such as MOS transistors, connected to the input node of a single capacitor. During the overshoot duration, the current sources selectively operate at saturation to generate a pulsed current with an amplitude of half the load current. The recharge of the capacitor is done with the load current.

Abstract: An amplifier apparatus for use with a sensor includes: (a) a first and a second amplifying circuit segment coupled with the sensor and cooperating to effect substantially balanced handling of signals received from the sensor; the first amplifying circuit segment includes a first transistor device; the second amplifying circuit segment includes a second transistor device; (b) a countercurrent unit coupled with the first and second amplifying circuit segments for receiving a first indicator signal from the first transistor device and a second indicator signal from the second transistor device; the first indicator signal represents a first parameter in the first transistor device; the second indicator signal represents a second parameter in the second transistor device; the countercurrent unit provides feedback signals to at least one of the first transistor and second transistor devices to reduce input impedance of the apparatus.

Abstract: An amplifier system with feedback current cancellation comprises an amplifier, a feedback network, first and second unity-gain buffers, a second resistance, and a current mirror. The amplifier includes an input, an output, and at least one stage. The feedback network includes a first resistance having one end that communicates with the input of the amplifier and an opposite end that communicates with the output of the amplifier. The first and second buffers each include an input and an output. The inputs of the first and second buffers communicate with the output and the input of the amplifier, respectively. The second resistance communicates with the outputs of the first and second buffers. The current mirror provides a current at the input of the amplifier that is proportional to a second current flowing through the second resistance.

Abstract: A preamplifier circuit is connected to a transducing head, and has integrated bias circuitry and offset recovery circuitry. The offset recovery circuitry is activated in response to a transition from write mode to read more to provide an output signal representative of a signal across the transducing head. The bias circuitry is driven by the output signal of the offset recovery circuitry to bias the transducing head.

Abstract: A driver for a voice coil motor in a disk drive includes a sensor that provides a sense current by sensing a coil current in the voice coil motor, a comparator that provides an error current by determining a difference between a command current and the sense current, an integrator that provides an integrated error current by integrating the error current, and an amplifier that provides the coil current by amplifying the integrated error current.

Abstract: A (e.g., hard-disk drive (HD)) system supports reader standby mode and/or writer standby mode. For reader standby mode, reader circuitry in the system's preamplifier is transitioned to a low-power mode during write operations. To provide quick transition from write mode to read mode, the reader circuitry is transitioned to pre-read mode before the end of the write operation. For writer standby mode, the preamplifier's writer circuitry is transitioned to a low-power mode during read operations. To provide quick transition from read mode to write mode, the writer circuitry is transitioned to a pre-write mode before the end of the read operation. The availability of a reader standby mode during write operations and a writer standby mode during read operations reduces power consumption as compared to HD systems that leave the reader circuitry in pre-read mode throughout each write operation and the writer circuitry in pre-write mode throughout each read operation.

Abstract: Managing temperature of a read/write head (120) in a disk drive system in which there is a power variance due to different operation modes. A circuit device (100) determines and delivers additional power needed for compensating for the temperature variance due to different operational power requirements. The power is delivered to a resistive heater (Rheat) associated with the head (120). The compensating power is based on the delivery voltage, delivery current, and resistance of the resistive heater (Rheat). The delivery current is varied to account for changes in the resistance of the resistive heater (Rheat) since it can vary with temperature. By sensing the current with a sensor (13), the resistance is determined via the sensed current and the delivery voltage. The current is adjusted for maintaining the compensating power.

Abstract: An amplifier system with feedback current cancellation comprises an amplifier having at least one stage, a feedback network, first and second replica circuits, first and second unity-gain buffers, a second resistance, and a current mirror. The feedback network includes a first resistance that communicates with an input and an output of the amplifier. The first and second replica circuits approximately replicate the DC characteristics of the output and the input of the amplifier, respectively. Inputs of the first and second buffers communicate with the first and second replica circuits, respectively. The second resistance communicates with outputs of the first and second buffers. The current mirror provides a current at the input of the amplifier that is proportional to a second current flowing through the second resistance.

Abstract: A disk drive controller including a preamplifier and a controller is disclosed, in which communications between the controller and the preamplifier are carried out over at least some shared terminals and conductors. A first pair of differential lines is provided to communicate data, sensed at read/write heads of the disk drive, from the preamplifier to the controller, and a second pair of differential lines communicates data to be written to the disk drive from the controller to the preamplifier. Control signals are communicated over a serial interface between the controller and preamplifier, over the first pair of differential lines, so that serial communication can be carried out simultaneously with the writing of data from the controller to the preamplifier. Alternatively, the control signals are communicated over the second pair of differential lines, simultaneously with the reading of data from the preamplifier to the controller.

Abstract: A system and method for providing an interface an interface between a read channel and a disk controller. The interface includes a plurality of differential pair signal lines operable to communicate data and control signals between the read channel and the hard disk controller. The data and control signal lines communicate operations for transferring data between the disk controller and the read channel. The operations may be communicated as commands that may be communicated to a preamplifier circuit to access registers in the preamplifier that may be configured to control the preamplifier operation.

Abstract: A system and method for providing an interface an interface between a read channel and a disk controller. The interface includes a plurality of differential pair signal lines operable to communicate data and control signals between the read channel and the hard disk controller in a manner that eliminates the need for a plurality of single ended digital control lines thereby reducing the signal lines between the read channel and the disk controller. The read channel further includes a circuit for receiving a reset signal at a power line.

Abstract: A head protection circuit that protects a write head and a magnetoresistive (MR) read head by bypassing electrostatic charge applied to the write head when the power of a preamplifier is turned “off” includes: a first differential mode switch and a first differential mode resistance connected between each end of the write head; and a first common mode switch and a first common mode resistance connected between one end of the write head and a ground potential. The first differential mode switch and the first common mode switch installed in the preamplifier are turned “on” when the preamplifier is turned “off” and vice versa. The head protection circuit has an effect of protecting the write head and the MR read head by bypassing common mode electrostatic charge and differential electrostatic charge generated at the ends of the write head when the preamplifier is turned “off.

Abstract: A read channel equalizer of a magnetic tape drive which equalizes digitally sampled magnetic signals detected by a read head is dynamically adapted. A detector of equalizer dynamic adaptation logic compares equalizer output signals to desired values that are based on the decoding scheme (such as +2, 0 and ?2 for PR4) to sense equalizer output signals that are offset from at least one desired value, and signals the fact of each offset and its polarity as amplitude independent error signals. The signaled sensed amplitude independent error signals are fed back to adjustable taps of the equalizer. The simplified error signals thus avoid complex calculations of waveform errors, such as least mean square calculations. The error signals may be weighted and may be adjusted to align synchronously provided error signals with asynchronous taps of the equalizer.

Abstract: A preamplifier circuit for a disk drive system is disclosed. The preamplifier circuit has first and second inputs that sense the voltage on either side of a magnetoresistive (MR) head element, which presents a varying resistance according to the localized magnetic field at a nearby disk surface. The preamplifier circuit includes a programmable input impedance circuit, which presents an impedance in parallel to feedback impedance at each of the first and second inputs. The parallel impedance presented by the programmable input impedance circuit is controlled by controlling a current source in the programmable input impedance circuit; a higher current results in a lower input impedance.

Abstract: A recording head drive circuit drives a recording head that records information on a magnetic recording medium. A switching circuit is a H-bridge circuit which includes a plurality of transistors. The switching circuit switches direction of a write current (Iw) flowing in the recording head, in accordance with a conduction state of each transistor. A write current controller controls the write current (Iw) in the recording head. An overshoot control circuit adds an overshoot current (Ios), proportional to the write current (Iw), to the write current (Iw) flowing in the recording head, in a predetermined overshoot time period.

Abstract: A disk drive data storage system, comprising a magnetic disk a head for writing data to the disk, and circuitry for providing a first voltage (HWX) to a first node (N1) and a second voltage (HWY) to a second node (N2). The first and second voltage circuitry comprises a first transistor (421P2) of a first type and coupled to the first node, a first transistor (422N2) of a second type and coupled to the second node, a second transistor (441P2) of the first type and coupled to the second node, and a second transistor (442N2) of the second type and coupled to the node. The system also comprises circuitry for providing, during a first time period, a first biasing signal (VNDY) and a second biasing signal (VPDY) and circuitry for providing, during a second time period, a third biasing signal (VNDX) and a fourth biasing signal (VPDX).

Abstract: An adaptive equalizer comprising a variable filter which equalizes a digital input signal which is input in a time sequential order, an adaptive controller unit which updates a filter coefficient of the variable filter based on an output signal of the variable filter and the input signal and according to an equalization algorithm, and a coefficient resetting unit which resets a filter coefficient of the variable filter at a predetermined timing.

Abstract: An apparatus, method, and system for providing asymmetric signal correction in a HDD system using magneto-resistive (MR) heads for reading information stored thereon. The MR head produces a signal that is asymmetric, and an asymmetric correction circuit corrects the asymmetric signal for further processing. The asymmetric correction circuitry comprises a differential amplifier having a variable gain for producing a current proportional to the asymmetric signal. The differential amplifier is coupled with two high speed switches for producing an output signal having only positive polarity. When the asymmetric correction output signal combines with the input signal, the resultant signal approximates the inverse distortion of the asymmetric input signal.

Abstract: The storage media recording/writing system includes a media drive circuit, a head retaining means, a head moving means, a head drive circuit, a signal processing circuit, and a controller to control these. The head drive circuit possesses a first semiconductor integrated circuit having an amplifier that amplifies the read signal from the head, and a second semiconductor integrated circuit placed between the first semiconductor integrated circuit and the signal processing circuit, which has a circuit that receives write data from the signal processing circuit and generates a drive signal to drive a write head. Further, the first semiconductor integrated circuit is mounted on a part near the front of the head retaining means, and the second semiconductor integrated circuit is installed on the side of the moving means.

Abstract: Embodiments in accordance with the present invention provide a disk drive and a control method in the disk drive which can obtain good recording performance by amplifying the write current according to the recording method and the recording frequency. A HDD in accordance with an embodiment of the present invention comprises a write current supply section and a write head. The write current supply section generates a write signal for recording to a disk and, based on the write current, generates a write current IW. The write head records data to the disk by the write current IW. The write current supply section comprises a write channel to generate a write signal, a write driver to generate a write current from the write signal, a high frequency pattern extracting circuit to extract high frequency pattern parts from the write signal, and a write driver to generate a write current IB from the extracted high frequency pattern parts.

Abstract: To calibrate the VGA of a read head, test signals from a DAC are input to the VGA and the output of the VGA is observed, with the gain of the VGA being adjusted as appropriate. So that the DAC need not be made with tight tolerances, a DC signal can be fed into the DAC prior to VGA calibration, and an auxiliary ADC is used to receive the output of the DAC and to determine, for a given DC input, what the signal produced by the DAC actually is. In this way, during subsequent VGA calibration the test signal from the DAC is known not by virtue of the DAC having a tight manufacturing tolerance but by virtue of the actual measurements of its outputs for given register inputs.

Abstract: A variable read output impedance control circuit of the present invention includes a variable impedance circuit as the output impedance of a magnetic media storage system. Preferably, the variable impedance circuit includes one or more diodes. The diodes are preferably coupled in series, to provide the output impedance of the magnetic media storage system. The impedance of the diodes is variable based on the amount of bias current that is provided to the diodes. The bias current is provided to the diodes from a current source preferably controlled by a controller circuit. By varying the amount of current provided to the diodes, the impedance of the diodes is adjusted. Accordingly, the read output impedance of the magnetic media storage system is controlled by controlling the bias current provided to the diodes.

Abstract: A symmetrical read element circuit for reducing electrical and magnetic noise using signal processing, such as a differential preamplifier. The circuits are symmetrically created on both sides of the read element so that the noise is balanced on both leads of the sensor element allowing substantial noise reduction by the signal processing. That is, the present invention provides symmetrical leads and pads designed for equal noise pickup, and for cancellation of the balanced noise.

Abstract: A write driver circuit (38) uses a matching resistors (R0, R1) to match the impedance of the head (32) disposed between output nodes (OUTP, OUTN). Control circuitry (Q4, Q5, Q6, Q7, R2, R4, R6 and R7) maintains the voltage at reference voltage nodes (VREFP, REFN) at essentially the same voltage as its corresponding output node. The matching resistor is disposed between the reference voltage node and the output node along with a driver (40a, 40b), which may be implemented as an AB driver. Since the voltage between the reference node and the output node is generally zero, very little current is shunted by the matching resistors, and thus, there is very little power wasted by the matching resistors. In the preferred embodiment, the output transistors of the AB drivers are driven by switched current sources (Q28 and Q29) to provide enhanced current to the bases of the output transistors on an as needed basis.

Abstract: Disk drive self-servo writing includes transferring a reference pattern by magnetic printing onto a reference disk, wherein the resulting printed reference pattern includes embedded servo information that provides servo timing and head position information, installing the reference disk and a head into the disk drive, reading the printed reference pattern using the head to generate a readback signal, sampling the readback signal at a sampling rate to generate a sampled signal, processing the sampled signal waveform spectrum to generate a recovered signal including the embedded servo information and fundamental and higher harmonics of the sampled signal, using the embedded servo information from the recovered signal to precisely position and maintain the head at concentric tracks of the reference disk, and self-writing servo patterns onto the tracks with the head.

Abstract: A write driver (38) produces balanced voltages across head (32) by using the input write data (WDX and WDY) drive transistors of a slower transistor type (typically PNP) on one half of an H-bridge configuration, while transistors of a faster transistor type (typically NPN) in the other half of the H-bridge configuration are driven indirectly by transistors of the slower type, with a trans-resistance in series with transistors of the faster type. Accordingly, the voltage nodes on either side of the write head are pulled to Vcc and Vee symmetrically. A trans-resistance block (40) uses current sources to pull current from capacitive nodes for faster switching.

Abstract: In one illustrative example disclosed, a magnetic storage device includes at least one magnetic disk; a magnetic head which includes first and second read sensors; a suspension which supports the magnetic head relative to the magnetic disk; and read circuitry which includes a preamplifier. The preamplifier has a first input port coupled to the first read sensor; a second input port coupled to the second read sensor; a first bias source coupled to the first input port for actively current/voltage biasing the first read sensor; a second bias source coupled to the second input port for zero biasing the second read sensor; and a subtractor having first and second inputs coupled to the first and the second input ports, respectively. The first input of the subtractor is provided with a first signal which includes a read sensor data signal and an interference signal, whereas the second input of the subtractor is provided with a second signal which includes the interference signal but not the read sensor data signal.

Abstract: A magnetic disk drive apparatus includes a magnetic disk with a data region, a magnetic head located in a region of the magnetic disk other than the data region or outside of the magnetic disk before startup of the magnetic disk and loaded on the data region after the startup, and a current supply unit for providing, just after the startup, a dummy write current with a current value lower than a normal write current value to the magnetic head located in the region of the magnetic disk other than the data region or outside of the magnetic disk.

Abstract: A magnetic storage system includes a read element including a tunneling giant magneto-resistive (TGMR) sensor. A shunting device includes a control terminal and first and second terminals that communicate with respective first and second terminals of the read element. The shunting device shorts said first and second terminals when said control terminal is not powered to protect the read element from electrostatic discharge. A first voltage limiting circuit limits voltage that is input to first terminals of said shunting device and said read element. Said first voltage limiting circuit includes first and second diodes. An anode of said first diode and a cathode of said second diode communicate with said first terminal of said read element and said first terminal of said shunting device and a cathode of said first diode and an anode of said second diode communicate.

Abstract: An apparatus, method, and system for providing asymmetric signal correction in a HDD system using magneto-resistive (MR) heads for reading information stored thereon. The MR head produces a signal that is asymmetric, and an asymmetric correction circuit corrects the asymmetric signal for further processing. The asymmetric correction circuitry comprises a differential amplifier having a variable gain for producing a current proportional to the asymmetric signal. The differential amplifier is coupled with two high speed switches for producing an output signal having only positive polarity. When the asymmetric correction output signal combines with the input signal, the resultant signal approximates the inverse distortion of the asymmetric input signal.

Abstract: A disk drive includes recording media having one or more recording surfaces, one or more transducer heads positionable relative to the recording surfaces by an actuator operating within a head position servo loop, and a data transfer driver. A preamplifier in the data transfer driver includes one or more head interfaces, each head interface for controlling a transducer head for read and write operations, and a mode controller for controlling each head interface based on configuration information for selectively (i) reading data from at least one recording surface, (ii) writing data to at least one recording surface, and (iii) simultaneously reading data (such as a reference pattern) from at least one recording surface and writing data (such as servo patterns) to at least one recording surface.

Abstract: An apparatus, system, and method are disclosed for measuring magnetoresistive head assembly resistance. A measurement module measures a reference voltage across a reference resistance while applying a reference current to the reference resistance. In addition, the measurement module measures a test voltage across a first biasing resistor, a MR head assembly, and a second biasing resistor connected in series while applying the reference current to the first biasing resistor, the MR head assembly, and the second biasing resistor. A computation module calculates the MR head assembly resistance from the reference voltage, the test voltage, the reference resistance, and the resistances of the first and second biasing resistors.

Abstract: A magnetic recording and reproducing apparatus includes a separator and first and second amplifiers. The separator separates a servo data signal and a user data signal, both reproduced by a reproducing head. The first and second amplifiers are connected to the output stage of the separator to increase the amplitude ratio of the servo data signal to the user data signal. The magnetic recording and reproducing apparatus can precisely decode the servo data along with the user data, and can achieve a highly precise servo control.

Abstract: User data is read from a medium having servo data and user data encoded thereon. The user data is read with a read/write head that is operable in a write mode and a read mode. Servo data is read in a time window following a transition from write mode to read mode, with a frequency passband that has a first low frequency corner. User data is read from the medium after expiration of the time window, with a frequency passband that has a second low frequency corner that is lower than the first low frequency corner.

Abstract: The present invention achieves technical advantages as an improved Parallel Damping scheme suitable for very-low-supply preamp operation. The improved Parallel Damping Scheme accurately generates a programmable Iw flowing through the write head while compensating for a leakage current path through a Parallel Damping resistor.

Abstract: A demagnetizer for an inductive load having a driver circuit including at least one transistor and a ramp-down voltage source switchably connected to the driver circuit, so that when the ramp-down voltage source is connected to the transistor, it drives the voltage of the transistor below its threshold voltage.

Abstract: An amplifying circuit and method are disclosed for amplifying electrical signals, such as electrical signals generated by the read head of a disk drive. The circuit includes a pair of cross-coupled differential amplifier circuits. Each differential amplifier circuit is asymmetric, including two input transistors of different transistor types. For instance, a first of the two input transistors of each differential amplifier circuit may be a bipolar transistor and a second of the two input transistors may be a field effect transistor. By utilizing asymmetric differential amplifier circuits, a relatively wider operating frequency range is obtained.

Abstract: Method and apparatus for removing residual magnetization in a data transducer, such as a recording head used to write data to a recording medium in a data storage device. A residual magnetization sense circuit senses a residual magnetization of a pole of the data transducer as a result of the application of a data transmission current to the transducer. A demagnetization current generator removes the residual magnetization by supplying the transducer with a demagnetizing current that decreases to a final magnitude in accordance with a selected profile. The demagnetization current preferably comprises a bi-directional, time varying current of selected frequency to the transducer that tapers linearly, exponentially or in a step-wise fashion to the final magnitude. The demagnetization profile is preferably continuously adapted during operation.

Abstract: For use with a servowriter that includes a writer core having a plurality of transistors that route servowriting current in response to a servo write signal, a write transition controller, a method of operating the same and a magnetic disk drive incorporating the controller or the method. In one embodiment, the controller includes: (1) logic circuitry, coupled to the writer core, that selectively blocks the servo write signal based on a state of a write current control signal and (2) current shunt circuitry, coupled to the writer core, that operates concurrently with the logic circuitry selectively to shunt current around the writer core based on the state.

Abstract: An amplifier (70) has a differential input stage (84,86). An output transistor (102) is connected to receive a single ended output developed by transistor 86. First (74) and second (76) current sources are connected to establish respective first and second currents in the input differential transistors (84,86) according to a predetermined ratio. First and second voltages are subtracted from the differential inputs (VM,VP) in respective differential amplifiers (88,90), and the output is derived from the output transistor having a magnitude proportional to an inverse of a product of a square of the reference resistance, a carrier mobility, and an oxide capacitance.

Abstract: The present invention provides a disk storage system with a low error rate, which is suitable for reduction in size. The other end of the signal line, which is connected with a read head at one end, is connected with a head bias circuit to apply a sense current to the read head and a pair of first and second capacitance elements for allowing the read signal element formed by the read head to pass, a loop is provided for amplifying the read signal obtained through the first and second capacitance elements by supplying the read signal to an input terminal of a differential amplifying circuit and for converting the amplified signal into the current by transconductance and providing a positive feedback of the amplified signal to the input terminal of the differential amplifying circuit.

Abstract: A recording system, such as a magnetic or optical recording system, sets input attenuation level setting and variable gain amplifier (VGA) operating region during zero gain start (ZGS) by sharing the ZGS adjustment between attenuator settings and VGS gain setting. Further adjustment is made to attenuator settings and VGS gain setting for each subsequent servo or read sector event. The input attenuation level setting and variable gain amplifier (VGA) operating region are set so as to minimize effects of gain error due to incorrect attenuator setting, and subsequently operate the VGA near the center of its range where the non-linear effects are minimal.

Abstract: A write driver produces balanced voltages across head by using the input write data drive transistors of a slower transistor type (typically PNP) on one half of an H-bridge configuration, while transistors of a faster transistor type (typically NPN) in the other half of the H-bridge configuration are driven indirectly by transistors of the slower type, with a trans-resistance in series with transistors of the faster type. Accordingly, the voltage nodes on either side of the write head are pulled to Vcc and Vee symmetrically. A trans-resistance block (40) uses current sources to pull current from capacitive nodes for faster switching.