Abstract: Systems and methods for improving accuracy of head positioning using existing servo patterns are provided. In one embodiment, a method for improving read head positioning is provided that comprises: writing a series of tracks over a range of read offsets to be calibrated; measuring a set of raw track profiles from the series of tracks; sampling the set of raw track profiles at a series of signal amplitude levels; constructing a reference track profile from the set of sampled track profiles; calculating a set of read offset deltas from each sampled track profile; merging the sets of read offset deltas into a set of average read offset deltas; and converting the set of average read offset deltas into a read offset correction table. A similar method for improving disk write head positioning is also provided which utilizes such a read offset correction table to eventually create write offset correction table.

Abstract: A hard drive write preamplifier includes a first differential pair of PNP BJTs having a first PNP BJT and a second PNP BJT; a first tail current source coupled into emitter of the PNP BJTs of the first differential pair; a second differential pair of NPN BJTs having a first NPN BJT and a second NPN BJT; a second tail current source coupled into the emitters of the NPN BJTs of the second differential pair; wherein a collector of each of the PNP BJTs of the first differential pair are coupled to a corresponding collector the NPN BJTs of the second differential pair; a first shift up PNP BJT having emitter coupled to the collector of a first PNP BJT of the first differential pair; a second shift up PNP BJT having an emitter coupled to the collector of the second PNP BJT of the first differential pair.

Abstract: Systems and techniques to interpret signals on a noisy channel are described. A described technique includes storing a group of signals including a filtered digital signal and one or more previous signals, the filtered digital signal being based on an analog signal; interpreting the filtered digital signal as first discrete values; determining whether the first discrete values are adequately indicated based on a result of the interpreting; initiating a retry mode when the first discrete values are not adequately indicated; producing, in the retry mode, a new signal, the new signal being determined based on an average of at least a portion of the group of signals; interpreting, in the retry mode, the new signal as second discrete values; and determining whether the second discrete values are adequately indicated based on hard decisions indicated by the new signal and hard decisions indicated by the filtered digital signal.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response are described. A described system includes an asymmetry correction circuit configured to receive an analog signal and to compensate for asymmetry in the received analog signal, a signal equalizer configured to receive an input signal responsive to an output of the asymmetry correction circuit and to generate an equalized signal, a discrete time sequence detector operable to examine the equalized signal, and a control circuit operable to provide a coefficient adjustment to the asymmetry correction circuit to affect asymmetry compensation based on an estimate of nonlinearity derived from the equalized signal and multiple reconstructed ideal channel output values. The reconstructed ideal channel output values can be derived from an output of the discrete time sequence detector and correspond to at least two different discrete times.

Abstract: A read head circuit includes a read element configured to read data stored magnetically on a platter and includes first and second terminals. A write element writes data on the platter. A normally-ON transistor includes first, second and control terminals. The first and second terminals of the transistor are connected to a respective one of the first and second terminals of the read element. The control terminal receives a control voltage referenced from a power terminal. The power terminal powers the read element or the write element. Responsive to the control terminal being powered by the power terminal, the normally-ON transistor provides an open circuit between the first terminal of the read element and the second terminal of the read element. Responsive to the control terminal not being powered by the power terminal, the normally-ON transistor shorts the first and second terminals of the read element.

Abstract: A system including a first circuit and a second circuit. The first circuit is configured to (i) select a first portion of a signal based on a first offset, (ii) amplify the first portion of the signal according to a first function, and (iii) scale the amplified first portion based on a first factor to generate a first compensation for asymmetry in the first portion of the signal. The second circuit is configured to (i) select a second portion of the signal based on a second offset, (ii) amplify the second portion according to a second function, and (iii) scale the amplified second portion based on a second factor to generate a second compensation for asymmetry in the second portion of the signal.

Abstract: Various embodiments of the present invention provide systems and methods for signal offset cancellation. For example, a method for error cancellation is disclosed. The method includes: receiving an input signal that includes a second order error component; applying a transfer function to the processed input to reduce the second order error component; and providing an output signal that is the result of applying the transfer function to the input signal.

Abstract: A disk drive is disclosed comprising a plurality of disk surfaces and a plurality of corresponding heads. The disk drive further comprises a preamp including a first integrated circuit coupled to a first plurality of the heads. The first integrated circuit comprises a first read-output for outputting a preamplified read signal, a first write-input for receiving a first write signal, a write-output-passthrough for outputting a passthrough write signal in response to the first write signal, and a read-input-passthrough for receiving a passthrough read signal. The preamp further comprises a second integrated circuit coupled to a second plurality of the heads, wherein the second integrated circuit comprises a second read-output for outputting the passthrough read signal, and a second write-input for receiving the passthrough write signal.

Abstract: In one embodiment, an apparatus includes an amplifier configured to receive an asymmetric signal. Correction control circuitry is configured to control gain control circuitry based on the asymmetrical signal to adjust a gain of the amplifier to correct the asymmetric signal. A first adjustment of the gain control circuitry is performed during a first interval and a second adjustment of the gain control circuitry is performed during a second interval to correct the asymmetric signal.

Abstract: A device for setting a bias for a magneto-resistive (MR) head can include a counter configured to provide a count value that varies incrementally from a first count value to a maximum count value. Logic is configured to determine at least one of whether the bias for the MR head has reached a predetermined threshold and whether the counter has reached the maximum count value. The logic provides a bias output signal corresponding to the count value for setting the bias of the MR head according to the determination by the logic.

Abstract: Various systems and methods for reducing cross coupling in proximate signals are disclosed. As one example, a system for reducing cross-coupling in adjacent signals that includes an active slew rate limiter circuit is disclosed. The active slew rate limiter circuit is operable to receive an input signal, and to provide an output signal based on the input signal with a controlled slew rate. In some cases, such systems may be included within a storage device that includes a read head. In such cases, the systems may operate to assure a substantially constant power dissipation within the read head.

Abstract: The invention provides a driving circuit for a voice coil motor. In one embodiment, the driving circuit includes a logic circuit, a digital-to-analog converter, and an output circuit. The logic circuit generates a series of samples of a digital output signal according to a digital input signal, wherein the samples of the digital output signal sequentially alter from a first input value of the digital input value to a second input value of the digital input signal according to an alteration pattern determined by a mode selection signal. The digital-to-analog converter converts the digital output signal to an analog output signal. The output circuit generates a driving current signal according to the analog output signal for driving the voice coil motor.

Abstract: A controller includes a control circuit. The control circuit includes a forward path that includes an input and an output, a feedback path coupled to the output and to the input, and a sensor that is between the input and the output. The sensor generates a sensor signal based on an input signal applied to the input. The forward path generates an output signal based on the sensor signal. The output signal is sent along the feedback path to the input of the forward path. The controller also includes a detector that obtains an intermediate signal from the forward path between the input and the output. The detector generates a control signal using the intermediate signal. The forward path includes a control device that limits the output signal to a predetermined value. The detector controls the control device using the control signal.

Abstract: An apparatus including one or more reader circuits, one or more writer circuits, and a loopback channel. The one or more reader circuits may be configured to read data from a magnetic medium. The one or more writer circuits may be configured to write data to the magnetic medium. The loopback channel is coupled between the one or more reader circuits and the one or more writer circuits.

Abstract: A circuit for compensating asymmetry in a waveform of an input signal using a piecewise approximation of a saturation curve, the circuit including a first circuit configured to output a first compensation for a first section of the saturation curve using a first function and a second circuit configured to output a second compensation for a second section of the saturation curve using a second function. The second function is different than the first function. The first compensation and the second compensation provide the piecewise approximation of a region of the saturation curve. The region includes at least the first second and the second section.

Abstract: Systems and techniques to interpret signals on a noisy channel. In general, in one implementation, the technique includes: interpreting an input signal as discrete values, and in response to an inadequate signal, averaging multiple signals to improve interpretation of the input signal. The input signal can be a read signal from a storage medium, such as those found in disk drives. A read channel can include a buffer and an averaging circuit capable of different signal averaging approaches in a retry mode, including making signal averaging decisions based on a signal quality measure. Buffering read signals can be done in alternative locations in the read channel and can involve buffering of many prior read signals and/or buffering of an averaged read signal.

Abstract: A read head circuit includes a read element configured to read data stored magnetically on a platter. The read element includes a first terminal and a second terminal. A normally-ON transistor includes a first terminal, a second terminal and a control terminal. The first terminal is directly connected to the first terminal of the read element. A second terminal is directly connected to the second terminal of the read element. Responsive to the control terminal being powered, the normally-ON transistor provides an open circuit between the first terminal of the read element and the second terminal of the read element. Responsive to the control terminal not being powered, the normally-ON transistor is configured to short the first terminal of the read element to the second terminal of the read element.

Abstract: Various embodiments of the present invention provide systems and methods for acquiring timing and/or gain information. For example, various embodiments of the present invention provide data processing circuits that include a sample splitting circuit, a first averaging circuit, a second averaging circuit and a parameter calculation circuit. The sample splitting circuit receives a data input that includes a series of samples that repeat periodically over at least a first phase and a second phase. The sample splitting circuit divides the series of samples into at least a first sub-stream corresponding to the first phase and a second sub-stream corresponding to the second phase. The first averaging circuit averages values from the first sub-stream to yield a first average, and the second averaging circuit averages values from the second sub-stream to yield a second average. The parameter calculation circuit calculates a parameter value based at least in part on the first average and the second average.

Abstract: Signal correction is performed by determining an offset error based at least in part on a first portion of a signal within a first amplitude range. The offset error is associated with error due to offset in the signal. An signal error, associated with error due to offset and magneto-resistive asymmetry (MRA) in the signal, is determined based at least in part on a second portion of the signal within a second amplitude range; the second amplitude range does not overlap with the first amplitude range. An MRA error is determined by removing the offset error from the signal error and the MRA error is removed from the signal.

Abstract: An apparatus, system, and method are disclosed for measuring magnetoresistive head assembly resistance. A measurement module measures a reference voltage across a reference resistance while applying a reference current to the reference resistance. In addition, the measurement module measures a test voltage across a first biasing resistor, a MR head assembly, and a second biasing resistor connected in series while applying the reference current to the first biasing resistor, the MR head assembly, and the second biasing resistor. A computation module calculates the MR head assembly resistance from the reference voltage, the test voltage, the reference resistance, and the resistances of the first and second biasing resistors.

Abstract: A system and method for providing an interface an interface between a read channel and a disk controller. The interface includes a plurality of differential pair signal lines operable to communicate data and control signals between the read channel and the hard disk controller. The data and control signal lines communicate operations for transferring data between the disk controller and the read channel.

Abstract: The present invention discloses a 3-phase brushless DC motor controller, which comprises: a unit for generating a PWM signal; an ADC for converting a back electromotive force (BEMF) signal from an analog form into a digital form; a synchronization and extraction unit operating in synchronization in part with the PWM signal for extracting the digital BEMF signal to obtain a corresponding ZCP signal; and a unit for judging whether a commutation operation is to be performed according to a change of the corresponding ZCP signal. A wait instruction and a delay instruction help to accurately acquire the digital BEMF signal.

Abstract: A corrector circuit for correcting second harmonic distortions is provided. The corrector circuit includes a transconductance circuit having an input transconductance with a transresistance load for receiving a distorted voltage signal having a second harmonic component. The transconductance circuit is adapted to generate a corrected voltage signal having the second harmonic component that is reduced from the distorted voltage signal as a function of the input transconductance. The corrector circuit further includes biasing means for providing a biasing current to the transconductance circuit (with the input transconductance that depends on the biasing current). The biasing means includes means for providing a fixed component of the biasing current, means for providing a variable component of the biasing current (being a function of the distorted voltage signal according to a proportionality coefficient) and means for programming the proportionality coefficient.

Abstract: A communications circuit includes a first filter having a corner frequency that is adjustable. A data type identifier that tracks first and second types of data flowing through the communications circuit. A control module that adjusts the corner frequency of the first filter to provide alternating current (AC) coupling during the first type of data and adjusts the corner frequency of the first filter to provide direct current (DC) coupling during the second type of data.

Abstract: Embodiments of the present invention help to efficiently determine the appropriate setting of the write current of a magnetic head relative to temperature. According to one embodiment, a test computer determines the set value of a write current as a function of temperature for each head device portion from the relationship between a write current and an error rate. A test execution controller sets a selected head device portion and a write current to an AE, and writes data on a magnetic disk using the components in a HDD. The test execution controller reads the written data, and the error rate of the data from an error correcting section. The test execution controller repeats the same process with the write current varied. Upon completion of the measurement at the preset write currents, the test execution controller transfers the measurement data to the test computer.

Abstract: Resistivity sense bias circuits are described herein. An example resistivity sense bias circuit for use with a magnetoresistive read head includes a current biasing portion configured to provide a bias current across the magnetoresistive read head thereby establishing a bias voltage across the magnetoresistive read head, a resistivity sensing portion coupled to the current biasing portion and configured to sense a change in the bias current based on a resistivity change of the magnetoresistive read head, and a voltage source to provide the bias voltage and to adjust the bias voltage in response to the resistivity change of the magnetoresistive read head.

Abstract: A method and apparatus for writing magnetization states in magnetic layers of a multi-layer continuous magnetic recording medium with more than two recording levels and a method and apparatus for reading readback pulse shapes representing a magnetization state transition between such written magnetization states. Writing each magnetization state includes selecting the magnetization state, determining a write current sufficient to write the magnetization state, and applying the write current to a magnetic write head to write the magnetization state, including simultaneously writing associated magnetic states in each magnetic layer of at least one pair of magnetic layers. A readback pulse shape representing a written magnetization state transition is read. The written magnetization state transition is uniquely identified from the readback pulse shape of the transition or from both the readback pulse shape of the transition and the readback pulse shape of one or more contiguous magnetization state transitions.

Abstract: An amplifier amplifies, according to a first gain value, a first input signal acquired by reproducing first information from first areas having the first information recorded therein area by area in order. The amplifier also amplifies, according to a second gain value, a second input signal acquired by reproducing second information pursuant to reproduction of the first information, from a second area adjacent to the first area and that has the second information recorded at a recording level different from that of the first information. When the first input signal is amplified, a first gain value following a change in the first signal is calculated so that the level of the amplified signal becomes constant. When the second input signal is amplified, a second gain value following a change in the first gain value is calculated so that the level of the amplified signal becomes constant.

Abstract: A head of a hard disc device is retracted to a predetermined position by operating a VCM (Voice Coil Motor) driver. Trouble in a hard disc is detected and retraction is performed even if a short circuit occurs in either of the output line of a VCM driver in an input end of a high potential side or in an input end of a low potential side. A ground short circuit is detected in each side separately and different retracting methods are executed for each case.

Abstract: Aspects of the present embodiment are related to a power supply voltage supply circuit and the disk apparatus that are capable of reducing power consumption in data writing and reading. The power supply voltage supply circuit includes a data processing unit writing data onto a disk medium and/or reading data from the disk medium=having a plurality of zones assigned a cylinder number, a data input-output unit transmitting data to the data processing unit at a transfer rate in accordance with the zones, a power supply voltage supply unit supplying a voltage to the data input-output unit and a control unit controlling the power supply voltage supply unit in order to supply the voltage in accordance with the transfer rate.

Abstract: A signal conversion circuit includes: an input circuit that rejects common mode inputs and is configured to receive a differential input signal and shift a first bias of the differential input signal to produce a single ended intermediate signal with a second bias; and an amplifier circuit configured to amplify the single ended intermediate signal to produce an amplified signal. The input circuit can include: first and second transistors with drains configured to couple with a supply voltage, and gates of the first transistor and the second transistor are configured to receive the differential input signal; a first resistor coupled to a source of the first transistor and a drain of a third transistor; and a second resistor coupled to a source of the second transistor and a drain of a fourth transistor; where the third transistor and the fourth transistor are connected in a current mirror configuration.

Abstract: Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers are disclosed. A timer in a hard disk drive preamplifier comprises a first switch to selectively store charge in a storage device based on an input signal, the storage device receiving a first current and storing the charge to cause the storage device to have a first voltage that increases at a first rate; a compensation device to cause the first voltage to be substantially equal to a second voltage after a predetermined time period; and a trigger to output a signal when the first voltage is substantially equal to the second voltage, the predetermined time period controlling a transition time between a first hard disk drive operating condition and a second hard disk drive operating condition different than the first operating condition.

Abstract: Systems and techniques relating to interpreting signals on a channel having an asymmetrical signal amplitude response. A signal processor, such as a read channel transceiver device usable in a magnetic recording system, includes an asymmetry correction circuit configured to receive an analog signal and to compensate for asymmetry in the received analog signal, a signal equalizer configured to receive an input signal responsive to an output of the asymmetry correction circuit and to generate an equalized signal, a discrete time sequence detector operable to examine the equalized signal, and a control circuit that provides a coefficient adjustment to the asymmetry correction circuit to affect the asymmetry compensation based on an estimate of non-linearity derived from the equalized signal and an output of the discrete time sequence detector. The estimate can be a least mean squared estimate of the non-linearity in the equalized signal.

Abstract: A method of setting up a pre-amplifier for a hard disk drive and a hard disk drive incorporating the method. A serial interfacing mode of the pre-amplifier is checked by writing and reading data to/from the pre-amplifier. A chip ID of the pre-amplifier is checked and a vendor of the pre-amplifier is identified using the chip ID. Default values of the pre-amplifier stored in a ROM and adaptive codes of the pre-amplifier are automatically downloaded to a register of a hard-disk controller, simplifying the pre-amplifier installation and reducing errors which may occur during manual installation of the pre-amplifier.

Abstract: A method for providing feedback current cancellation comprises providing an amplifier with an input, an output, and at least one stage, feeding back a first current based on the output of the amplifier to the input of the amplifier, and substantially cancelling the first current by supplying a second current to the input of the amplifier.

Abstract: A write driver circuit includes a first write driver that communicates with a first node of a write head. A first feedback path communicates with a control input and an output of the first write driver. The first feedback path includes a first resistance connected between the output of the first write driver and the control input of the first write driver. A second write driver communicates with a second node of the write head. A second feedback path communicates with a control input and an output of the second write driver. The second feedback path includes a second resistance connected between the output of the second write driver and the control input of the second write driver.

Abstract: A system comprises a read element, a first differential amplifier, and a second differential amplifier including inputs that communicate with outputs of the first differential amplifier. First and second resistances communicate with the inputs of the first differential amplifier, respectively, and communicate with the outputs of the first differential amplifier, respectively. First and second capacitances communicate with the inputs of the first differential amplifier, respectively. Third and fourth resistances communicate with the first and second capacitances and with the magneto-resistive read element, respectively, and communicate with the outputs of the second differential amplifier, respectively.

Abstract: A data storage drive comprises a storage disk, a read/write head, and signal processing circuitry in signal communication with the read/write head. The read/write head is operative to read data from and write data to the storage disk at a plurality of data transfer rates. Moreover, the signal processing circuitry is powered by a variable power source. The variable power source varies supply voltage to the signal processing circuitry as a function of a current one of the data transfer rates of the read/write head. Power consumption is reduced in this manner.

Abstract: A system includes N channels and a control module. Each of the N channels includes a latch and a signal generator module, where N is an integer greater than 1. The latch selectively latches a B-bit codeword, where B is an integer greater than 1. The signal generator module generates a signal based on the B bit codeword. The control module transmits the B-bit codeword via a B-bit data bus to the latch of each of the N channels. The control module generates control signals that select the latch in at least one of the N channels.

Abstract: A sample and hold circuit is disclosed that provides longer hold times. An analog multiplexer circuit is also disclosed that exhibits low switch leakage. The analog multiplexer circuit comprises a shared node, a plurality of input circuits, a control input for selecting one or more of the plurality of input circuits, and an amplifier coupled to the shared node. Each input circuit comprises an input node, a primary input switch for selectively coupling an input to the input node, and a secondary input switch for selectively coupling the input node to the shared node, wherein the secondary input switch comprises one or more transistor switches. The parasitic drain and source diodes of one or more transistor switches in secondary input switch in a selected input circuit are coupled to a voltage that is distinct from an input signal of the selected input circuit.

Abstract: Apparatuses, circuitry, architectures, systems, methods, algorithms and software for performing automatic gain calibration on an input signal. The apparatuses and/or circuits generally include an amplifier, a filter, a comparator, and a controller. The amplifier is configured to receive a gain level signal and to amplify the input signal in accordance with the gain level signal to produce an amplified signal. The filter is configured to filter the amplified signal to produce a filtered signal. The comparator is configured to compare the filtered output to a threshold value and to produce a comparison signal in response thereto. The controller is configured to iteratively reset the filter and adjust the gain level signal in response to the comparison signal to select a gain level.

Abstract: A head IC, which adjusts an amplitude level of a read signal of a head, for outputting to a read channel having an AGC amplifier, includes: a differential amplifier; an AGC circuit; external gain setting sections; and a switch. Since the AGC amplifier is disposed in the head IC, the amplitude from the head is automatically adjusted in the head IC, and the signal level, which enters the input dynamic range of the AGC amplifier of the read channel, can be adjusted. The AGC amplifier can be operated as a fixed gain amplifier using a gain value which is set from the outside, so the power consumption can be minimized even if automatic adjustment is performed.

Abstract: Methods and apparatus for temperature compensation for hard disk drive writer overshoot current are disclosed. A disclosed system comprises creating a first delay based on the temperature of the hard disk drive, creating a second delay based on the temperature of the hard disk drive, and creating a pulse based on the first and second delay.

Abstract: A read head circuit comprises a read element including first and second terminals. A shunting device comprises a transistor including a first terminal that is connected to the first terminal of the read element, a second terminal that is connected to the second terminal of the read element, and a control terminal. The shunting device shorts the first and second terminals when the control terminal is not powered.

Abstract: A head IC adjusts an amplitude level of head read signals with regard to scattering in head output characteristics, so as to conform to the input dynamic range of the read channel AGC. An AGC amplifier is provided in a head IC connected to a read channel, and the feedback response speed of the AGC circuit of the head IC is set to be substantially slower than the feedback response speed of the AGC circuit of the read channel. Within the head IC, the amplitude of signals from the head is automatically adjusted, enabling adjustment of the input signal level to the input dynamic range of the AGC amplifier of the read channel. The AGC circuit of the head IC has no effect on the faster AGC operation of the AGC circuit of the read channel.

Abstract: The present invention provides a VCM driver realizing low power consumption and high accuracy and a PWM amplifier compensating a dead time distortion. A phase compensator, a ?? modulator receiving an output signal of the phase compensator and converting the output signal to a control code of predetermined bits, a PWM modulator receiving the control code to produce a PWM signal, and an output circuit receiving the PWM signal to drive a voice coil constitute a forward path. A sense amplifier sensing a current of the voice coil, an ADC receiving an output signal of the sense amplifier, a low-pass filter receiving an output signal of the ADC, and a decimation filter receiving an output signal of the low-pass filter constitute a feedback path. An output signal of the decimation filter is fed back to the input side of the phase compensator to form a major feedback loop having a first-order characteristic loop gain.

Abstract: A head IC adjusts an amplitude level of a read signal of a head and outputs the adjusted signal to a read channel having an AGC amplifier. A head IC includes: a differential amplifier; an AGC circuit; external gain setting sections; and a switch. The AGC amplifier is disposed in the head IC, and the amplitude from the head is automatically adjusted in the head IC. The signal level can be adjusted within the input dynamic range of the AGC amplifier of the read channel. An estimated gain value converted from a result of measuring a resistance value of the head is used as an initial value for the adjustment of the AGC amplifier. It becomes possible attempting to prevent an increase in the lock-in times of the AGC, to guarantee stability, and to prevent judgment errors of the AGC.

Abstract: A difference value between a gain control value when a head comes into contact with a recording medium and a gain control value when the head floats with respect to the recording medium by a target floating amount is stored in advance. When the information access device is actually operated, supply power to a heater is adjusted to once bring the head into contact with the recording medium, a first gain control value adjusted by a gain control section when the head comes into contact with the recording medium is obtained, a second gain control value to be adjusted by the gain control section when the head floats from the recording medium by the target floating amount is obtained from the first gain control value and the difference value, and the supply power to the heater is adjusted such that the second gain control value is supplied to a gain variable amplifier by the gain control section.

Abstract: A biasing device for a magneto-resistive element, including a first bias supply circuit coupled to the magneto-resistive element; and a first bias control circuit coupled to the first bias supply circuit, the first bias control circuit capable of controlling the first bias supply circuit to provide a first calibration mode bias signal during a calibration mode and a first operating mode bias signal during an operating mode, the first operating mode bias signal having a lower noise level than the first calibration mode bias signal.

Abstract: A magnetic recording and reproducing device is a hard disk device which writes information onto a magnetic disk (not shown), or reads information therefrom, and includes: a reproducing head; a recording head; and a magnetic head driving circuit. The magnetic head driving circuit is a circuit, by which driving of the reproducing head and the recording head is controlled, and onto which the reproducing head, a recording head driving circuit, a control unit, and a variable impedance element are integrated. This magnetic head driving circuit is switched on a time division base to a read mode during reproducing operation, and to a write mode during recording operation. The control unit reduces the impedance of the variable impedance element during the write mode.