Abstract: A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier (SCR) that is electrically coupled to the output of a power amplifier; an ESD detection circuit that triggers the SCR responsive to detect an electrostatic discharge on an ESD bus; and an ESD clamp circuit that is coupled to the first voltage line.

Abstract: In one embodiment, a circuit protection device includes a common mode noise filter having a plurality of sheets, each of the sheets being formed to optionally include a coil pattern, an internal electrode, a hole filled with a conductive material, and a hole filled with a magnetic material; and an electrostatic discharge (ESD) protection device having a plurality of sheets, each of the sheets being formed to optionally include an internal electrode and a hole filled with an ESD protection material.

Abstract: In one embodiment, a system includes a cable comprising a plurality of leads and an ESD dissipating adhesive coupled to the plurality of leads in a coverage area for providing ESD protection to an element of an electronic device. The ESD adhesive comprises a mixture of a polymeric thin film and electrically conductive fillers dispersed in the film, and the ESD adhesive has a resistivity from about 50 to 100 M?. In another embodiment, a method for providing ESD protection to an element of an electronic device includes applying an ESD adhesive across exposed leads of a cable and evaporating the solvent from the ESD adhesive. At least some of the leads are coupled to an element of an electronic device. The ESD adhesive comprises a polymeric thin film, electrically conductive fillers dispersed in the polymeric thin film, and a solvent for controlling a viscosity of the ESD adhesive.

Abstract: It is desired to achieve a high ESD protection performance by a small area circuit. An electrostatic discharge protection circuit includes: protection circuits, wherein each protection circuit includes a MOS transistor; and a trigger circuit configured to supply a trigger signal to a gate electrode of the MOS transistor of each protection circuit in response to a surge voltage between a low potential node and a high potential node. Each protection circuit is configured to electrically connect the low potential node and the high potential node to one another when the trigger signal is supplied to the gate electrode. The gate electrode of each protection circuit is connected to a resistive element having larger resistance value than Rmax, supposing that Rmax is a largest parasitic resistance between each of the plurality of protection circuit and an output of the trigger circuit.

Abstract: A protecting unit having a function of thermal energy guiding comprises a body electrically connected to a first lead-out electrode and a second lead-out electrode; the body being wrapped in a packing material; a thermal energy guider disposed on the body adopting a continuous leading wire; one end of the leading wire being disposed on the first lead-out electrode, and the other end thereof being outward extended from the packing material. Thereby, the thermal energy guider utilizes thermal conduction to guide thermal energy in/out of the body so as to prevent electronic appliances from overloading and avert danger.

Abstract: A device for protecting a radio frequency transmission line from transient voltages includes an inner conductor for transmitting communication signals of a desired frequency band and a grounded, coaxial outer conductor electrically insulated from the inner conductor by a pair of annular insulators. As one feature of the invention, a tap conductor for discharging transient voltages carried by the inner conductor that fall outside the desired frequency band is coupled at one end to the inner conductor through a press-fit connection. As another feature of the invention, a pair of high-quality contacts are mounted onto opposite ends of the outer conductor and serve, together with the inner conductor, as the only electrical contact surfaces for the protective device that transmit the desired communication signals. As another feature of the invention, each insulator has a constant outer diameter along the entirety of its length and a variable inner diameter.

Abstract: An overvoltage protection element with a housing, at least one overvoltage limiting component in the housing, especially a varistor, and two connecting elements for electrically connecting the overvoltage protection element to a current or signal path in a normal state, the connecting elements being in electrically conductive contact with a respective pole of the overvoltage limiting component. In the normal state of the overvoltage protection element, at least one pole is connected to a connecting element via a plug-and-socket connection, and at least one spring is located between the housing and the overvoltage limiting component such that, when the overvoltage limiting component is thermally overloaded, it is turned by the spring separating the at least one pole from the assigned connecting element, and creating a thermally separating connection between the overvoltage limiting component and the housing when the temperature of the overvoltage limiting component exceeds a given boundary temperature.

Abstract: The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly to a band-pass structure electrostatic discharge protection circuit. An ESD protection circuit is disposed at the input of a radio frequency (RF) core circuit. The ESD protection circuit comprises a plurality of diodes and inductors constructing a plurality of discharging paths, wherein the diodes and inductors forms a band-pass filter structure. Such that, the RF core circuit with the ESD protection circuit of the present invention feature much higher ESD robustness and better RF performance than the conventional design.

Abstract: A PCB strip and a method of manufacturing an electronic component embedded printed circuit board are disclosed. The PCB strip in accordance with an embodiment of the present invention includes a unit area, which has a plurality of substrate units provided therein, and a dummy area, which is provided on an outer side of the unit area. Here, an electronic component can be embedded in the substrate unit, and an electrostatic discharge preventing component for protecting the electronic component from an electrostatic discharge can be embedded in the dummy area.

Abstract: An electrostatic discharge protection circuit is located between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first semiconductor switch and a second semiconductor switch. The first semiconductor switch is electrically connected to the first voltage terminal. If a voltage at the first voltage terminal complies with a starting condition, the first semiconductor switch is turned on, so that an electrostatic discharge current flows through the first voltage terminal and the first semiconductor switch. The second semiconductor switch is electrically connected between the first semiconductor switch and the second voltage terminal, wherein the electrostatic discharge current from the first semiconductor switch passes to the second voltage terminal through the second semiconductor switch.

Abstract: A semiconductor die includes a substrate comprising a first layer of a first wide band gap semiconductor material having a first conductivity, a second layer of a second wide band gap semiconductor material having a second conductivity different from the first conductivity, in electrical contact with the first layer, a third layer of a third wide band gap semiconductor material having a third conductivity different from the first conductivity and second conductivity, in electrical contact with the second layer, a fourth layer of a fourth wide band gap semiconductor material having the second conductivity, in electrical contact with the third layer, and a fifth layer of a fifth wide band gap semiconductor material having the first conductivity and in electrical contact with the fourth layer, wherein the first layer, the second layer, the third layer, the fourth layer, and the fifth layer are sequentially arranged to form a structure.

Abstract: An apparatus for protecting equipment connected to a high voltage direct current line comprises a current valve having at least one semiconductor device and a rectifying member connected in anti-parallel therewith. A surge arrester is configured to connect said current valve to said line, and a control unit is configured to control the current valve to conduct for draining current from the line to ground.

Abstract: The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

Abstract: An overvoltage protection circuit may include a reference voltage generator, a trigger circuit, and a clamping device. The reference voltage generator is for providing a reference voltage that is relatively constant during a powered EOS/ESD event. The trigger circuit is coupled to receive the reference voltage and a power supply voltage. The trigger circuit is for comparing the reference voltage to the power supply voltage. In response to detecting that the power supply voltage is above the reference voltage, the trigger circuit provides a trigger signal having a voltage proportional to a voltage level of the overvoltage event. The clamping device is coupled between a first power supply terminal and a second power supply terminal. The clamping device is for providing a current path between the first and second power supply terminals in response to the trigger signal.

Abstract: In one embodiment, a wind-power generating system 10 includes: a lightning protecting device including a receptor 70 provided on a blade surface and a lightning conductor 73 grounding the receptor 70; an airflow generating device 60 provided on the blade surface and including first and second electrodes 61, 62 separated via a dielectric 63; a discharge power source 65 including switches 90, 91 able to connect the first and second electrodes 61, 62 to output terminals 84, 85 respectively and a switch 92 able to connect the first or second electrode 61, 62 to a grounding conductor 100; and a thundercloud detecting device detecting information regarding thundercloud approach. When the information regarding the thundercloud approach is detected, the second electrode 62 is connected to the grounding conductor 100 and the first and second electrodes 61, 62 are disconnected from the output terminals 84, 85.

Abstract: A system to interface analog-to-digital converters to inputs with arbitrary common-modes includes a common-mode voltage amplifier circuit and a PGA circuit connected to the common-mode voltage amplifier circuit. The common-mode voltage amplifier and PGA circuits receive first and second analog input signals. The PGA circuit eliminates the arbitrary common-modes from the first and second analog input signals based on an output of the common-mode voltage amplifier circuit.

Abstract: A tunable coaxial surge arrestor includes an inner conductor within a bore of an outer body of the coaxial surge arrestor. An inner end of a stub is coupled with the inner conductor. The stub is also coupled with the outer body at a selectable location along the length of the stub.

Abstract: In an active clamp implemented in a 5V complementary BiCMOS process, the footprint of the active clamp, which includes at least one NMOS clamp stack, is reduced by introducing a BJT into the circuit to allow the number of NMOS clamp stacks to be reduced.

Abstract: In accordance with the disclosed subject matter herein, an apparatus for suppressing in a split-phase power system, effects of line-to-ground transient voltage spikes, balancing phase voltage with respect to ground, filtering phase voltage harmonics, cleaning up electrical noise in a split-phase power system, redirecting energy and absorbing electrical noise, protecting or replacing typical TVSS (transient voltage surge suppressor) units. The apparatus of the present invention can not be damaged by electrical noise. It uses virtually no energy in monitor mode and cannot draw over 3 amps. The apparatus of the present invention can be applied to single-phase lines from center tapped delta power transformers. In some embodiments of the disclosed subject matter, an apparatus for use with a power supply bus having at least a first power line and a second power line.

Abstract: The present invention provides a power supply (200) comprising a ground terminal (110, 320), means (102, 104, 240, 242) for receiving and transmitting a telecommunications signal from/to at least one telecommunications device and means (100) for protecting the telecommunications device from a surge by shunting the surge to the ground terminal (110, 320).

Abstract: There is described a protection apparatus against electrostatic discharges for an integrated circuit; said integrated circuit comprises a radiofrequency or higher frequencies internal circuit. The internal circuit has a first and a second terminals for the output or the input of a radiofrequency or higher frequencies signal. The apparatus comprises first means for electrically connecting said first and second terminals of the internal circuit to at least a PAD and the integrated circuit comprises at least a first and a second supply circuital lines and at least a first and a second protection devices against electrostatic discharges connected to said first and second supply lines. First means have a resistive component and each of said first and second protection devices against the electrostatic discharges have a parasitic capacitive component.

Abstract: An electrostatic discharge (ESD) clamp, coupled across input-output (I/O) and common (GND) terminals of a protected semiconductor device or integrated circuit is provided. One ESD clamp comprises an ESD transistor (ESDT) with source-drain coupled between the GND and I/O terminals, a first resistor coupled between the gate and source and a second resistor coupled between the ESDT body and source. Paralleling the resistors are control transistors with gates coupled to one or more bias supplies Vb, Vb?. The main power rail (Vdd) of the device or IC is a convenient source for Vb, Vb?. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events.

Abstract: Apparatuses and methods for protecting electronic circuits are disclosed. In one embodiment, an apparatus for providing protection from transient signals comprises an integrated circuit, a pad on a surface of the integrated circuit, and a configurable protection circuit within the integrated circuit. The configurable protection circuit is electrically connected to the pad. The configurable protection circuit comprises a plurality of subcircuits arranged in a cascade, and selection of one or more of the plurality of the subcircuits for operation determines at least one of a holding voltage or a trigger voltage of the configurable protection circuit.

Abstract: A switching power supply includes: a first switch provided between a positive terminal of a DC power supply and a positive terminal of a load; a second switch connected in parallel with the first switch; a first capacitor provided between the second switch and a node of the first switch on a DC power supply side; a first inductor provided between the first capacitor and the positive terminal of the DC power supply; and a control circuit that turns off the second switch after the first switch is turned off and when or before a voltage across the first capacitor becomes zero.

Abstract: Improved ESD protection circuits for RFICs requiring both high voltage and high frequency operation is described. A cascode grounded gate snap-back NFET (GGNFET) combined with a precharge circuit and a diode network results in a positive ESD protection clamp with low capacitance and high turn-on voltage. The positive ESD protection clamp provides ESD protection to an IC during a positive voltage ESD pulse. Exemplary embodiments of a negative ESD protection clamp are disclosed where a bias circuit or a charge pump is used in place of the precharge circuit in a manner that allows the combination of the bias circuit or the charge pump together with a diode network and a cascode grounded gate snap-back NFET to provide protection against negative ESD voltage pulses. The combination of a positive and a negative ESD protection clamp provides ESD protection to an IC during either a positive or a negative voltage ESD pulse.

Abstract: Apparatuses and methods for providing transient electrical event protection are disclosed. In one embodiment, an apparatus comprises a detection and timing circuit, a current amplification circuit, and a clamping circuit. The detection and timing circuit is configured to detect a presence or absence of a transient electrical event at a first node, and to generate a first current for a first duration upon detection of the transient electrical event. The current amplification circuit is configured to receive the first current from the detection and timing circuit and to amplify the first current to generate a second current. The clamping circuit is electrically connected between the first node and a second node and receives the second current for activation. The clamping circuit is configured to activate a low impedance path between the first and second nodes in response to the second current, and to otherwise deactivate the low impedance path.

Abstract: A solid state circuit breaker for disrupting the flow of direct current. A power transistor is used in series with the direct current. The power transistor disrupts the direct current only when it is in an off state. A first optoisolator and a second optoisolator are provided. The second optoisolator selectively alters the power transistor to its off state. The first optoisolator selectively controls the second optoisolator. A threshold resistor is provided through which the direct current passes. The threshold resistor creates a voltage differential. The voltage differential is supplied to the first optoisolator and activates the first optoisolator if the voltage differential is greater than a selected threshold voltage.

Abstract: The disclosed invention reduces an increase in the number of electrostatic discharge protection circuits or the number of electrostatic discharge protection elements due to increases in the number of separations of power voltages and the number of separations of ground voltages. A semiconductor integrated circuit includes first, second, and third operation voltage supply terminals; first, second, and third internal circuits; first, second, and third electrostatic discharge protection circuits; and a coupling midpoint. The first, second, and third internal circuits operate at first, second, and third operation voltages supplied to the first, second, and third operation voltage supply terminals, respectively. The first, second, and third electrostatic discharge protection circuits are coupled between the first, second, and third operation voltage supply terminals and the coupling midpoint, respectively.

Abstract: An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.

Abstract: An overvoltage protection plug is disclosed. The overvoltage protection plug includes a protection plug body formed from a chassis and a housing and defining an interior volume, the protection plug body including an insertion portion and a handle. The overvoltage protection plug further includes a gas tube located within the interior volume, the gas tube electrically connected to metallic leads protruding through the body at the insertion portion. The overvoltage protection plug also includes a grounding plate electrically connected to a ground pin of the gas tube.

Abstract: An EMI noise shielding device applied to a power supply control system includes a first resistor with a terminal electrically coupled to a terminal of a second resistor to form an input terminal, a differential amplifier for receiving a feedback voltage (Vfb) signal containing a noise from the input terminal to perform a first filter process to generate a first node voltage (VA) signal, a signal converter for receiving the first node voltage (VA) signal to perform an analog-to-digital signal conversion process and a second filter process to generate a second node voltage (VB) signal, and a digital control circuit for receiving the second node voltage (VB) signal to perform a determination process and a third filter process to generate a third node voltage (VC) signal. Therefore, the noise signal contained in the feedback voltage (Vfb) signal can be filtered to maintain the normal operation of the power supply control system.

Abstract: Circuit and method for RC power clamp triggered dual SCR ESD protection. In an integrated circuit, a protected pad is coupled to an upper SCR circuit and a lower SCR circuit; and both are coupled to the RC power clamp circuit, which is coupled between the positive voltage supply and the ground voltage supply. A structure for ESD protection is disclosed having a first well of a first conductivity type adjacent to a second well of a second conductivity type, the boundary forming a p-n junction, and a pad contact diffusion region in each well electrically coupled to a pad terminal; additional diffusions are provided proximate to and electrically isolated from the pad contact diffusion regions, the diffusion regions and first and second wells form two SCR devices. These SCR devices are triggered, during an ESD event, by current injected into the respective wells by an RC power clamp circuit.

Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a source region and a drain region. The source region is to be coupled to a low-level voltage. The drain region is disposed apart from the source region and includes a first P-type heavily doped region and at least one first N-type heavily doped region. The first P-type heavily doped region is configured to couple to a pad, and the first N-type heavily doped region is adjacent to the first P-type heavily doped region and floated. An electrostatic discharge protection apparatus is also disclosed herein.

Abstract: An electrical switching array and method uses a programmable multi-channel analog switch with a high voltage T/R switch and voltage limiting circuit for ultrasound image system echo signal multiplexing beamforming receiver frontend circuit.

Abstract: An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad. The ESD protection circuit includes a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage. An inverter includes an input end and an output end. The output end of the inverter is coupled with a gate of the clamp FET. A RC time constant circuit is disposed between the first supply voltage and the second supply voltage. A current mirror includes a first transistor. The current mirror is coupled between the input end of the inverter and the second supply voltage. A circuit is coupled with the input end of the inverter. The circuit is capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current.

Abstract: A DC power tool having an interiorly provided lithium battery element and a charging switch includes a safety protection module to eliminate the risk of circuitry burn-out and other dangers resulting from connecting the power tool to a power supply with unmatched rated voltage and rated current when charging the power tool via use of an adapter.

Abstract: An integrated circuit is disclosed to bypass transients between first and second nodes. The circuit includes a first bypass capacitor implemented as a metal oxide semiconductor (MOS) transistor and coupled to a first node; and a switch coupled to the first bypass capacitor and the second node, the switch preventing leakage current from passing through the first bypass capacitor during power down.

Abstract: The subject of the invention is a device for suppressing very fast transients (1, 1a, 1b), applicable in protecting electric and/or electric power equipment, and especially transformers operating in electric power substations and in wind power plants, connected in the supply network circuit downstream of the circuit breaker and upstream of the protected equipment. The device according to the invention is a component of an induction character (1, 1a, 1b), comprising a high-frequency magnetic core (2) arranged around the current-conducting lead (3). On the magnetic core (2) there is wound at least one winding (4, 4a) with at least one pair of terminals (6) used for connecting at least one damping resistor (7).

Abstract: An output transistor bias generation circuit which applies a bias voltage to one of two NMOS transistors constituting an output circuit having a stack structure, includes diode-connected NMOS transistors provided between an external connection pad connected to an external signal line having a voltage higher than a power supply voltage of an LSI circuit, and the gate of an NMOS transistor, diode-connected NMOS transistors provided between the gate of the NMOS transistor and a ground line, a diode-connected NMOS transistor provided between the power supply line and the gate of the NMOS transistor, and a capacitor-connected NMOS transistor provided between the gate of the NMOS transistor and the ground line.

Abstract: A multiphase current supplying circuit according to the present invention includes a diode bridge, an intervening circuit, an inverter, a control circuit, and a lightning arrester. The diode bridge is connected to a single-phase AC power supply system via the lightning arrester, and performs full-wave rectification on a single-phase AC voltage. The intervening circuit includes a capacitor and an inductor, and is constituted by a choke input type low-pass filter. More specifically, one end of the inductor and one end of the capacitor are connected, output from the diode bridge is received between the other end of the inductor and the other end of the capacitor, and a rectified voltage generated at both ends of the capacitor is output to the inverter.

Abstract: An electronic apparatus includes an electronic component electrically connected to a substrate positioned beneath the electronic component. A member includes a plurality of decoupling capacitors having different voltages, and the decoupling capacitors are electrically connected to the electronic component. A plurality of voltage planes in the member are electrically connected to the decoupling capacitors. The decoupling capacitors, via the voltage planes in the member, provide different voltages to the voltage planes and thus the electronic component.

Abstract: The present invention provides a smoke-free ESD protection structure used in integrated circuit devices. A JFET or n-channel MOS transistor is coupled between an I/O pad, and a transistor and diode, wherein the JFET or n-channel MOS transistor limits the current flowing through the diode and transistor to prevent the integrated circuit device from heating up and catching on fire or smoke during the smoke test. Moreover, the integrated circuit device will not be damaged by the smoke test.

Abstract: The present invention relates to a discharge structure for an overvoltage and/or overcurrent protection, in particular to a discharge structure for an electrostatic discharge (ESD) protection, for an integrated circuit (IC), and to an ESD protection device for an IC comprising such a discharge structure and to a method for making such a structure. The present invention particularly relates to such a discharge structure (50, 52) which comprises at least two discharge paths (40, 80) provided to conduct a current to a terminal (60), whereas substantially all of the discharge paths (40, 80) present substantially the same resistance for the current.

Abstract: A device (1) has a series circuit of submodules with a power semiconductor circuit and an energy accumulator connected in parallel with the power semiconductor circuit. Each submodule is associated with a short circuit device for shorting the submodule. The short circuit device is a vacuum switching tube. The device is cost-effective and at the same time enables safe bridging of a defective submodule.

Abstract: Methods of protecting an electrical device, such as a ballast, from damage due to an inrush current, and devices incorporating such methods, are disclosed. A loss of input power received by the ballast is detected. In response, the ballast is entered into a standby mode. The ballast is able to remain in the standby mode for a standby period of time. The input power is monitored during the standby period of time to measure a start time. Measurement of the start time is triggered by the ballast receiving input power again. The ballast is entered into an active mode when the measured start time exceeds a protection time. The protection time corresponds to an amount of time needed for an inrush current to dissipate following input power again being received by the ballast, protecting the ballast from possible damage due to the inrush current.

Abstract: An embodiment bridgeless power factor correction circuit comprises a first boost converter and a second boost converter connected in parallel. A first switch is coupled between the input of the first boost converter and ground. A second switch is coupled between the input of the second boost converter and ground. Both the first switch and the second switch help to reduce the common mode noise of the bridgeless power factor correction circuit. The bridgeless power factor correction circuit further comprises two surge protection diodes coupled between the inputs of two boost converters and the output of the bridgeless power factor correction circuit.

Abstract: The invention discloses an electrostatic discharge protection circuit suitable for an integrated circuit system. The integrated circuit system includes a first power terminal, a second power terminal, an internal circuit and a reset signal wiring. The electrostatic discharge protection circuit includes a first transistor and a second transistor. The first transistor has a first gate, a first electrode and a second electrode. The first gate is coupled to the first power-source. The first electrode is electrically connected to the second power-source. The second transistor has a second gate, a third electrode and a fourth electrode, which are electrically connected to the second electrode, the first power-source and the reset signal wiring respectively. When the integrated circuit system is under an electrostatic discharge condition, the first and the second transistors are switched on, so as to equalize the voltage level of the reset signal wiring to the voltage level of the first power terminal.

Abstract: A resistance determining system for an over voltage protection (OVP) circuit, includes an external power source, a microcontroller, a digital rheostat and a display unit. The external power source supplies an external voltage to the OVP circuit. The microcontroller stores an over voltage value. The microcontroller is connected to the external power source and configured to detect the external voltage and compare the external voltage with the over voltage value. The digital rheostat is connected to the microcontroller and includes a first rheostat having two connection terminals respectively connected to two first connection ends of the OVP circuit. The microcontroller adjusts the first rheostat to be a first resistance value to activate the OVP circuit when the external voltage is substantially equal to the over voltage value. The display unit is connected to the microcontroller and configured to display the first resistance value.

Abstract: A protection circuit apparatus comprises an electrostatic discharge circuit coupled to an isolation filter. The isolation filter comprises an inductor coupled to a ground-coupled capacitor, the inductor and the capacitor being coupled to the electrostatic discharge circuit. The inductor is also coupled to an electrostatic discharge sensitive device to be protected from an electrostatic discharge event.

Abstract: A semiconductor device has a structure including the first semiconductor region 103 which is provided in the first terminal portion 100 and includes the first n-type impurity region 106, the first resistance region 107 provided at an inner periphery portion of the first n-type impurity region 106 in a plane view, and the first p-type impurity region 108 provided at an inner periphery portion of the first resistance region 107 in the plane view, and the second semiconductor region 104 which is provided in the second terminal portion 101 and includes the second p-type impurity region 109, the second resistance region 110 provided at an inner periphery portion of the second p-type impurity region 109 in the plane view, and the second n-type impurity region 111 provided at an inner periphery portion of the second resistance region 110 in the plane view.