Abstract: A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.

Abstract: A fault protector for an opto-electronic device includes a MOSFET having an integral body-diode. A capacitor is connected between a drain and a gate of the MOSFET, and a resistor is connected between the gate and a source of the MOSFET. The drain of the MOSFET is connectable to a first terminal of an opto-electronic device, and the source of the MOSFET is connectable to a second terminal of the opto-electronic device. The device overcomes problems of previously known techniques by preventing a reverse-bias voltage from exceeding an absolute maximum specified by a manufacturer, and also prevents ESD or other power-related faults from exceeding the maximum forward-bias voltage of the laser diode, while not adding significant resistance or capacitance to the laser diode, thereby not complicating the task of driving the laser diode.

Abstract: A method for operating an electrical power supply network is described. The power supply network has several levels of different voltages. The levels are interconnected by switches. A first switch is made so that the maximum interruptible short-circuit current of the first switch is smaller than the maximum flowing short-circuit current. In the event of failure, a test is made as to whether the short-circuit current presently flowing through the first switch is smaller than the maximum interruptible short-circuit current. The first switch will remain closed if this is not the case, and the first switch will be opened if this is the case.

Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Abstract: A circuit includes a discharge arrangement configured to discharge an electrostatic charge. The discharge arrangement has a discharge state. A first circuit is configured to provide a pulse to the discharge arrangement when the electrostatic charge is sensed. The pulse causes the discharge arrangement to enter the discharge state. A second circuit is configured to maintain the discharge arrangement in the discharge state after the pulse has ended. A third circuit is configured to receive the pulse and to provide a delayed output to the discharge arrangement. The delayed output causes the discharge arrangement to exit the discharge state.

Abstract: A switching regulator includes a power stage for coupling to a load through an inductor. The power stage switches so that the power stage sources positive current to the load through a first transistor of the power stage during some periods and sinks negative current from the load through a second transistor of the power stage during other periods. The switching regulator further includes a protection circuit operable to force the second transistor into an off-state state responsive to the negative current flowing through the inductor exceeding a predetermined negative threshold.

Abstract: A voltage swing decomposition circuit includes first and second clamp circuits and a protection circuit. The first clamp circuit is configured to clamp an output node of the first clamp circuit at a first voltage level when an input node of the voltage swing decomposition circuit has a voltage higher than the first voltage level. The second clamp circuit is configured to clamp an output node of the second clamp circuit at a second voltage level, higher than the first level, when the voltage of the input node is lower than the second voltage level. The protection circuit is coupled to the output nodes of the first and second clamp circuits, and is configured to selectively set an output node of the protection circuit to the first or second voltage level. The first and second clamp circuits are coupled together by the output node of the protection circuit.

Abstract: Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q1, Q2, Q4) in a main ESD current conducting path between a first and a second terminal (T1, T2), and further comprises at least one driving transistor (Q3) connected in parallel to at least one of the ESD current conducting transistors (Q1) and provided for conducting a driving current (Ib2) to one or more of the ESD current conducting transistors (Q3) on occurrence of an ESD event.

Abstract: Power adapters for providing power to accessory devices in refrigerated containers are provided herein. The power adapter comprises a first connector communicatively coupled with a plurality of conductors; a second connector communicatively coupled with two or more of the plurality of conductors; and a shunt communicatively coupled with at least four of the plurality of conductors and configured to provide power to an accessory output in response to the accessory connection being communicatively coupled with an accessory device.

Abstract: A lightning protection circuit includes a first lightning protection branch including at least one transient voltage suppression (TVS) protection element, and a testing element integral to the lightning protection circuit. The testing element is operable to test a functionality of the lightning protection circuit while he lightning protection circuit is installed in an electronic control system. A controller is connected to the testing element, such that the controller receives sensed signals from the testing element.

Abstract: A surge protector, an HVAC unit including the surge protector and a method of testing electrical equipment employing the surge protector is disclosed. In one embodiment, the surge protector includes: (1) a first lead, a second lead and a third lead and (2) a protective network having three surge protection units with one of the three surge protection units coupled between each distinct combination of the first, second and third leads, the protective network configured to provide simultaneous surge protection between each of the distinct combinations.

Abstract: The present invention provides an integrated circuit having a better ESD protection capability and capable of reducing a circuit layout area. The integrated circuit comprises: an internal circuit, a first pad, and at least a first impedance matching unit. The first impedance matching unit is coupled between the internal circuit and the first pad, and the first impedance matching unit comprises: a first switch unit and a first resistance unit. The first switch unit is coupled to the internal circuit, and the first resistance unit is coupled between the first switch unit and the first pad, wherein the first resistance unit has a first terminal and a second terminal. The first terminal is directly electrically connected to the first pad and the second terminal is coupled to the first switch unit.

Abstract: Disclosed is an overvoltage protection circuit which includes a first terminal through which a first voltage is supplied to an internal circuit; a second terminal through which a second voltage is supplied; a rectifier having an input end connected to the first terminal and having an output end; and first-stage to n-th-stage switching elements which are connected in parallel to one another. The first-stage to n-th-stage switching elements have first to n-th controlling ends, respectively. Each of the switching elements has first and second controlled ends connected to the first terminal and the second terminal, respectively. The rectifier is configured to output a control voltage from the output end thereby to cause the first-stage to n-th-stage switching elements to be turned on, in response to receipt of an overvoltage from the first terminal.

Abstract: ESD (electrostatic discharge) protection for radio frequency (RF) couplers included in the same semiconductor package as other integrated circuits, such as integrated circuits having power amplifier (PA) circuitry, is disclosed along with related systems and methods. The disclosed embodiments provide ESD protection for RF couplers within semiconductor packages by including coupler ESD circuitry within an integrated circuit within the semiconductor package and coupling the connection ports of the RF coupler to this coupler ESD circuitry. Further, this coupler ESD circuitry can be implemented using two sets of serially connected diodes so that the signal connected to the coupler ESD circuitry can swing around ground without being clipped by the ESD circuitry. Still further, the ESD diodes can be formed in deep N well structures to improve isolation and to reduce parasitic capacitance associated with the ESD diodes.

Abstract: An electrostatic discharge protection circuit includes an input node coupled to receive an input signal and an output node coupled to output the input signal to an internal circuit. A first inductor is coupled to the input node and to the output node, and a second inductor is coupled to the output node and to a first power supply node through a resistance. A plurality of protection devices are coupled to the first and second inductors and are disposed in parallel with each other.

Abstract: An integrated circuit includes an internal power line, a no-connection (NC) pad, and a switch configured to electrically connect the internal power line with the NC pad to supply a first external voltage to the internal power line through the NC pad in response to a control signal.

Abstract: A protection device includes: a serial element unit that includes a first switching element and a resistive element, one end being connected to a control terminal of a protection-target switching element, the other end being connected to a first voltage line, the protection-target switching element including a first terminal connected to the first voltage line, a second terminal connected to a second voltage line and an inductor unit, and the control terminal, the protection-target switching element switching a conduction state at the normal time to a non-conduction state between the first terminal and the second terminal when an off-voltage is applied to the control terminal; a capacitance provided at the protection-target switching element and has a predetermined capacitance value; and a controller that performs control such that the first switching element is in a conduction state if the protection-target switching element is put into a non-conduction state.

Abstract: An intrinsically safe energy limiting circuit for connection between an upstream DC power source and a downstream electrical load powered from the upstream DC power source, wherein the circuit comprises from upstream to downstream an input to be connected to the DC power source, an electronic current limiter configured to limit a current through the circuit to a maximum value if the current reaches this value, a fuse designed to open at a current value greater than the maximum value, a DC-to-DC converter configured to convert a DC input voltage to a lower nominal DC output voltage, a zener barrier having a zener voltage higher than the DC output voltage, and an output for connection to the electrical load.

Abstract: A load driving device according to an exemplary aspect of the present invention includes: an output transistor coupled between a first power supply line and an output terminal, the output terminal being configured to be coupled with a load; a protection transistor that is provided between a gate of the output transistor and a second power supply line, and brings the output transistor into a conduction state when a polarity of a power supply coupled between the first power supply line and the second power supply line is reversed; and a back gate control circuit that controls the second power supply line and a back gate of the protection transistor to be brought into a conduction state in a standby mode when the polarity of the power supply is normal.

Abstract: A power amplifier (PA) controller semiconductor die and a first radio frequency (RF) PA semiconductor die are disclosed. The PA controller semiconductor die includes a first electro-static discharge (ESD) protection circuit, which ESD protects and provides a first ESD protected signal. The RF PA semiconductor die receives the first ESD protected signal. In one embodiment of the PA controller semiconductor die, the first ESD protected signal is an envelope power supply signal. The PA controller semiconductor die may be a Silicon complementary metal-oxide-semiconductor (CMOS) semiconductor die and the RF PA semiconductor die may be a Gallium Arsenide semiconductor die.

Abstract: In one general aspect, an apparatus can include an input terminal and an overvoltage protection device coupled to the input terminal and configured to receive energy via the input terminal. The overvoltage protection device can have a breakdown voltage at an ambient temperature less than a target maximum operating voltage of a source configured to be received at the input terminal. The apparatus can also include an output terminal coupled to the overvoltage protection device and a load.

Abstract: Methods and apparatus to provide transient event protection for circuits are disclosed. An example apparatus includes a first clamp circuit. The first power circuit provides a first reference voltage. The first clamp circuit directs energy from a signal node to the first power circuit in response to a transient resulting in a voltage at the signal node being lower than a second reference voltage. The apparatus also includes a second clamp circuit. The second clamp circuit includes a transistor. A collector terminal of the transistor is prevented from having a lower voltage than the second reference voltage. A second power circuit provides the second reference voltage, which is lower than the first reference voltage. The second clamp circuit directs energy from the signal node to the second power circuit in response to a transient resulting in the voltage at the signal node being higher than the first reference voltage.

Abstract: Aspects of the invention provide for qualifying a new meter with specific power supply requirements. In one embodiment, aspects of the invention include a system, including: an electric meter having a housing; and a voltage-modifying device connected to the electric meter for modifying a received voltage, such that the electric meter operates in accordance with a predetermined power supply requirement, wherein the voltage-modifying device is located within the electric meter housing or external to the electric meter housing.

Abstract: This document discusses, among other things, systems and methods to provide an internal supply rail with over voltage protection using a host power source, an external power source, and a switch configured to receive indications of host and external power source validity. In an example, the switch can be configured to provide the internal supply rail using the host power source when the indication of host power source validity indicates a valid host power source and the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.

Abstract: A circuit comprises a first conductor, a second conductor, and a first detect and disconnect circuit. The first conductor is coupled to a first power supply voltage terminal. The second conductor is positioned a first predetermined distance from the first conductor. The first detect and disconnect circuit has a first terminal coupled to the second conductor and a second terminal coupled to a second power supply voltage terminal. The first detect and disconnect circuit detects a first electrical property change between the second conductor and the first conductor. In response to detecting the change in the first electrical property, the second conductor is disconnected from the second power supply voltage terminal. A method for manufacturing a semiconductor device comprising the circuit is also provided.

Abstract: The described devices, systems and methods include an electro-static discharge clamp with a latch to prevent false triggering of an electro-static discharge protection circuit in response to fluctuations in a power supply rail.

Abstract: A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.

Abstract: An exemplary ESD protection device is adapted for a high-voltage tolerant I/O circuit and includes a stacked transistor and a gate-grounded transistor e.g., a non-lightly doped drain type gate-grounded transistor. The stacked transistor and the gate-grounded transistor are electrically coupled in parallel between an I/O pad and a grounding voltage of the high-voltage tolerant I/O circuit.

Abstract: An Electrostatic Discharge (ESD) protection circuitry comprises a protection device structure. The protection device structure includes at least one transistor with a gate operably connected to a pad. The at least one transistor turns on upon an ESD event and conducting charge to a substrate. At least one additional transistor with a gate operably connected to the substrate turns on after the at least one transistor upon an ESD protection event.

Abstract: A protective circuit compares at least two different signals and asserts a control node toward respective logic states accordingly. At least one of the signals is derived from a voltage on a power rail within a computer or other device. A switching element passes or isolates an enable signal based on the logic state of the control node, enabling or preventing operation of a power supply, accordingly. Central processing units (CPUs) or other elements are protected against electrically caused damage in the event that a fault is detected by the protective circuit.

Abstract: A Peltier element is provided so that an electrically conductive plate forming a heat absorbing portion is in close proximity to an insulating layer and an electrically conductive plate forming a heat radiating portion is provided in close proximity to an insulating layer. The Peltier element has one end connected to a branch line branched from a power line, and has the other end electrically connected to an electrode plate. Further, the Peltier element receives from the branch line a portion of electric power supplied to a power transistor, and outputs it to the electrode plate. In other words, the Peltier element uses the portion of the electric power supplied to the power transistor, to absorb heat generated by the power transistor and radiate it toward a heat radiating plate.

Abstract: An ESD protection circuit includes a resistive element, a capacitive element, a protecting element, and a controller. The resistive element, the protecting element, and the controller are provided in an element formation layer. At least part of the capacitive element includes an interconnect capacitor provided in a plurality of interconnect layers. When viewed in plan, at least part of a capacitance formation region in which the interconnect capacitor is provided overlaps at least part of an element formation region in which the resistive element, the protecting element, and the controller are provided.

Abstract: A transmission circuit including four transmission component sets for Ethernet is provided. Each transmission component set is coupled between an Ethernet connector and an Ethernet chip and has a protection component set. For each transmission component set, a first capacitor is coupled between first and second transmission lines (TLs), and coupled to the Ethernet connector via the first TL and to the Ethernet chip via the second TL; a second capacitor is coupled between third and fourth TLs, and coupled to the Ethernet connector via the third TL and to the Ethernet chip via the fourth TL; first and second inductors are cascaded and coupled between the first and third TLs; a third inductor is coupled between the second and fourth TLs; and a contact between the first and second inductors is coupled to a ground via a fifth TL.

Abstract: An ESD protection circuit for an RF semiconductor device includes an RF input pad configured to receive an RF input signal having an RF operating frequency for the RF semiconductor device. A first ESD block is coupled between an intermediate node and the first power supply voltage terminal, to direct an ESD pulse of a first polarity toward the first power supply voltage terminal. A second ESD block is coupled between the intermediate node and the second power supply voltage terminal, to direct an ESD pulse of a second, opposite polarity toward the second power supply voltage terminal. A resonance circuit is coupled between the RF input pad and the intermediate node. The resonance circuit is configured to present a greater impedance to the RF input signal having the RF operating frequency than to the ESD pulses.

Abstract: An electrical apparatus, which is immovable in a facility, comprises plural electric circuits. Each electric circuit has one or more resistance elements and is connected to each input terminal connected a power source. The electric circuits are arranged positionally closely with each other. In each electric circuit, a desired functional circuit is connected in series to the resistance element, and a protection circuit is connected in series to the resistance element and connected in parallel with the functional circuit. A discharge member is provided in each electric circuit and arranged between each input terminal and the functional circuit. The discharge member includes a discharge gap which allows the discharge member to face with the discharge member of an adjacently arranged electric circuit. The discharge gap discharge deliberately to the adjacently positioned discharge member when a voltage applied to a selected electric circuit exceeds a predetermined voltage value.

Abstract: An electrostatic protection circuit in a semiconductor device includes a first first-conductivity type well extending in a first direction over a semiconductor substrate, a second first-conductivity type well extending in a second direction over the semiconductor substrate and perpendicular to the first direction with one end coupled to a first long side of the first first-conductivity type well, and a second-conductivity type well formed around the first first-conductivity type well and the second first-conductivity type well. It also includes a first high-concentration second-conductivity type region extending in the second direction on a surface of the second first-conductivity type well and a first high-concentration first-conductivity type region extending in the second direction on a surface of the second-conductivity type well while facing the first high-concentration second-conductivity type region.

Abstract: This document discusses, among other things, systems and methods to provide an internal supply rail with over voltage protection using a host power source, an external power source, and a switch configured to receive indications of host and external power source validity. In an example, the switch can be configured to provide the internal supply rail using the host power source when the indication of host power source validity indicates a valid host power source and the external power source when the indication of host power source validity indicates an invalid host power source and the indication of external power source validity indicates a valid external power source.

Abstract: A target closing phase determining circuit determines energization flux errors in respective phases and respective closing phases of a first phase, and determines a target closing phase of the first phase so as to minimize an evaluated value related to determined energization flux errors in the respective phases. Each of the energization flux errors is the maximum value of absolute values of center values of transformer fluxes generated in a static state after energization. The target closing phase determining circuit determines the energization flux errors based on residual flux values for the first to third phases of a three-phase power supply, respectively, a pre-arc characteristic and a closing time variation characteristic of a three-phase circuit breaker, a connection condition of windings of a three-phase transformer, to which the three-phase circuit breaker is connected, and voltage phase differences among the phases of the three-phase power supply.

Abstract: Certain embodiments of the invention may include systems, methods and apparatus for voltage clamp circuits. According to an example embodiment of the invention, a voltage clamp circuit may include a first circuit portion electrically coupled to the output of at least one power source. The first circuit portion comprises a power semiconductor device having a first, second and a third node and one or more zener diodes electrically coupled to the first or the second node of the power semiconductor device. The voltage clamp circuit may further include a second circuit portion in electrical communication with the first circuit portion, where the second circuit portion comprises a resistor, a capacitor and a directional device, and where the second circuit portion connects to the one or more zener diodes to reduce peak voltage output between the second and the third node of the power semiconductor device.

Abstract: A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.

Abstract: An ESD protection circuit and method for its use are provided. The circuit comprising: a discharge path formed by first and second NMOS transistors which are sequentially connected between a ground and a power supply; an ESD event detection unit; first and second drive units respectively connected between an output of the ESD event detection unit and a gate of the first transistor and between the output of the ESD event detection unit and a gate of the second transistor. The first and second drive units respectively cause the first and second transistors to be turned on during an ESD event and to be turned off when there is no ESD event.

Abstract: A power unit (e.g., inverter module) includes a housing and a switch attached to the housing. The switch may be configured to be electrically coupled to a remotely-mounted drive circuit through two or more wire leads. The power unit also includes a clamping circuit electrically coupled to terminals of the switch and in parallel with the switch. The clamping circuit may be disposed inside the housing or on an outer surface of the housing, and is configured to limit a voltage across the switch.

Abstract: A circuit with an electro-static discharge clamp coupled to a first power source and second power source. The electro-static discharge clamp includes an NMOS stack and an electro-static discharge detector. The NMOS stack has a first NMOS transistor with gate node ng1 and a second NMOS transistor with gate node ng2. The electro-static discharge detector is configured to control the NMOS stack, and may include three switches. A first switch is configured to switch the gate node ng1 to the second power source. A second switch is configured to switch the gate node ng1 to the gate node ng2. A third switch is configured to switch the gate node ng1 to the ground.

Abstract: A robust ESD protection circuit, method and design structure for tolerant and failsafe designs are disclosed. A circuit includes a middle junction control circuit that turns off a top NFET of a stacked NFET electrostatic discharge (ESD) protection circuit during an ESD event.

Abstract: Systems, methods, and apparatus for limiting voltage across a switch utilizing voltage clamping circuitry are provided. The voltage clamping circuitry may include a rectifier circuit comprising inputs and outputs, the inputs in parallel communication across operational circuitry; an electronic active switching device in parallel communication with the outputs of the rectifier circuit; and at least one Zener diode in parallel communication with the electronic active switching device. When voltage across the electronic active switching device and the Zener diode meets or exceeds a predetermined value, the current will flow through the electronic active switching device and limit voltage across the operational circuitry to within a voltage clamping circuitry voltage limit.

Abstract: In a power source of a welding system, an inverter rectifier output circuit and method for reducing the blocking voltages across saturable reactors associated with a rectifier coupled to a transformer winding in the inverter rectifier output circuit during both turn-on and turn-off transitions of the rectifier. At least a portion of a reverse recovery current associated with the rectifier is blocked by allowing blocking voltages to build across associated saturable reactors during a transition phase of the rectifier. During a turn-off portion of the transition phase, the blocking voltages are reduced using a RC circuit, thereby suppressing a peak voltage associated with the rectifier. During a turn-on portion of the transition phase, the blocking voltages are reduced using another saturable reactor in series with a free-wheeling diode.

Abstract: ESD protection circuit including a resistor and at least one protection transistor; the resistor coupled between an I/O signal node and an internal node of internal circuit, the protection transistors serially coupled between the internal node and a voltage node with each protection transistor comprising a gate and a drain which is coupled to the gate.

Abstract: An integrated circuit, comprises a power supply node being connectable to a voltage supply (Vdd); a ground node connectable to ground (GND); and an electrostatic discharge protection structure for diverting an electrostatic discharge away from protected parts of the integrated circuit. A gated domain is present which is supply gated and/or ground gated with respect to the power supply node and/or the ground node, as well as a gating switch for gating the gated domain relative to the power supply node and/or the ground node. The gating switch enables in a connecting state, and in a disconnecting state inhibits, an electrical connection between the gated domain and at least one of: the power supply node and the ground node. The integrated circuit includes ESD gating control circuitry for controlling in case of an electrostatic discharge event the gated domain to be electrically connected to the power supply node and/or the ground node.

Abstract: A trigger circuit detects a transient voltage increase on an integrated circuit. The trigger circuit controls a conductivity state of a clamping device to limit the transient voltage increase. The trigger circuit comprises a common capacitive element having a capacitive value, wherein a first time value and a second time value are dependent upon the capacitive value of the common capacitive element, the first time value applicable to an unpowered state of the integrated circuit and the second time value applicable to a powered state of the integrated circuit. The first time value and the second time value control a trigger circuit parameter which may include a detection range within which a rate of transient voltage increase causes the trigger circuit to become active or an “on” time upon which an active duration of control of the conductivity state of the clamping device depends.

Abstract: Electrostatic discharge (ESD) protection circuit including a first silicon controlled rectifier (SCR) and a trigger circuit; the trigger circuit including a first MOS transistor and a second transistor, triggering the first SCR and providing a second SCR shunt with the first SCR during ESD.