Abstract: A Compact Secondary Substation including a fault protection system and a method for fault protection in Compact Secondary Substations (CSS). The CSS includes a Ring Main Unit (RMU), a transformer and a Low Voltage (LV) switchgear. The CSS includes a number of detectors, which detectors can be placed at least in one of the RMU, the transformer or in the LV switchgear, which detectors can be connected to a control unit, which control unit by fault detection by the detectors can activate a fast operating switch for grounding. By using the fast operating grounding switch and controlling this on the basis of the detectors placed inside the CSS, an active arc fault protection is achieved. The control unit also controls the fast operating grounding switch so that it works as a working grounding switch.

Abstract: A power-to-ground clamp transistor provides electrostatic discharge (ESD) protection. A filter capacitor and resistor generate a filter voltage that is buffered by three stages to drive the gate of the clamp transistor. The filter capacitor is about twenty times smaller than in a conventional clamp circuit. Feedback in the circuit keeps the clamp transistor turned on after the R-C time constant of the capacitor and resistor in the filer has elapsed, allowing for a smaller capacitor to turn on the clamp transistor longer. A sub-threshold-conducting transistor in the first stage conducts only a small sub-threshold current, which extends the discharge time of the first stage. The gate of the sub-threshold-conducting transistor is driven by feedback from the second stage. A feed-forward resistor has a high resistance value to slowly raise the voltage of the second stage from the filter voltage, and thus slowly raise the gate of the sub-threshold-conducting transistor.

Abstract: An electronically-activated roof access hatch is described that allows an operator to unlock the roof access hatch safely from the ground before ascending to the roof access hatch. The opening of the roof access hatch is controlled by a control panel that unlocks the roof access hatch and causes the roof access hatch to open.

Abstract: A conductor arrangement is provided for reducing very fast transients in high voltage applications. The conductor arrangement includes a conductor element having a main conducting orientation, and a conductive annular shell element coaxial to the conductor element, thus forming an annular cavity around the conductor element. The annular shell element in the main conducting orientation includes a first end portion and a second end portion. The first end portion is conductively connected to the conductor element. The second end portion includes an annular collar which is substantially coaxial to the conductor element, thus together with the conductor element forming a coaxial capacitor which has a solid material filling. The capacitor includes a surge arrester which may serve as an energy conversion portion.

Abstract: A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape.

Abstract: The present disclosure generally pertains to surge protection systems that protect outside plant equipment from high-energy surges. In one exemplary embodiment, a protection system is used for protecting Ethernet equipment that is coupled to an outside Ethernet cable. The protection system provides protection and remains capable of coupling signal energy between an Ethernet cable and Ethernet equipment without significantly degrading Ethernet performance. However, the protection system, while allowing the desirable Ethernet signals to pass between the cable and the equipment, prevents the electrical voltages and currents of high-energy surges, such as surges from lightning or AC power faults, from damaging the Ethernet equipment.

Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

Abstract: Disclosed are advances in the arts with novel and useful voltage transient protection circuitry in configurations which include a bridge circuit in combination with one or more voltage reference, load to ground circuit, and/or snub circuit such that the output node is held at a selected voltage level, preferably mid-rail, and potentially damaging transient voltages are avoided.

Abstract: A power supply circuit includes an energy-consuming component including an input terminal, an input over-voltage protection circuit connected to the input terminal, and a feed back circuit. The feedback circuit is connected to the input over-voltage protection circuit and the input terminal of the energy-consuming component. The feedback circuit monitors the voltage on the input terminal, compares the voltage on the input terminal with a reference voltage, and turns off the input over-voltage protection circuit to cut off voltage provided to the input terminal of the energy-consuming component when the voltage on the input terminal is larger than the reference voltage.

Abstract: An ESD protection circuit comprises three transistors and two voltage dividers. The two source/drain terminals of a first transistor are electrically coupled to a first power line and a second power line respectively. The two source/drain terminals of a second transistor are electrically coupled to the first power line and a gate terminal of the first transistor respectively. The two source/drain terminals of a third transistor are electrically coupled to the gate terminal of the first transistor and the second power line respectively. A first voltage divider supplies a first voltage to a gate terminal of the second transistor according to a potential difference between the first power line and the second power line. A second voltage divider supplies a second voltage to a gate terminal of the third transistor according to the potential difference between the first power line and the second power line.

Abstract: A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage. One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts.

Abstract: An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.

Abstract: The present invention describes an electrostatic discharge protection circuit that protects an internal circuit of a semiconductor device from electrostatic discharge. The electrostatic discharge protection circuit includes a first electrostatic protection unit that transfers static electricity as a driving signal and also discharges the static electricity to a first discharge line when the static electricity is generated in a pad. It also includes a second electrostatic protection unit that discharges the static electricity generated in the pad to a second discharge line in response to the driving signal transferred from the first electrostatic protection unit. Since the first electrostatic protection unit performs an electrostatic discharge operation and at the same time aids the driving of the second electrostatic protection unit, electrostatic discharge performance can be enhanced while a layout area of the electrostatic discharge protection circuit can be reduced.

Abstract: An electrical protection assembly for connection between an electrical power supply line and electrical equipment has an insulating mounting structure; a first arm connectable to a live conductor for connection to a fusible device at a first end and a voltage surge protection unit at a second end, pivotally attached to the mounting structure in a displaceable manner intermediate its ends; a first connection arrangement at the first end of the first arm for connection to the fusible device; and a second connection arrangement at the second end of the first arm for connection to the voltage surge protection unit. The assembly further includes first and second springs for urging the first arm relative to the mounting structure. The springs may urge the second connection arrangement towards the voltage surge protection unit and the first connection arrangement away from the fusible device.

Abstract: In some embodiments, a power supply clamp may include a switchable discharge device configured to discharge an electrostatic discharge; and a control circuit configured to generate a control voltage to turn off the discharge device at a shutoff time, with the shutoff time being long enough to allow the electrostatic discharge though the discharge device but short enough to reduce a duration of a power-up current transient through the discharge device. Other embodiments may be described and claimed.

Abstract: A semiconductor device includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one of the semiconductor substrates. In the device, the through electrode is electrically connected with the plurality of electrostatic discharge protection circuits.

Abstract: An ESD protection circuit with multiple domains, which comprises: an ESD protection device, coupled between a first power supplying line and a first ground line; a first internal circuit, having a first terminal coupled to the first power supplying line; a first switch, coupled between a second terminal of the first internal circuit and a second ground line; and a first ESD detection circuit, coupled to the first switch, for detecting an ESD signal, and controls the first switch to be non-conductive when the ESD signal occurs.

Abstract: Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an actively-controlled protection circuit includes a detector, a timer, a current source and a latch. The detector is configured to generate a detection signal when the detector determines that a transient signal satisfies a first signaling condition. The timer is configured to receive the detection signal, and to generate a current control signal. The current control signal is provided to a current source, which produces a trigger current at least partly in response to the control signal. The trigger current is provided to a node of the latch, thereby enhancing the conductivity modulation of the latch and selectively controlling the activation voltage of the latch.

Abstract: A protection circuit is connected between an interface circuit and a main circuit of an electronic device. The interface circuit is for providing a path for a power supply to power the main circuit. The protection circuit includes an electrostatic protection unit and a mis-connect protection unit. The electrostatic protection unit is electrically connected to the interface circuit and the main circuit and is configured for clamping a voltage of a node to a predetermined value, which the node is defined by the interface circuit, the electrostatic protection unit, and the main circuit. The mis-connect protection unit is electrically connected between the node and the main circuit. When the interface circuit is incorrectly connected to the power supply, the mis-connect protection unit disconnects an electrical connection between the power supply and the main circuit.

Abstract: An electromagnetic pulse protection circuit having wave filtering functions, composed of an inductor free slow response protection circuit and a fast response protection circuit, and a filter is series-connected on a signal transmission route, and is utilized to provide impedance in effectively preventing electromagnetic pulses caused by lightning (LS) or other electronic weapon (NEMP, HEMP, PEMP) interferences. In addition, it is capable of suppressing electromagnetic pulses at specific frequencies, thus, raising the capability of electronic elements in resisting against electromagnetic pulses. Furthermore, said filter is made of high-temperature-super-conduction (HTSC) material, so that when said HTSC material of said filter is subject to a sudden infusion or invasion of said electromagnetic pulses, it is switched to a high impedance state in a very short period of time in effectively restricting currents passing through said filter, hereby avoiding the damages of a communication system.

Abstract: An embodiment is a semiconductor device comprising a receiver circuit comprising fin field effect transistors (FinFETs), a transceiver circuit comprising FinFETs, and a transmit bus electrically coupling the receiver circuit and the transceiver circuit, wherein the receiver circuit and the transceiver circuit each further comprises an electrostatic discharge protection circuit comprising planar transistors electrically coupled to the transmit bus. Other embodiments may further comprise a power clamp electrically coupling a first power bus and a first ground bus, a power clamp electrically coupling a second power bus and a second ground bus, or at least two diodes electrically cross-coupling the first ground bus and the second ground bus. Also, the planar transistors of the transceiver circuit and the receiver circuit may each comprise a planar PMOS transistor and a planar NMOS transistor.

Abstract: Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an actively-controlled protection circuit includes a detector, a timer, a current source and a latch. The detector is configured to generate a detection signal when the detector determines that a transient signal satisfies a first signaling condition. The timer is configured to receive the detection signal, and to generate a current control signal. The current control signal is provided to a current source, which produces a trigger current at least partly in response to the control signal. The trigger current is provided to a node of the latch, thereby enhancing the conductivity modulation of the latch and selectively controlling the activation voltage of the latch.

Abstract: A protection circuit 10 provided with a current regulating section 14 with a first end connected to a power source line VDD and a second end connected to an input terminal 116A of an inverter 116. The current regulating section 14 applies a voltage of less than a threshold value voltage to the input terminal 116A when a surge current having predetermined frequency characteristics flows from the first end in a particular flow path, by generating induced electromotive force so as to generate a magnetic field to cancel out the magnetic field occurring due to the surge current, thereby impeding flow of the surge current. The current regulating section 14 applies a voltage of the threshold value voltage or greater to the input terminal 116A when a driving current not having the frequency characteristics flows in from the first end.

Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor including a first drain, a second transistor including a second drain, and a resistor including a first terminal and a second terminal. The first terminal is coupled to the first drain and the second drain. Additionally, the system includes a third transistor coupled to the second terminal and a protected system. The third transistor includes a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a third drain. The protected system includes a fourth transistor, and the fourth transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a fourth drain.

Abstract: A surge protection module comprises a base, a plurality of first pins extending from the base to connect electrically to an upstream circuit, a plurality of second pins extending from the base to connect electrically to a downstream circuit, a fuse device acting between each first pin and a respective one of the second pins, at least one analog arrestor upstream of the fuse devices that is electrically connected across the first pins and in electrical connection to a ground terminal extending from the base, and a low capacitance solid state arrestor arrangement electrically connected to each second pin downstream of the fuse devices and to the ground terminal.

Abstract: Apparatus and methods for integrated circuit protection are provided. In one embodiment, an integrated circuit (IC) includes a first pad, a second pad, a third pad, a first protection subcircuit coupled between the first pad and a common node, a second protection subcircuit coupled between the second pad and the common node, and a third protection subcircuit coupled between the third pad and the common node. The first, second, and third protection subcircuits each include one or more building blocks for maintaining the voltage of each of the pads within a predefined safe range, as well as to maintain the voltage between each of the pads within acceptable limits. A portion of the building blocks used to provide transient signal protection can be shared between pads, thereby reducing the area of the pad protection circuit relative to a scheme using a separate stack of building blocks for each pad.

Abstract: A circuit arrangement for protection against electrostatic discharges comprises an shunt device, which is connected between a first and a second terminal of the circuit arrangement and has a control input, via which the conduction of the shunt device can be controlled. In addition there is a trigger element, which has a trigger output for issuing a trigger signal in dependence on a voltage between the first and the second terminal of the circuit arrangement. The circuit arrangement additionally comprises an interruption unit that can be controlled via a deactivation input by means of a sendable deactivation signal and which is connected on the input side to the trigger output and on the output side to the control input. In addition, a method for shunting electrostatic discharges is shown.

Abstract: Implementations are presented herein that include an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first transistor and a second transistor. The first transistor has a first terminal that is coupled to a first supply line and a bulk that is coupled to a second supply line. The second transistor has a first terminal that is coupled to the second supply line, a bulk that is coupled to the first supply line and a second terminal that is coupled to a second terminal of the first transistor to define a protected node. The ESD protection circuit further includes a current limiting element that has a first terminal that is coupled to the protected node.

Abstract: A semiconductor device includes a substrate on which an electronic circuit is provided. Two or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an aggregate amount of a current flowing between the substrate and said pads. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter.

Abstract: A circuit comprising a first transistor group configured to electrically isolate, at least in part, a second transistor group from an input voltage; the second transistor group configured to provide voltage protection to a third transistor group; and the third transistor group configured to switch on and off.

Abstract: An electrically noisy D.C. power source having high slew rate A.C. transient voltage, is cut off from a capacitive load by a switchable, constant slew rate voltage source, upon the detection of an A.C. transient voltage having a slew rate that would otherwise cause a current overload through the capacitive load or the voltage source, or the D.C. power source.

Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit for suppressing a transient voltage. The transient voltage suppressing (TVS) circuit includes a Zener diode connected between a ground terminal and a node for triggering a snapback circuit. In one embodiment, this node may be a Vcc terminal. The TVS device further includes a snapback circuit connected in parallel to the Zener diode for conducting a transient voltage current with a snapback current-voltage (I-V) characteristic upon turning on of the snapback circuit. And, the TVS device further includes a snapback suppressing circuit connected in series with the snapback circuit for conducting a current with an I-V characteristic complementary to the snapback-IV characteristic for clamping a snapback voltage.

Abstract: Disclosed is an improved electrostatic discharge protection device that can effectively cope with electrostatic stress of a microchip operating at high voltage. The ESD protection device includes at least one gate coupled NMOS (GCNMOS) having a gate connected to a drain via a capacitor disposed between the gate and the drain and connected to a source and a well to pick-up via a resistor, and devices for low or medium voltage operation of 6V or less connected in series to the gate coupled NMOS (GCNMOS).

Abstract: A transient voltage surge suppressor assembly comprising: a first energy absorbing device; a second energy absorbing device in parallel with the first device; and a voltage sense circuit configured to take the first device off-line when a voltage swell lasts for a duration. The first and second devices may be wired in parallel between a line and a neutral. The assembly may include a third energy absorbing device wired between the line and a ground, the third device also being configured to be taken off-line when the voltage swell lasts for the duration. The voltage sense circuit may be powered by a line voltage or a lower supply voltage. The first device may be more sensitive than the second device. For example, the first device may have a lower clamping voltage than the second device. The first device may be smaller and/or include fewer components than the second device.

Abstract: An RCD transient absorption circuit, having a first port and a second port, the RCD transient absorption circuit comprising a first resistor, a capacitor and a diode, wherein: the first resistor is connected in parallel to the capacitor, and resultant parallel connection of which is connected in series to a diode; one end of the resultant parallel connection of the first resistor and the capacitor is connected to a cathode of the diode; another end of resultant parallel connection is the first port of the RCD transient absorption circuit; and the second port of the RCD transient absorption circuit is an anode of the diode; the RCD transient absorption circuit further comprises a power-trimming device connected in parallel to the first resistor and the capacitor.

Abstract: An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, includes an ESD clamp circuit coupled between a VDD power rail node and the VSS power rail node and a LC-tank structure coupled between the VDD power rail node and the VSS power rail node and to the RF I/O pad. The LC-tank structure includes a first ESD block between the VDD power rail node and the RF I/O pad, and a second ESD block between the VSS power rail node and the RF I/O pad. At least one of the first and second ESD blocks includes a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes.

Abstract: In a lamination type semiconductor device, in the case where a power source plane is wrapped by a closed area to prevent the needless radiation from being leaked to the outside of the semiconductor package, a planar conductor for shield having an area intersecting with the respective layers is required. However, in a device for manufacturing the lamination type semiconductor device, a process for manufacturing the above-mentioned conductor cannot be realized ordinarily. In order to make the process possible, it is required to modify or replace a manufacturing apparatus of the semiconductor device, and accordingly a manufacturing cost will be considerably increased. In the present invention, a guard ring is arranged in an surrounding area of a power source plane. The guard ring is connected to a GND plane of another layer through a via. Consequently, the RF radiation occurs between the power source plane and the guard ring.

Abstract: An electrostatic discharge (ESD) protection element is described, the ESD protection element including a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.

Abstract: An electrical circuit comprising a power supply, a load and a surge protection device adapted to protect said load and/or power supply from electrical fast transient events according to the requirements of IEC 61000-4-2 or 4 and which comprises a stress threshold, in which the electrical circuit further comprises a monitoring device adapted to monitor the current in said surge protection device and detect the breaching of said threshold by electrical fast transient events.

Abstract: One embodiment features an electrical circuit comprising: a high-voltage input configured to receive a high voltage into the electrical circuit; a low-voltage input configured to receive a low voltage into the electrical circuit; a thin-oxide circuit comprising a thin-oxide metal-oxide-semiconductor field-effect transistor (MOSFET); and a protection circuit configured to protect the thin-oxide circuit from the high voltage, wherein the protection circuit comprises a thick-oxide MOSFET clamp circuit, and an adaptive voltage reference circuit configured to provide an adaptive reference voltage, wherein the thick-oxide MOSFET clamp circuit is biased by the adaptive reference voltage.

Abstract: Transient blocking unit reset capability is improved by adding one or more transistors in parallel to one of the main blocking transistors of the circuit. These additional transistors switch off at higher voltages than their corresponding main blocking transistor, and have higher on-resistances than their corresponding main blocking transistor. The resulting transient blocking unit characteristic has two or more different slopes in the negative differential resistance part of the circuit I-V characteristic. This piecewise linear behavior can be exploited to ensure that the circuit I-V characteristic only has a single intersection with a normal load characteristic. By satisfying this condition, automatic reset is ensured, because the combination of the transient blocking unit with any load that is consistent with the normal load characteristic will have only one stable operating point.

Abstract: A semiconductor device has: a power supply line; a ground line; a signal line for transmitting a signal; a signal pad connected to the signal line; a protection element connected between the signal line and the ground line; and a trigger circuit configured to supply a trigger current to the protection element. The trigger circuit has: a PMOS transistor whose gate and backgate are connected to the power supply line and whose source is connected to the protection element; and an amplifier circuit part configured to amplify a first current flowing through the PMOS transistor to generate a second current. The trigger current includes the second current.

Abstract: A SCR-based based electrostatic discharge protection device with a shunt path is provided. The shunt path operates at a low resistance when an enabling signal of the shunt path is asserted and a high resistance when the enabling signal is negated. The shunt path connects the cathode and the gate of the silicon-controlled rectifier, and provides a conductive path for displacement current from a parasitic capacitance when the shunt path is enabled, such as when power is provided to the device, and further allows the SCR to enter a low-resistance state when the shunt path is not enabled, such as when power is not provided to the device. A threshold trigger circuit is operably coupled between the anode and the cathode of the silicon-controlled rectifier and is configured to provide a current path when the anode voltage reaches a predetermined value lower than a breakdown voltage of the silicon-controlled rectifier.

Abstract: A circuit comprises an inductive load. The circuit further comprises an energy-absorbing component operably coupled to the inductive load and arranged to absorb energy generated by the inductive load.

Abstract: A transient voltage compensation system is provided. The transient voltage compensation system includes a processor and a first voltage regulator coupled to the processor, wherein the first voltage regulator is to deliver a load current to the processor at an output voltage. The transient voltage compensation system also includes a second voltage regulator coupled to the first voltage regulator, wherein the second voltage regulator is to regulate the output voltage in response to transient loads of the processor.

Abstract: An electrostatic discharge (ESD) clamp circuit is provided. The ESD clamp circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a third transistor. A clamp device of the ESD clamp circuit is implemented by the third transistor. A parasitic capacitor of the third transistor forms a detection scheme along with the second resistor to detect the ESD. The first resistor, the second resistor, the first transistor, and the second transistor form a feedback scheme to control the third transistor for discharging the ESD current.

Abstract: An ESD protection circuit has a merged triggering mechanism. The ESD protection circuit comprises: an ESD detection circuit, for detecting an ESD voltage to generate a control signal; a first type ESD protection device, for outputting a first trigger current; a second type ESD protection device, for receiving a second trigger current; and a trigger circuit, for constituting a conductive path according to the control signal, such that the trigger circuit can receive the first trigger current from the first type ESD protection device and outputs the second trigger current to the second type ESD protection device.

Abstract: The present disclosure generally pertains to surge protection systems that protect outside plant equipment from high-energy surges. In one exemplary embodiment, a protection system is used for protecting Ethernet equipment that is coupled to an outside Ethernet cable. The protection system provides protection and remains capable of coupling signal energy between an Ethernet cable and Ethernet equipment without significantly degrading Ethernet performance. However, the protection system, while allowing the desirable Ethernet signals to pass between the cable and the equipment, prevents the electrical voltages and currents of high-energy surges, such as surges from lightning or AC power faults, from damaging the Ethernet equipment.

Abstract: A low forward voltage drop transient voltage suppressor utilizes a low-reverse-voltage-rated PN diode electrically connected in parallel to a high-reverse-voltage-rated Schottky rectifier in a single integrated circuit device. The transient voltage suppressor is ideally suited to fix the problem of high forward voltage drop of PN diodes and high leakage of low reverse breakdown of Schottky rectifiers. The low-reverse-voltage PN rectifier can be fabricated through methods such as 1) double layers of epi (with higher concentration layer epi in the bottom) or 2) punch through design of PN diode by base with compression.

Abstract: Disclosed is a surge protection device (200) comprising a semiconductor substrate(210) of a first conductivity type, said semiconductor substrate having a first surface and a second surface opposite to the first surface, the substrate further comprising a first junction device at the first surface having a junction oriented parallel to the first surface, and a second junction device at the second surface having a junction oriented parallel to the second surface, said first and second junction devices facing each other, with the first and second junction being separated by the bulk of the semiconductor substrate.