Abstract: A semiconductor die includes a substrate comprising a first layer of a first wide band gap semiconductor material having a first conductivity, a second layer of a second wide band gap semiconductor material having a second conductivity different from the first conductivity, in electrical contact with the first layer, a third layer of a third wide band gap semiconductor material having a third conductivity different from the first conductivity and second conductivity, in electrical contact with the second layer, a fourth layer of a fourth wide band gap semiconductor material having the second conductivity, in electrical contact with the third layer, and a fifth layer of a fifth wide band gap semiconductor material having the first conductivity and in electrical contact with the fourth layer, wherein the first layer, the second layer, the third layer, the fourth layer, and the fifth layer are sequentially arranged to form a structure.

Abstract: A circuit breaker comprising first and second JFETs, each comprising a gate, drain and source connection, the JFETs sources being operatively connected to each other to form a common-source connection and adapted to be connected to and operating to open an external circuit when the current flowing through the JFETs exceeds a predetermined threshold, the JFETs' gates, and common-source connection being operatively connected to a gate driver circuit which causes the JFETs to turn off when the predetermined threshold is exceeded; whereupon the current flows through the common-source connection into the second gate and into the gate driver circuit which causes the gate driver circuit to turn off the first and second JFETs and open the circuit breaker. Also claimed is a method of sensing an overloaded circuit comprising leading and trailing JFETs in a circuit that open the circuit and prevent current flow when a predetermined threshold is exceeded.

Abstract: Apparatuses and methods for providing transient electrical event protection are disclosed. In one embodiment, an apparatus comprises a detection and timing circuit, a current amplification circuit, and a clamping circuit. The detection and timing circuit is configured to detect a presence or absence of a transient electrical event at a first node, and to generate a first current for a first duration upon detection of the transient electrical event. The current amplification circuit is configured to receive the first current from the detection and timing circuit and to amplify the first current to generate a second current. The clamping circuit is electrically connected between the first node and a second node and receives the second current for activation. The clamping circuit is configured to activate a low impedance path between the first and second nodes in response to the second current, and to otherwise deactivate the low impedance path.

Abstract: The invention relates to a multi-staged overvoltage protection circuit, in particular for information-technology systems, comprising at least one coarse protection element and at least one fine protection element, wherein the at least one fine protection element can be activated by a triggering device depending on a threshold. According to the invention, the applied operating voltage is led to an evaluation device, which generates a reference voltage. Also provided is an evaluation unit, firstly for checking to see whether the current operating voltage is above the reference voltage, secondly for checking to see whether the voltage excess exceeds a previously determined level, and thirdly for establishing whether the rate of change of the operating voltage is greater than another previously determined value so that a transient overvoltage exists, wherein the triggering device then receives an activation signal from the evaluation device.

Abstract: In an embodiment, set forth by way of example and not limitation, a power line surge protector circuit includes a first input node, a second input node, a first output node and a second output node; a semiconductor shunt having an avalanche breakdown potential, the shunt being coupled between the first input node and the second input node, whereby a voltage potential between the first input node and the second input node which is in excess of the avalanche breakdown potential shunts current between the first input node and the second input node; and a resettable circuit breaker coupled between the first input node and the shunt.

Abstract: Techniques or processes for providing markings on products are disclosed. Particular arrangements of input devices may provide enhancements in ease of use. Further, cosmetic laser marking of input devices may provide improved visual appearance. Additionally, selectively controlling laser operation parameters during laser marking may provide laser marking that may be substantially electrically conductive, which in turn may be helpful in electrostatic discharge protection.

Abstract: An electronic fuse (506, 507) suitable for use in a direct current, DC, applications which is exposed to surges. The electronic fuse (506,507) comprises a current sensor (500) for measuring a current flowing in a current path of the DC system, the electronic fuse comprising a first transistor switch (501) which is arranged in the current path, the first transistor switch comprising at least one parasitic diode (511) having a forward direction which is opposite to an operational DC direction of the current path. The electronic fuse further comprising a controller (502) operatively connected to the current sensor (500) and adapted to control the first transistor switch (501) based on the measured current, and a current restrictor (503,520) which is capable of blocking a current from flowing in the current path in a direction opposite to the operational DC direction.

Abstract: In the circuit for detecting static electricity, a switch for cancelling charges on an electrode body, which detects static electricity, is not necessarily provided. The circuit (30) for detecting static electricity comprises: a P-channel FET and an N-channel FET having respective gates thereof electrically connected to each other; a direct-current power supply for driving the P-channel FET and the N-channel FET; an electrostatically charging section (39) to be electrostatically charged, the electrostatically charging section being a portion where the gates of respective P-channel FET and the N-channel FET are electrically connected to each other; and automatically resetting means (C1, C2) which makes the electrostatically charging section (39) automatically discharge the static electricity, which has charged on the electrostatically charging section, and makes it possible to have the electrostatically charging section (39) electrostatically charged again.

Abstract: Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected.

Abstract: An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a ground rail and the first drain to an I/O pad; coupling a gate driver control circuit to the first drain and the first gate; and providing a ground potential to the first gate, via the gate driver control circuit, during an ESD event occurring from the I/O pad to the ground rail.

Abstract: An ESD protection device with a tunable holding voltage is disclosed. Embodiments include: providing a silicon-controlled rectifier (SCR) having a first n-type layer with a cathode connection, a first p-type layer with a first control connection, a second n-type layer with a second control connection, and a second p-type layer with an anode connection; coupling the anode connection to a power rail; coupling the cathode connection to a ground rail; providing a tunable holding voltage control unit including a first NMOS having a first gate, a first drain, and a first source, wherein during an ESD event, the first NMOS is turned off and a holding voltage of the SCR is low; coupling the first drain to the first control connection; coupling the first source to the ground rail; and coupling the first gate to a program circuit.

Abstract: An embodiment high efficiency power regulator comprises a three-terminal converter and a protection device. The three-terminal converter comprises a first terminal coupled to a positive terminal of an input voltage bus, a second terminal coupled to a positive terminal of an output voltage bus and a third terminal coupled to the protection device. The protection device comprises an inrush current limiting element connected in series with a reverse polarity protection device.

Abstract: Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode.

Abstract: An input protection circuit may include an input node to receive an input signal, and may further include an output node to provide a protected output signal based on the input signal. Protection circuitry may be coupled between the input node and the output node to establish a current path that bypasses the input node and pulls the output pin to a specified reference voltage level in the event of a transient at the input node. A push-pull power supply may be used to provide the reference voltage to the current path, and dissipate any excess voltage by burning it off in a semiconductor device included in the push-pull power supply circuitry.

Abstract: An electro-static discharge protection device includes a substantially rectangular parallelepiped base in which insulating ceramic layers are laminated, a pair of discharge electrodes that are located inside the base and that include facing portions facing each other, and outer electrodes that are located on surfaces of the base and that are electrically connected to the discharge electrodes. The base includes a cavity therein, and the facing portions of the discharge electrodes are exposed in the cavity. The base has an hourglass shape in which the thickness of the insulating ceramic layers is gradually decreased from an area near both ends of the base to a central portion thereof with respect to both a longitudinal cross section passing through the center in the longitudinal direction of the base and a lateral cross section passing through the center in the lateral direction of the base.

Abstract: Disclosed herein is a semiconductor integrated circuit including in a same semiconductor substrate: first and second power supply lines; a protected circuit being connected between the first and second power supply lines and provided with a supply voltage; a detecting circuit detecting a surge generated in the first power supply line; an inverter circuit having one or more inverters connected in series to each other; and a protection transistor being connected between the first and second power supply lines and controlled by output of the detecting circuit to discharge the surge to the second power supply line. In the inverter circuit, an inverter whose output is connected to a control node of the protection transistor is connected between the first power supply line and a third power supply line that is different from the first and second power supply lines.

Abstract: The invention relates to a surge arrester which, in a housing (7), has at least one arrester element (3), in particular a varistor, a solder-fixed thermal disconnection point (5), which is connected to the arrester element, and a damage indicating device (11) for displaying the fault state, wherein the damage indicating device also queries the state of a thermal disconnection device, in particular a fuse, and presents the possible fault states of the arrester element and of the disconnection device mechanically in an OR combination in a suitable way. Furthermore the thermal disconnection device comprises a movable component, which is fixed by an indicator wire and is released after the melting or destruction of said wire. According to the invention, a guide part (9) for a compression spring (10) or similar force accumulator is provided on or in the housing.

Abstract: An electrostatic discharge (ESD) protection circuit includes a first power line; a second power line; a ground line; two stack transistors connected in series between the first power line and the ground line; a first resistor connected between the first power line and a first node; a first transistor and a capacitor connected in series between the first node and the ground line; a second transistor connected between the second power line and a second node; a third transistor connected between the first power line and a third node; an inverter, connected between the third node and the ground line, and having an input connected to the second node; a fourth transistor, connected to the first power line, and having a gate connected to the second node; and a fifth transistor, connected between the second power line and the third node, and having a gate connected to a terminal of the fourth transistor.

Abstract: The present invention relates generally to systems and methods for detecting ground faults (i.e., line-to-ground faults) in motor drive systems. In particular, the embodiments described herein include a common mode choke of a motor drive system having additional (i.e., secondary) turns wound around a core of the common mode choke. These secondary turns are in addition to and separate from a plurality of sets of primary turns wound around the core of the common mode choke, each set of primary turns corresponding to a phase of AC power to which the common mode choke is directly coupled. The secondary turns terminate in series with a burden resistor. Ground faults may be detected by monitoring the voltage across the burden resistor.

Abstract: An electrical system includes an alternating current (AC) source; a transformer rectifier unit (TRU) connected to the AC source, the TRU configured to receive AC power from the AC source, convert the AC power to direct current (DC) power, and output DC power; a DC bus configured to receive the DC power output by the TRU; at least one DC load powered by the DC bus; and a shunt regulator connected to the output of the TRU, the shunt regulator configured to overload the output of the TRU in the event of an overvoltage condition at the output of the TRU, such that a voltage available to the DC bus during the overvoltage condition does not exceed a reference voltage.

Abstract: A transient voltage surge suppression device includes a varistor assembly having a compact thickness, and a disconnect element carrying a separable contact along a linear axis to disconnect the varistor element from external circuitry.

Abstract: Power consumption of electronic components is reduced, particularly in a multi-chip package. Embodiments reduce parasitic capacitance of a semiconductor chip by reducing ESD protection circuitry that is not needed during operation of the package. ESD protection circuitry would be operational during production and/or testing of the chip, but some circuitry would be disabled or removed prior to normal operation of the multi-chip package.

Abstract: Integrated circuits, memories, protection circuits and methods for protecting against an over-limit electrical condition at a node of an integrated circuit. One such protection circuit includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit electrically coupled to a reference voltage and further electrically coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition for the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit.

Abstract: A Power over Ethernet (PoE) Power Device (PD) circuit and a protection circuit of electrostatic discharge (ESD) thereof are provided. The protection circuit of ESD includes a transient voltage suppressor (TVS) and a high-voltage capacitor, wherein the TVS and the high-voltage capacitor are coupled in series between a negative power terminal and a grounding terminal to reduce system malfunctions or damages when ESD or transient voltage surge occurs.

Abstract: An integrated protection circuit for protecting a main circuit from spurious high amplitude voltage signals is provided, wherein the main circuit has a main circuit input terminal connected to an input line, and the protection circuit comprises a transistor, a resistor and a capacitor. The transistor has a first electrode connected to the input line, a second electrode connected to a common reference, and a control electrode connected to the resistor. The resistor is connected to the common reference; and the capacitor is implemented as a fringe capacitor between the input line and the control electrode or a conductive line connected to the control electrode.

Abstract: An electrostatic discharge (ESD) protection device that protects a power amplifier from ESD. The ESD protection device includes a filter circuit connected to an antenna line of a wireless communication apparatus and that passes an ESD component having a predetermined frequency or less, a detection circuit that converts an output of the filter circuit into an analog DC output, a level determination circuit that detects that the analog DC output of the detection circuit is a predetermined threshold value or more, and a control interrupt circuit that controls a state of the power amplifier in accordance with an output of the level determination circuit.

Abstract: Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a circuit from an ESD event. The ESD protection device includes first and second trigger elements. Upon detecting an ESD pulse, the first trigger element provides a first trigger signal having a first pulse length. The second trigger element, upon detecting the ESD pulse, provides a second trigger signal having a second pulse length. The second pulse length is different from the first pulse length. A primary shunt shunts power of the ESD pulse away from the ESD susceptible circuit based on the first trigger signal. A current control element selectively pumps current due to the ESD pulse into a substrate of the primary shunt based on the second trigger signal.

Abstract: A voltage suppressor component including a semiconductor layer; a first port mounted on the semiconductor layer and configured to receive electrical power; a second port mounted on the semiconductor layer and configured to provide the electrical power, and a fuse in electrical series between the first port and the second port and mounted on the semiconductor layer.

Abstract: A safe area voltage regulator is provided that includes a loss element, a distributed shunt regulator and an output terminal. The loss element component is directly connected to the distributed shunt regulator and includes a plurality of loss elements connected in series. The distributed shunt regulator is made up of a plurality of shunt regulators connected in parallel and is configured to regulate a peak voltage of a voltage signal to below a maximum voltage threshold. The output terminal is directly connected to the distributed shunt regulator and configured to output the voltage signal with the regulated peak voltage.

Abstract: A power converter includes a transient voltage protection circuit connected between an input of the power converter and a power stage of the power converter. The transient voltage protection circuit provides a low resistance connection from the input of the power converter to the power stage of the power converter when the input voltage is less than a predetermined threshold, but blocks the input voltage from the power stage when the input voltage is equal to or greater than the predetermined threshold voltage. The power converter may be a boost power converter used in a vehicle to provide power from a main power bus of the vehicle to a subsystem of the vehicle such as an anti-lock brake system.

Abstract: A power converter includes a bypass circuit connected in parallel with a power stage of the power converter. The bypass circuit provides a lower loss current path in parallel with the power stage when an input voltage of the power converter exceeds a predetermined threshold. The power converter may be a boost power converter used in a vehicle to provide power from a main power bus of the vehicle to a subsystem of the vehicle such as an anti-lock brake system.

Abstract: An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to selectively switch a bonding pad to (i) a first rail of a power source and (ii) a discharge rail in response to an electrostatic discharge. The second circuit is generally configured to clamp the electrostatic discharge between the discharge rail and the first rail. The third circuit may be configured to bias the discharge rail to a second rail of the power source.

Abstract: A circuit interrupter, such as a GFCI or AFCI product, is provided having a suppression and protection circuit and circuit interrupter circuitry. In one configuration, a semiconductor device and a voltage clamping device or surge protector, such as a metal oxide varistor (MOV), are utilized in the circuit interrupter for handling transient surges and overvoltage conditions. The semiconductor device, such as a SIDCA and a TVS diode, is connected to a solenoid or trip coil of the circuit interrupter circuitry to limit the amount of current through the semiconductor device. The MOV is placed between phase and neutral conductors of the circuit interrupter circuitry.

Abstract: Some embodiments relate to an electrostatic discharge (ESD) protection device. The ESD protection device includes a first electrical path extending between the first and second circuit nodes and including a trigger element. A second electrical path extends between the first and second circuit nodes. The second electrical path includes a shunt element. A switching element is configured to trigger current flow through the shunt element based on both a state of the trigger element and a state of the switching element.

Abstract: One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical switch, a second diode including a second anode and a second cathode, with the second cathode coupled to the node via a second mechanical switch, the second anode coupled to a ground and a resistor coupled to the input circuit between the integrated circuit and the node, wherein in a first mode of operating, the first mechanical switch and the second mechanical switch are conducting, and in a second mode of operating, the first and second mechanical switches are nonconducting.

Abstract: Systems and methods for limiting voltage on an auxiliary bus are described. The voltage-limited auxiliary bus may be comprised of a DC auxiliary bus comprised of a positive conductor and a negative conductor; a chopper, wherein the chopper is normally in a non-conducting state; a resistor in series with the chopper, wherein the chopper and the resistor are connected between the positive conductor and the negative conductor of the DC auxiliary bus; and a chopper control, wherein an overvoltage on the DC auxiliary bus causes the chopper control to cause the chopper to begin conducting and the conducting limits the voltage on the DC auxiliary bus and dissipates energy from the overvoltage.

Abstract: A circuit arrangement for enforcing an intrinsically safe situation in a hazardous zone features a first switching device that lies in the series arm and a second switching device that lies in the shunt arm. If a fault occurs that would violate the conditions of intrinsic safety, the first switching device is initially blocked and the second switching device is switched through with a time delay such that the output terminals are mutually short-circuited. In addition, a monitoring device is provided for monitoring the load conditions at the switching device arranged in the series arm.

Abstract: A method and device for protecting an electric system against overvoltage occurrences, the electric system being adapted to be subjected to voltages. The device includes a plurality of surge arresters and a detector configured to detect overvoltage occurrences in the electric system. The surge arresters are connected in series, the plurality of surge arresters including a first surge arrester which is connectable to ground and a second surge arrester which is connectable to the electric system which is to be protected. The device includes a switch connected in parallel with at least one surge arrester of the plurality of surge arresters, and the switch is adapted to be open when no overvoltage occurrence is detected and adapted to close upon overvoltage occurrence detection and short-circuit the surge arrester with which it is connected in parallel. An electric system includes at least one such device.

Abstract: Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.

Abstract: An over voltage protection (OVP) monitoring system and a method thereof. The OVP monitoring system includes a battery pack connected to an external system, the battery pack including a battery, a first memory to store a voltage value of the battery, a second memory comprising a first sub-memory and a second sub-memory to store numbers of OVP operations of the battery, a controller to store the voltage value of the battery in the first memory upon an occurrence of an OVP operation and to increment a number of OVP operations stored in either the first sub-memory or the second sub-memory according to the voltage value of the battery stored in the first memory and a signal generator to generate either a first alarm signal or a second alarm signal based on the contents of the first and second sub-memories.

Abstract: A system comprises a package with top and bottom surfaces, a plurality of high-power transient voltage suppressors arranged within the package, and a robust lead frame. Each of the transient voltage suppressors has first and second major surfaces substantially perpendicular to the top and bottom surfaces of the package. The lead frame comprises leads connected to the major surfaces of the transient voltage suppressors. Each of the leads has a thickness greater than about 0.015 inches (or 0.381 mm) in a mounting portion, in order to dissipate heat from the transient voltage suppressors and to resist vibration-induced stress on the package.

Abstract: A printed circuit board includes a primary region, a secondary region and an isolation region disposed between the primary region and the secondary region to galvanically isolate the primary region from the secondary region. The primary region is to be coupled to an AC source. The primary region also includes an electrostatic discharge (ESD) conducting pathway to redirect current to the AC source that crosses the isolation region. A spark gap is included in the ESD conducting pathway.

Abstract: An enhanced turn-on time SCR based electrostatic discharge (ESD) protection circuit includes an integrated JFET, method of use and design structure. The enhanced turn-on time silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection circuit includes an integrated JFET in series with an NPN base.

Abstract: Protection circuits, design structures, and methods for isolating the gate and gate dielectric of a field-effect transistor from electrostatic discharge (ESD). A protection field-effect transistor is located between a protected field-effect transistor and a voltage rail. Under normal operating conditions, the protection field-effect transistor is saturated so that the protected field-effect transistor is coupled to the voltage rail. The protection field-effect transistor may be driven into a cutoff condition in response to an ESD event while the chip is unpowered, which increases the series resistance of an ESD current path between the gate of the protected field-effect transistor and the voltage rail. The voltage drop across the protection field-effect transistor may reduce the ESD stress on the gate dielectric of the protected field-effect transistor.

Abstract: An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition.

Abstract: An optocoupler circuit includes a switch connected in parallel with a photo LED, the photo LED having an anode and a cathode. The anode is connected to a power supply via a decoupling capacitor. The optocoupler circuit is arranged so that the switch turns on the photo LED when in the open position. When closed, the switch directs current flow through a series resistor to ground and shunts current flow away from the photo LED to turn off the photo LED. A second capacitor is connected to the cathode of the photo LED. The second capacitor is wired in series with a second switch and a current limiting resistor connected to ground. The first switch and second switch operate in complementary states to prevent the cathode connected capacitor from discharging. The disclosed optocoupler circuit provides the ability to function at increased levels of common mode voltage transients.

Abstract: Methods and apparatus for protecting data bus ports and their corresponding PHY devices from taking damage associated with excess voltage across one or more signal pairs during an intermittent connection are provided. Such connections cause the signal pins to carry external device current which raises the signal voltage above the power rails, exceeding the PHY device ratings and causing PHY degradation or destruction. In an exemplary embodiment, an RC circuit is used to detect the voltage level across a signal pair. If this voltage level exceeds a certain preset voltage level, power to the outgoing serial bus port is shut off and return power is abated. While the circuit is responding, the exemplary embodiment uses a 3.6V Zener diode to bleed excess voltage to ground. A current monitor/limiter is also used for limiting current if the voltage level detected exceeds a certain threshold.

Abstract: A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P+ doped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region.

Abstract: Described herein are various embodiments of a power distribution unit having modular components. For example, according to one embodiment, a power distribution unit can include a component portion that comprises at least two modules including outlet modules, circuit protection modules, power input modules, communications I/O modules, and display modules. Each of the at least two modules of the component portion can comprise at least one connection element and can be removably secured to one or more other of the at least two modules via the connection elements. The power distribution unit can also include a housing that defines an interior cavity. The component portion can be removably secured to the housing at least partially within the interior cavity.

Abstract: In a conventional differential output circuit, the output terminals are connected to the drains of a differential pair of transistors and the sources of the transistors are connected together at a first node. The bodies of the transistors are connected to a second node having a potential different from that of the first node. In the event of a HBM ESD event, discharge may take place through the differential transistors, leading to destruction of one of them. To reduce the likelihood of such discharge, in a preferred embodiment, switches are provided to connect the body of each of the differential transistors to the first node when an ESD event is sensed. In an alternative embodiment, a switch is provided to connect the first node to the second node when an ESD event is sensed.