Abstract: An ESD protection system for an internal circuit is disclosed. The ESD protection system comprises an ESD clamping device connected between a pad and a ground of a first domain); a pre-driver having an output coupled to a gate of the ESD clamping device); an ESD control circuit connected between the pre-driver and the internal circuit; and a transient detection unit coupled to the ESD control circuit, configured to detect an ESD transient from the pad of the first domain. The transient detection unit outputs an first signal to the control circuit upon detection of an ESD transient. In response, the control circuit causes the pre-driver to output a high-impedance state at the gate of the ESD clamping device, thereby floating the gate thereof.

Abstract: A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.

Abstract: A bridgeless interleaved power factor corrector is used to convert an AC power source into a DC power source. The bridgeless interleaved power factor corrector includes a first conversion circuit, a second conversion circuit, a first power switch, a second power switch, a positive-half control switch, and a negative-half control switch. The first power switch is coupled to one of two positive-half operation units of the first conversion circuit and one of two negative-half operation units of the second conversion circuit. The second power switch is coupled to the other one of two positive-half operation units and the other one of two negative-half operation units. The positive-half control switch is coupled between a neutral end and a ground end, and the negative-half control switch is coupled between a line end and the ground end.

Abstract: Disclosed are a fault current-suppressing damper topology circuit and a control method thereof and a converter. An anode of a separate diode is connected to a positive electrode of a second switch module, a cathode of the separate diode is connected to one end of an energy storage capacitor, and the other end of the energy storage capacitor is connected to a negative electrode of a first switch module; a damping resistor is connected in parallel with an arrester and then with the first switch module; a bypass switch is connected in parallel between a terminal x1 and a terminal x2 of the damper topology circuit; a power supply system acquires energy from the energy storage capacitor and supplies power to a control system; and the control system controls an operating state of the damper topology circuit by controlling the bypass switch, the first switch module and the second switch module. The fault current-suppressing damper topology circuit is applied to voltage source converters.

Abstract: A package may include a plurality of stacked semiconductor devices (chips) is disclosed. Each chip may include through vias (through silicon vias—TSV) that can provide an electrical connection between chips and between chips and external connections, such as solder connections or solder balls. Electro static discharge (ESD) protection circuitry may be placed on a bottom chip in the stack even when through vias connect circuitry on a top chip in the stack exclusive of the bottom chip. In this way, ESD protection circuitry may be placed in close proximity to the ESD event occurring at an external connection. In particular, every chip in the stack of semiconductor chips may have circuitry electrically connected to the external connection and by placing ESD protection circuitry on the bottom chip closest to the electrical connection, instead of on all chips ESD protection may be more area efficient.

Abstract: A package may include a plurality of stacked semiconductor devices (chips) is disclosed. Each chip may include through vias (through silicon vias—TSV) that can provide an electrical connection between chips and between chips and external connections, such as solder connections or solder balls. Electro static discharge (ESD) protection circuitry may be placed on a bottom chip in the stack even when through vias connect circuitry on a top chip in the stack exclusive of the bottom chip. In this way, ESD protection circuitry may be placed in close proximity to the ESD event occurring at an external connection. In particular, every chip in the stack of semiconductor chips may have circuitry electrically connected to the external connection and by placing ESD protection circuitry on the bottom chip closest to the electrical connection, instead of on all chips ESD protection may be more area efficient.

Abstract: An electrostatic discharge protection circuit may include discharge path circuitry to discharge charge on a supply line in response to detection of an ESD event. The charge on the supply line may be discharged through the discharge path circuitry from when a first timing window opens until a second timing window closes. The first timing window may also be used to detect ESD events. The two timing windows may allow an initial period of the ESD voltage on the supply line to be suppressed before the second timing window opens, and may further allow a remaining period of the ESD event following the initial period to be suppressed after the first timing window closes.

Abstract: A transient-triggered DC voltage-sustained power-rail ESD clamp circuit comprises: a transient-triggered module, a DC voltage-triggered module and a discharge device, wherein the transient-triggered module is connected with the DC voltage-triggered module and the discharge device respectively. When an ESD event is approaching, the ESD protection circuit can be turned on well and quickly, and can effectively avoid the problems of erroneous triggering and latching-up caused by quick power-on and high-frequency noise at the same time.

Abstract: A wire connection structure includes a ring-shaped magnetic body, a first wire having a first wire end portion which is inserted through the ring-shaped magnetic body from a first direction, a second wire having a second wire end portion which is inserted through the ring-shaped magnetic body from a second direction opposite to the first direction, and a conductive member which is disposed outside the ring-shaped magnetic body and has two end portions that are electrically connected to a conductor of the first wire end portion and a conductor of the second wire end portion respectively.

Abstract: In one embodiment, a PoDL system includes a PSE that uses high side and low side circuit breakers that uncouple the PSE voltage source from the wire pair in the event that a fault is detected. Faults may include a temporary short to ground, or to a battery voltage, or between the wires. The breakers perform an automatic retry operation in the event the fault has been removed. The voltages on the wires in the wire pair may be monitored to determine whether the voltages are within a normal range or indicative of a fault condition. Other embodiments are disclosed.

Abstract: A semiconductor integrated circuit device is provided with first and second regions that are operated by mutually different voltages, and a signal wiring that supplies a signal from the first region to the second region. The second region includes a circuit that is connected to between a first wiring to which a voltage is selectively supplied and a third terminal to which a voltage is supplied, and is operated by a differential voltage between the voltage in the first wiring and the voltage supplied to the third terminal, and a discharge circuit for discharging a charge in the first wiring. By using the discharge circuit, the potential difference between the signal wiring and the first wiring is prevented from becoming larger, and thus makes it possible to reduce damages of the circuit included in the second region.

Abstract: A system includes an alternating current (AC) to direct current (DC) voltage convertor, a power factor correction (PFC) subsystem, and one or more motor drives. The AC to DC voltage converter receives alternating current from an AC voltage source. The PFC subsystem receives DC voltage from the AC to DC voltage convertor. The PFC subsystem also outputs a corrected DC voltage corresponding to an output voltage setpoint. The PFC subsystem includes a controller operable to dynamically adjust the output voltage setpoint. The one or more motor drives receive voltage via the PFC subsystem. The output voltage setpoint is determined based at least in part on estimating a load associated with the one or more motor drives configured to receive voltage via the PFC subsystem.

Abstract: An apparatus includes a device, a comparison circuit, and a switch. The device includes a first terminal coupled to a first power supply signal, and a second terminal coupled to a ground reference. The comparison circuit is configured to compare a first voltage level on the first power supply signal to a second voltage level of a second power supply signal, and enable the device in response to a determination that the first voltage level is greater than the second voltage level. The switch circuit is configured to couple a power supply terminal of the comparison circuit to the first power supply signal in response to determining that the first voltage level is greater than the second voltage level, and to couple the power supply terminal to the second power supply signal in response to determining that the first voltage level is less than the second voltage level.

Abstract: The object of the invention is an overvoltage protection apparatus with monitoring function having a parallel circuit of two branch circuits, wherein the first branch circuit has a first overvoltage protection device and a second overvoltage protection device that are connected in series, wherein the second branch circuit has a third device and a fourth device that are connected in series, wherein the first overvoltage device and the third device have a first shared voltage potential during operation, and wherein the second overvoltage device and the fourth device have a second shared voltage potential during operation, wherein a first measuring tap is provided between the first overvoltage protection device and the second overvoltage protection device and wherein a second measuring tap is provided between the third device and the fourth device, with a signal being derived from the voltage between the first measuring tap and the second measuring tap that provides state information in relation to the first ove

Abstract: A circuit protection device including a housing (15) defining a chamber (19) and a metal oxide varistor (MOV) stack (310) disposed within the chamber (19). A first spring (330a) is electrically attached at a first end to a first input terminal (311a) of the MOV stack (310) by a solder connection (30) and at a second end to a first input line (20a). The first spring (330a) is biased away from the first input terminal (311a). A second spring (330b) is electrically attached to a second input terminal (311b) of the MOV stack (310) by a solder connection (40) and at a second end to a second input line (20b). The second conductive spring (330b) is biased away from the second input terminal (311b). When an overvoltage condition occurs, heat generated by the MOV stack (310) melts at least one of the first or second solder connections (30, 40) to allow the corresponding springs to be displaced away from the respective MOV stack (310) input terminals (311 a, 311 b), thereby creating an opening circuit.

Abstract: Provided are a power carrier signal coupling circuit and a communication system. The power carrier signal coupling circuit includes a first power carrier signal coupling channel and a second power carrier signal coupling channel. A phase of a three-phase alternating current (AC) power line serves as a common channel, the first power carrier signal coupling channel is arranged between the common channel and one of two phases of the three-phase AC power line other than the phase of the three-phase AC power line serving as the common channel; and the second power carrier signal coupling channel is arranged between the common channel and the other of the two phases of the three-phase AC power line other than the phase of the three-phase AC power line serving as the common channel.

Abstract: The invention concerns a device for protection against transitory overvoltages, comprising: a varistor; a discharge tube; a thermofusible soldering securing a first electrode of the discharge tube and a first electrode of the varistor, the thermofusible soldering being a conductor of electricity and being able to melt beyond a temperature threshold when the varistor or the discharge tube heats up; the second electrode of the varistor being designed to be connected to a first electrical line and the second electrode of the discharge tube being designed to be connected to a second electrical line; a restoring element exerting a restoring force tending to move the first electrode of the varistor away from the first electrode of the discharge tube in order to allow a separation between the first electrode of the varistor and the first electrode of the discharge tube during a melting of the thermofusible soldering.

Abstract: The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes GND wirings and GOA areas. The GND wirings are configured at outer sides of the GOA areas, and the GOA area includes a variety of GOA signal lines and N-th stage GOA circuits electrically connected by the GOA signal lines. A first ESD protection circuit is configured in a middle area between the 1-th stage GOA circuit and the N-th stage GOA circuit to discharge abnormal electrical charges of the GOA signal lines within the middle area. With such configuration, better ESD protection capability is provided between the GOA signal lines.

Abstract: A semiconductor device is provided. The device comprises: a first transistor that includes a first primary terminal, a second primary terminal and a first control terminal; a second transistor that includes a third primary terminal, a fourth primary terminal and a second control terminal; and a resistive element. The first and third primary terminal are connected to a first voltage line. The second primary terminal and one terminal of the resistive element are connected to a second voltage line. The first and second control terminal, the fourth primary terminal and the other terminal of the resistive element are connected to a node. A potential change in the third primary terminal is transmitted to the first control terminal by capacitive coupling between the third primary terminal and the node, turning on the first transistor.

Abstract: A capacitor input circuit for a mobile power supply includes a bulk capacitor and a switch. The switch connects the bulk capacitor to receive a rectified AC voltage from a rectifier when an AC line voltage input to the mobile power supply is lower than a threshold voltage. When the AC line voltage is greater than the threshold voltage, the switch electrically floats the bulk capacitor.

Abstract: A wind power generation system according to an embodiment includes a blade; a lightning protection device; an electric device; a voltage application mechanism; a first lightning arrester element; and a second lightning arrester element. The lightning protection device includes a receptor provided at the blade and guides a current of lightning to the ground from the receptor via a lightning conductor. The electric device is installed at the blade and includes a first electric conductor and a second electric conductor provided apart from each other. The voltage application mechanism applies a voltage between the first electric conductor and the second electric conductor. The first lightning arrester element has one end thereof electrically connected to the first electric conductor and has the other end thereof grounded. The second lightning arrester element has one end thereof electrically connected to the second electric conductor and has the other end thereof grounded.

Abstract: A surge reduction filter (SRF) includes a cartridge having a cartridge housing, a first active connection point for connection to an active line of an AC power supply, and a neutral connection point for connection to a neutral line of the AC power supply. The active and neutral connection points are located to be accessible from outside the cartridge. A first fuse and a first surge protection element are electrically connected in series between the active and neutral connection points. A status circuit is connected to monitor the surge protection element and an indicator is connected to the status circuit to indicate at least a normal status and a fault status of the surge protection element. The status circuit detects a change in voltage at a point between the fuse and the protection element and creates a fault indication if a voltage change is detected due to the fuse operating.

Abstract: An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first ESD cell is stacked in series with at least a second ESD cell. An active shunt transistor is electrically in parallel with the first ESD cell or second ESD cell, where the active shunt includes a control node. A trigger circuit has a trigger input and a trigger output, wherein the trigger output is coupled to the control node.

Abstract: A hazardous area coupler is provided which uses arrays of diodes to permit low voltage alternating current signals to pass through while shunting to ground any voltages greater than the clamping voltage of the diodes.

Abstract: The present invention provides a switching regulator with PFC function and a control circuit and a control method thereof. The switching regulator with PFC function includes a power stage circuit, a current sense circuit, and a control circuit. The power stage circuit operates at least one power switch therein according to an operation signal to convert an input voltage to an output voltage. When a transient voltage of the input voltage exceeds a transient voltage upper limit, or when a transient slew rate of the input voltage exceeds a transient slew rate upper limit, the control circuit adjusts a frequency response gain from a stable state frequency response gain to a transient state frequency response gain, such that a transient current of an output current does not exceed a current upper limit, and/or that a transient response time of the output current does not exceed a threshold transient time period.

Abstract: A first power line configured to receive a first voltage, a second power line configured to receive a second voltage which is lower than the first voltage, a first clamping unit configured to be connected to the first power line, a second clamping unit configured to be connected between the first clamping unit and the second power line, and a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit are included.

Abstract: A semiconductor device is provided. The device comprises: a first transistor that includes a first primary terminal, a second primary terminal and a first control terminal; a second transistor that includes a third primary terminal, a fourth primary terminal and a second control terminal; and a resistive element. The first and third primary terminal are connected to a first voltage line. The second primary terminal and one terminal of the resistive element are connected to a second voltage line. The first and second control terminal, the fourth primary terminal and the other terminal of the resistive element are connected to a node. A potential change in the third primary terminal is transmitted to the first control terminal by capacitive coupling between the third primary terminal and the node, turning on the first transistor.

Abstract: An apparatus and a method monitor the status of a thermal protection device within a surge protection device (SPD). A monitoring circuit connected to a monitor output signal of the SPD is responsive to the presence of a time-varying voltage on the monitor output signal. The time-varying voltage is present during a selected half of each AC cycle when the thermal protection device is intact such that the SPD is no longer providing surge protection. The time-varying voltage is not present when the thermal protection device is no longer intact. When the time-varying voltage is not present for a selected duration, the monitoring circuit illuminates a light-emitting diode (LED) to indicate that the thermal protection device has failed.

Abstract: An ESD protection structure formed within a semiconductor substrate of an integrated circuit device. The ESD protection structure comprises a thyristor structure being formed from a first P-doped section forming an anode of the thyristor structure, a first N-doped section forming a collector node of the thyristor structure, a second P-doped section, and a second N-doped section forming a cathode of the thyristor structure. A low-resistance coupling is provided between an upper surface region of the collector node of the thyristor structure and the anode of the thyristor structure.

Abstract: Methods and products for activating a backpack audio-visual system are generally described. In an example, a module in the backpack may detect a presence of a device in a first compartment that may be defined by a first set of walls. In response to the detection, the module may determine a status of a first speaker and a second speaker. The first and second speakers may be inside of a second compartment and a third compartment, respectively. The second and third compartments may be defined by a second and a third set of walls, respectively. Based on the presence of the device in the first compartment and the status of the first and second speakers, the module may establish a wireless communication link between the device and the first and second speakers. The backpack audio-visual system may be activated in response to the establishment of the wireless communication link.

Abstract: To provide a protection element in which an increase in current due to off-state leakage can be reduced while a drive current can be ensured during an ESD operation. Provided is the protection element including: a clamp MOS transistor that has a drain coupled to a power supply line and a source coupled to a ground line; and a potential increasing circuit that increases a potential of a diffusion layer at the ground line side of the clamp MOS transistor, more than a potential of the ground line. In this protection element, the potential of the diffusion layer coupled to the ground line of the clamp MOS transistor is increased from the potential of the ground line, whereby an increase in current due to off-state leakage can be reduced while a sufficient drive current is ensured during an ESD operation.

Abstract: An electronic device is disclosed that includes an output device and a detection circuit. The output device is coupled to an output pad, and is turned on according to a protection signal. The detection circuit is configured to detect a voltage level of a control node, to generate the protection signal based on the detected voltage level, and to switch the voltage level to a predetermined voltage level according to the detected voltage level.

Abstract: Embodiments of the present invention provide methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.

Abstract: A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a SLBJT situated in the n-type well, a base of the SLBJT situated in the n-type well and spaced from the emitter by a distance on one side of the base, a collector of the SLBJT situated in the n-type well and spaced from the base by the distance on an opposite side of the base, and an electrical connection to the substrate outside the n-type well. The SLBJT is used to characterize a transistor in a circuit by electrically coupling the SLBJT to a gate of the test transistor, applying a voltage to the gate, and characterizing aspect(s) of the test transistor under the applied voltage. The SLBJT protects the gate against damage to the gate dielectric.

Abstract: A system for dynamically controlling over voltage protection includes a voltage detection circuit, an over voltage protection reference signal output circuit, and an over voltage control signal output circuit. The voltage detection circuit is used for detecting a voltage and outputting a sampled voltage according to the voltage. The over voltage protection reference signal output circuit is coupled to the voltage protection circuit for generating an over voltage protection reference signal according to the sampled voltage and a voltage feedback signal. The over voltage control signal output circuit is coupled to the voltage detection circuit and the over voltage protection reference signal output circuit for generating an over voltage control signal according to the sampled voltage and the over voltage protection reference signal.

Abstract: In accordance with an embodiment, a method includes receiving by a drive circuit electrical power from a voltage tap of a first rectifier circuit that includes a load path and a voltage tap, and using the electrical power by the drive circuit to drive a second rectifier circuit that includes a load path. The load path of the first rectifier circuit and the load path of the second rectifier circuit are coupled to a common circuit node.

Abstract: A power detection circuit includes an input end for receiving an AC input signal, a rectifier for converting the AC input signal into a rectified signal, an output end for outputting the rectified signal, at least two voltage clamp circuits, each for providing an electrical path between the output end and a reference voltage end when the rectified signal is greater than a threshold voltage of the voltage clamp circuit. A threshold voltage of at least one of the voltage clamp circuit is different from a threshold voltage of another clamp circuit.

Abstract: The control circuit includes first and second primary terminals for connection to a DC network, a secondary terminal connected in series between the first and second primary terminals and at least one auxiliary energy conversion element and an auxiliary terminal. The first and second primary terminals have a plurality of modules and a plurality of primary energy conversion elements connected in series therebetween to define a current transmission path, each module including at least one energy storage device, each energy storage device being selectively removable from the current transmission path.

Abstract: A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated circuit. A first plurality of leads is electrically bonded to the first integrated circuit. A first lead of the first plurality of leads has an inner portion covered by the first encapsulant and an outer portion extending outside the encapsulant. The outer portion has a hole and a bend at the hole. The outer portion extends above the first encapsulant.

Abstract: A semiconductor device includes a semiconductor substrate having a predetermined region in which a standard cell is disposed, and also includes: a first circuit connected to a first ground power line; a second circuit that is connected to a second ground power line and formed from the standard cells; and a protection circuit interposed and connected between the first circuit and the second circuit. The protection circuit includes: a resistor connected in series between the first circuit and the second circuit; and a protector that is interposed and connected between a node of the resistor on the second circuit side and the second ground power line and clamps a potential difference between the node and the second ground power line to a predetermined voltage or lower. The protection circuit is formed in a protection cell disposed in the predetermined region.

Abstract: Apparatus and methods for overvoltage switches with active leakage current compensation are provided. In certain configurations, an IC includes an input node and a protection device or overvoltage switch electrically connected to the input node. The protection device includes a first well and a second well. The second well is positioned adjacent to the first well and has a conductivity type opposite that of the first well. Additionally, a first terminal of the protection device is electrically connected to the first well and to the input node of the IC. The protection device further includes a leakage current compensation circuit that is used to control a voltage level of the second well based on a voltage level of the first terminal to inhibit a leakage current of the first terminal of the protection device.

Abstract: An improved approach is provided for determining differential voltages for driver and receiver pairs as a result of electrostatic discharge (ESD) events including identifying circuits of interest, re-characterizing the circuits of interest into a system for evaluating differential voltages, determining the differential voltages for ESD pin locations, and outputting results after iterating through all the ESD pin locations. In some embodiments, re-characterizing may include performing a resistance only extraction of a net, attaching a resistance to any node in the circuit and to ground, formulating a conductance matrix and distributing the total current I as source points.

Abstract: An ESD protection circuit for an RF circuit includes first and second power supply voltage terminals for first and second power supply voltages and a power clamp coupled between the terminals. An RF input pad is configured to receive an input signal having an RF operating frequency. A resonance circuit is coupled to the RF input pad. A first ESD current path from the RF input pad to the first power supply voltage terminal includes the resonance circuit and a first ESD block configured to direct an ESD pulse of a first polarity toward the first terminal. A second ESD current path from the RF input pad to the second power supply voltage terminal includes the resonance circuit and a second ESD block configured to direct an ESD pulse of a second polarity toward the second terminal.

Abstract: A capacitor bank comprising at least two series chains each comprising a plurality of capacitors, wherein the series chains are coupled in parallel at corresponding points; and a fusible link arranged to form at least part of each coupling; wherein the corresponding points of each chain that are coupled to one another are at the same voltage when the capacitor bank is operational.

Abstract: An ESD protection circuit used to protect a protected circuit coupled between a first node and a second node against an ESD event. The ESD protection circuit has a discharging circuit and a control circuit. The discharging circuit selectively provides a current path for discharging a current from the first node to the second node. The control circuit controls the discharging circuit to switch on the current path during an ESD event. The control circuit further controls the discharging circuit to switch off the current path during the normal operation of the protected circuit.

Abstract: Various implementations described herein are directed to an integrated circuit for electrostatic discharge (ESD) protection. The integrated circuit may include a detection stage having a resistor and a first capacitor cascaded with a second capacitor. The resistor and the first capacitor are arranged to define a triggering node configured to provide a triggering signal. The first capacitor and the second capacitor are arranged to define a reference node configured to provide a reference signal. The integrated circuit may include a first ESD clamping stage having a first transistor configured to provide a supply voltage to a first clamping transistor based on the triggering signal. The integrated circuit may include a second ESD clamping stage having a second transistor configured to receive the supply voltage from the first transistor and provide the supply voltage to a second clamping transistor based on the reference signal.

Abstract: An electro-static discharge (ESD) structure includes an input pad, and a first switching device electrically connected to the input pad. The ESD structure further includes a first diode, wherein the first switching device is configured to selectively connect the first diode to the input pad, and the first diode is configured to provide a first dissipation path for an ESD event at the input pad. The ESD structure further includes a second diode selectively connectable to the input pad, wherein the second diode is configured to provide a second dissipation path for the ESD event at the input pad.

Abstract: A power switching device (e.g., a power MOSFET) drives relatively large surges of pulsed power through a laser emitter of a Time of Flight (TOF) determining system where both the power switching device and laser emitter are closely packed on a printed circuit board having further closely packed and temperature sensitive other components. Waveforms of pulse trains that control the power switching device are programmably defined and thus may include pulse durations that are unduly large or spacing between pulses that are unduly small such that overheating may occur. A pulse duration limiting circuit is provided having an analog integrator configured to integrate over time, the programmably defined pulses and a voltage triggered clamping device coupled to an output of the analog integrator. The voltage triggered clamping device has a predetermined threshold voltage at and above which it is switched from a relatively low transconductances mode to a substantially higher transconductances mode.

Abstract: Electrostatic discharge protection circuits and methods for protecting a core circuit from an electrostatic discharge event. The protection circuit may include a first anti-parallel diode pair including a first terminal coupled to an input/output pad, and a second anti-parallel diode pair including a second terminal coupled to a negative power supply voltage. The second anti-parallel diode pair is coupled in series with the first anti-parallel diode pair at a node. An offset pad is coupled to the node. The offset pad is configured to receive a first signal that is a duplicate of a second signal that is received at the input/output pad.

Abstract: An electrostatic discharge (ESD) protection device with a high holding voltage is disclosed including at least an ESD clamp coupled to a holding voltage tuning circuit. The ESD clamp may be coupled to the holding voltage tuning circuit through a connection circuit such as a diode. The ESD clamp may be implemented by a first silicon controlled rectifier (SCR) and the holding voltage tuning circuit may be implemented as a second SCR.