Abstract: An electrostatic discharge (ESD) logging system includes ESD detection circuitry having at least one input electrically connected coupled to a node of an ESD protection circuit. The ESD detection circuitry provides a detector signal in response to detecting an ESD event at the node of the ESD protection circuit. Capture circuitry is electrically connected to an output of the ESD detection circuitry. The capture circuitry asserts a capture signal to indicate the occurrence of the ESD event in response to the detector signal. A logic circuit provides a logic output in response to the capture signal.

Abstract: Disclosed is a device capable of preventing a short circuit even in the event of flooding. A terminal polarity fixing unit is disposed between an input terminal unit and an output terminal unit such that a first output terminal and a second output terminal are electrically connected to a neutral terminal and to a phase voltage terminal, respectively, all the time, regardless of how first and second input terminals are paired with the phase voltage terminal and the neutral terminal of an alternating-current outlet. First and second connecting terminals are electrically insulated from each other and spaced apart from each other while being exposed to one side of a body unit of a connecting terminal block made from an insulating body, and electrically connect the first and second output terminals to a load.

Abstract: In an embodiment, an ESD protection circuit may include a silicon-controlled rectifier (SCR) and a diode sharing a PN junction and forming a bi-directional ESD circuit. The single PN junction may reduce the capacitive load on the pin, which may allow the high speed circuit to meet its performance goals. In an embodiment, a floating P-well contact may be placed between two neighboring SCRs, to control triggering of the SCRs.

Abstract: A semiconductor device is provided. The semiconductor device includes a first conductive portion on a first side of a first shallow trench isolation (STI) region. The first conductive portion is formed within a first well having a first conductivity type. The first conductive portion has the first conductivity type. The first conductive portion is connected to an electro static discharge (ESD) circuit. A second conductive portion is on a second side of the first STI region. The second conductive portion is formed within a second well having a second conductivity type. The second conductive portion having the first conductivity type is connected to a first nanowire and an input output I/O port.

Abstract: An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.

Abstract: A surge protector for protecting telecommunications related equipment and other associated sensitive electrical components from over-voltage transient occurring on tip/ring conductors of telecommunication lines coupled thereto includes a printed circuit board and a plurality of surge protection circuits being mounted on the printed circuit board. Each of the plurality of surge protection circuits includes a first set of steering diodes and a second set of steering diodes. A common transient voltage clamping device has a first end connected to a first conductor lead and a second end connected to a second conductor lead so as to be shared by the plurality of surge protection circuits. A common pair of series-connected rectifier diodes has a first end also connected to the first conductor lead and a second end also connected to the second conductor lead so as to be shared by the plurality of surge protection circuits.

Abstract: An electrical apparatus for a vehicle has a primary control unit for controlling and supplying the electrical apparatus with energy and a secondary output unit subordinate to the control unit and outputs data transmitted by the control unit. The control unit and the output unit are connected to one another via a data line. The control unit has an electrical filter with three inductor coils for suppressing interference signals. The inductor coils are inductively coupled to one another such that a direction of a magnetic flux produced by a first flow of current in the first inductor coil and of a magnetic flux produced by a second flow of current in the second inductor coil in the main body is opposite a direction of a further magnetic flux produced by a third flow of current in the third inductor coil in the main body.

Abstract: Methods, systems, and apparatus for protecting electrical components are disclosed. In one aspect a system includes a first gas discharge tube connected to a first conductor of a first twisted wire pair; and a second gas discharge tube connected to a second conductor of the first twisted wire pair. The first gas discharge tube can also be connected to a third conductor of a second twisted wire pair, and the second gas discharge tube can be connected to a fourth conductor of the second twisted wire pair.

Abstract: A fault detection assembly of an integrated circuit having a supply port, an input port and a ground port. The fault detection assembly includes a first diode connected with one end to the supply port and connected with the other end to the input port, a second diode connected with one end to the input port and connected with the other end to the ground port, at least a first fault detection transistor of MOS type. At least one of first and second diodes includes a first diode-connected MOS transistor whose gate is connected to the gate of the first fault detection transistor.

Abstract: A false-trigger free power-rail ESD clamp protection circuit includes an ESD impact detection component, a discharge transistor, a discharge transistor turn-on channel, and a discharge transistor shutoff channel. The circuit, in a smaller layout area, has very strong electrostatic charge discharge capability under ESD impact, little power leakage during normal power-up, and relatively strong false-trigger immunity capability for quick power-up.

Abstract: A gate-coupled NMOS device according to an embodiment includes a P-type well region, an N-type well region, and N-channel MOS transistor, an N+-type tap region, a first conductive layer, and a second conductive layer. The N-type well region surrounds the P-type well region. An inner side of the N-type well region directly contacts a side of the P-type well region. The N-channel MOS transistor is disposed in the P-type well region. The N+-type tap region is disposed in the N-type well region. The first conductive layer is disposed on the N-type well region by interposing a first insulation layer and constitutes a MOS capacitor with the N-type well region and the first insulation layer. The second conductive layer is disposed on the N-type well region by interposing a second insulation layer and constitutes a resistor. A first end portion of the first conductive layer directly contacts a first end portion of the second conductive layer.

Abstract: An electrostatic discharge protection device including a PNP transistor, a protection circuit and an adjustment circuit is provided. An emitter of the PNP transistor is electrically connected to a pad, and a collector of the PNP transistor is electrically connected to a ground. The protection circuit is electrically connected between a base of the PNP transistor and the ground, and provides a discharge path. When an electrostatic signal occurs on the pad, the electrostatic signal is conducted to the ground through the discharge path and the PNP transistor. The adjustment circuit is electrically connected between the emitter and the base of the PNP transistor. When a power voltage is supplied to the pad, the adjustment circuit provides a control voltage to the base of the PNP transistor according to the power voltage, so as to prevent the emitter and the base of the PNP transistor from being forward biased.

Abstract: An electrical socket is provided with a ground; a neutral; and a line. The socket further includes female contact elements electrically connected to the ground, the neutral, and the line; line contacts electrically connected to the ground, the neutral, and the line; a surge protection module electrically connected to the ground, the neutral, and the line, the surge protection module including surge protection pairs; a count power module electrically connected to the surge protection module and including a bridge rectifier for converting AC to DC as output; and a count display module including a CPU electrically connected to the DC output, a surge detecting circuit electrically connected to the surge protection module for detecting a surge signal, and electrically connected to the CPU to send the detected surge signal to the CPU, and a display electrically connected to the CPU for displaying a count of the detected surge signal.

Abstract: An apparatus includes an input/output (I/O) pin and an electrostatic discharge device. The electrostatic discharge device is coupled to the I/O pin and to a voltage regulator.

Abstract: A high-power semiconductor module is disclosed, which can include a high-power semiconductor device mounted on the module and at least two electrical connections. The module can include a short-circuit device mounted on the module. The short-circuit device can generate a persistent electrically conducting path between the two electrical connections upon receiving a trigger signal by electrically destroying a semiconductor of the high-power semiconductor module.

Abstract: An integrated circuit includes a plurality of I/O cells, each including a portion of the first power bus, a portion of the second power bus, and an I/O pad coupled between the portions of the first and second power buses. A first set of the plurality of I/O cells is arranged along a die edge of the integrated circuit. A second set of the plurality of I/O cells is arranged along the die edge between the first set and the die edge. For each I/O cell in the first set, the portion of the first power bus is physically connected to the portion of the first power bus of an abutting I/O cell of the second set at a boundary between the I/O cell of the first set and the abutting I/O cell of the second set. The integrated circuit includes an ESD clamp and a trigger circuit.

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode.

Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.

Abstract: An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.

Abstract: The present invention discloses a protection circuit of Power Over Ethernet (POE) port and an Ethernet power-sourcing equipment. The port protection circuit includes: a first common mode suppression component, a second common mode suppression component, and a rectifier bridge. A first input end and a second input end of the rectifier bridge are connected to a first direct current output end and a second direct current output end of a PoE control chip, respectively. A first output end or a second output end of the rectifier bridge is connected to an uncharged signal line of a PoE port. An end of the first common mode suppression component is connected to the first output end of the rectifier bridge, and another end thereof is grounded. An end of the second common mode suppression component is connected to the second output end of the rectifier bridge, and another end thereof is grounded.

Abstract: An input/output (IO) circuit including: an IO driver circuit; an electrostatic discharge (ESD) protection semiconductor switch with a first input configured to receive an ESD, a second input connected to an ESD rail, and a switch control input; an ESD trigger circuit connected to the switch control input, wherein the ESD trigger circuit is configured to produce a trigger signal to close the protection semiconductor switch when the ESD detection circuit detects an ESD; and a bias circuit configured to provide a back bias signal to an isolated well of the ESD protection semiconductor switch when IO circuit is in normal operation.

Abstract: A connectorized wireless node used to distribute power and control devices in a system. The connectorized wireless node includes a housing, power control circuitry and wireless control circuitry. The power control circuitry is provided in the housing and distributes power to the devices. The wireless control circuitry is provided in the housing and receives wireless signals which contain control information. The wireless control circuitry cooperates with the power control circuitry to control the devices within a system.

Abstract: In one embodiment, a zero-crossing detection circuit for a synchronous step-down converter, can include: (i) a state determination circuit configured to compare a drain voltage of a synchronous transistor of the synchronous step-down converter against a reference voltage, and to generate a state digital signal indicative of whether a body diode of the synchronous transistor is turned on; (ii) a logic circuit configured to convert the state digital signal into a counting instruction signal; (iii) a plus-minus counter configured to generate a numerical signal in response to the counting instruction signal; (iv) a DAC configured to generate a correction analog signal based on the numerical signal; and (v) a zero-crossing comparator configured to receive the correction analog signal and the drain voltage of the synchronous transistor, and to provide a zero-crossing comparison signal to a driving circuit of the synchronous step-down converter.

Abstract: A cross-domain electrostatic protection device having four embedded silicon controlled rectifiers (a QSCR structure) embedded in a single cell. Two grounded-gate NMOS transistors are embedded into the cross-domain electrostatic protection device for reducing trigger voltage of the QSCR structure. Furthermore, an external trigger circuit and a bias circuit are applied to the cross-domain electrostatic protection device to reduce trigger voltage of the QSCR structure and leakage current.

Abstract: The invention provides a testing circuit for testing a connection between a chip and external circuitry. A current source is used to inject a DC current towards the connection to be tested from the chip side. On-chip ESD protection is provided giving a path between the connection to be tested and a fixed voltage line. A shunt path is also coupled to the connection to be tested on the external circuitry side. It is determined if the current source current flows through the ESD protection circuit, and this can be used to determine whether or not the connection to be tested presents an open circuit for the DC test current.

Abstract: An extension cord light source provides a source of light without additional cords or light units. A light source is attached or attachable to the end of an extension cord. The light source may be a light bulb-shaped source having multiple LEDs therein. Clear plastic encloses the devices therein and allows for multi-directional light beams. The LEDs may connected to a switch with multiple positions for controlling the amount of light. The extension cord lines pass through the bulb and into an outlet being a female plug. This combination thus eliminates the need for a drop light. A removable shade may be also attached to the bulb to prevent unnecessary light. A pilot lamp is included in the bulb to indicate that the power is present. The bulb may have a male plug therein that will accept the female plug of a conventional extension cord.

Abstract: Embodiments of the present invention disclose a lightning protection radio remote unit RRU, which includes a primary circuit, a secondary circuit, and a working circuit, where the primary circuit and the secondary circuit are configured to convert a power supply output by a power supply system into a working power supply to power the working circuit; the shield layer located on the RRU side of the shielded cable and the shield layer located on the power supply system side of the shielded cable are grounded respectively; a surge over-voltage withstand capability between the primary circuit and the earth is not less than a lightning over-voltage; a surge over-voltage withstand capability between each inner conductor in the shielded cable and the shield layer of the shielded cable is not less than the lightning over-voltage.

Abstract: An automated fire protection system for a freighter such as an aircraft may include a single fire retardant source for a first deck and a second deck. The system may further include a plurality of sensors for detecting fire and a plurality of nozzles for dispersing the retardant, wherein each nozzle is paired with one of the plurality of sensors. Once a fire is detected by one of the sensors, the fire protection system may eject fire retardant through only one or more nozzles paired with the sensor that detected the fire. Because retardant may be accurately dispersed close to the detected fire location through less than the plurality of nozzles, an amount of on-board retardant may be decreased, thereby decreasing weight of the fire suppression system. In an embodiment, the fire retardant may only be discharged during the descent, further decreasing the weight of the fire system.

Abstract: An input protection circuit changes the voltage of a signal to be input to an input circuit to a predetermined voltage or less and outputs the signal. The input protection circuit includes a first NMOS transistor and a second NMOS transistor. The first NMOS transistor includes a source to which an input signal is input, a gate to which a voltage based on a first voltage is applied, and a drain that outputs the signal to the input circuit based on the input signal and the gate voltage. The second NMOS transistor includes a source and a gate to each of which the voltage based on the first voltage is applied, and a drain that outputs a second voltage to the input circuit.

Abstract: A circuit includes a driver circuit between a first and second power supply nodes, and a first and second electrostatic discharge (ESD) protection circuits. The driver circuit is configured to generate a pair of differential signals at a first output node and a second output node. The first ESD protection circuit is coupled between the first output node and the second power supply node. The first ESD protection circuit includes a first transistor, and the first transistor includes a drain region and a source region in a well region. The second ESD protection circuit is coupled between the second output node and the second power supply node. The second ESD protection circuit includes a second transistor, and the second transistor includes a drain region and a source region in the well region.

Abstract: A secondary protection device may receive a voltage surge. The voltage surge may be received based on a failure associated with a primary protection device. The secondary protection device may protect a piece of protected equipment from the voltage surge based on receiving the voltage surge. The secondary protection device may generate a failure notification based on protecting the piece of protected equipment from the voltage surge. The failure notification may indicate the failure associated with the primary protection device. The secondary protection device may provide the failure notification.

Abstract: An input circuit suitable for an integrated circuit (IC) and a protection circuit in the input circuit are provided. The protection circuit includes a transistor, a voltage selector, an inverter, a resistor and a switch circuit. The transistor is coupled to an input end of the protection circuit. The voltage selector is coupled to the transistor and the input end of the protection circuit, and outputs a lower one of a voltage at the input end of the protection circuit and a ground voltage to the transistor. The inverter is coupled to the transistor. The resistor is coupled between a power supply voltage and the inverter. The switch circuit is coupled to the inverter, a preset voltage and an output end of the protection circuit and is controlled by the inverter to connect the preset voltage to the output end or to switch the output end to a floating state.

Abstract: A distributed electrostatic discharge protection circuit includes a plurality of electrostatic discharge protection elements and a current balancing network connecting the plurality of electrostatic discharge protection elements. The current balancing network is configured in a return path of the distributed electrostatic discharge protection circuit such that during an electrostatic discharge (ESD) event, the circuit provides predefined current density within each of the electrostatic discharge protection elements.

Abstract: A high frequency surgical device for generating a high frequency voltage for cutting and/or vaporizing biological tissue within a flushing liquid, in particular a conductive flushing liquid, including two output contacts at which an electrosurgical instrument is connectable and between which the HF voltage is provided during operations; a parallel resonant circuit which is electrically connected with the output contacts and in which the HF voltage is generated during operations, and wherein the HF voltage is configured for igniting an electric arc within the flushing liquid at the electrosurgical instrument. In order to provide an electrosurgical device for applications under a flushing liquid, wherein the flushing liquid is heated less and wherein the electrosurgical device provides better initial cutting properties, it is provided according to the invention that a voltage limiter is arranged between the parallel resonant circuit and the output contacts.

Abstract: A structure of ESD protection circuits on a BEOL layer includes a substrate. A plurality of interconnect layers and an inter-level dielectric layer are disposed on the substrate. The inter-level dielectric layer is disposed between the plurality of interconnect layers. The last layer of the interconnect layers comprises an I/O pad, a first pad and a second pad. A first diode and a second diode are disposed on the last layer of the inter-level dielectric layer, wherein the first diode electrically connects to the I/O pad and the first pad and the second diode electrically connects to the I/O pad and the second pad.

Abstract: A circuit arrangement for protecting against electrostatic discharges comprises a diverter (ECL) that is suitable for diverting an electrostatic discharge between a first terminal (IO) and a second terminal (VDD, VSS), as well as a compensation device (1). The compensation device (1) features a series circuit of a first resistor (RS) and a field effect transistor (T1) that is connected between the first terminal (IO) and the second terminal (VDD, VSS). A junction (K1) between the first resistor (RS) and the field effect transistor (T1) is connected to the gate terminal (G1) of the field effect transistor (T1) via an RC series circuit that acts as a low-pass filter.

Abstract: Processor devices are provided which operate in one of multiple power operating modes. A processor device comprises first and second processor chips connected in a stacked configuration, and which respectively include first and second processors that operate as a single logical processor. A mode control circuit generates control signals and different sets of configuration parameters. A first control signal is generated to input a first set of configuration parameters to the single logical processor, which is utilized to operate the single logical processor in a first power operating mode wherein the first processor is turned on and the second processor is turned off. A second control signal is generated to input a second set of configuration parameters to the single logical processor, which is utilized to operate the single logical processor in a second power operating mode wherein both the first processor and the second processor are turned on.

Abstract: A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; a first capacitor part including a first internal electrode and a second internal electrode disposed in the ceramic body; second to fifth capacitor parts including a third internal electrode having a first lead, a fourth internal electrode having a second lead, a fifth internal electrode having a third lead, and a sixth internal electrode having a fourth lead, the third to sixth internal electrodes being disposed on one dielectric layer in the ceramic body, and a seventh internal electrode disposed on another dielectric layer in the ceramic body; and a first external electrode and a second external electrode. The first capacitor part and the second to fifth capacitor parts may be connected in parallel to each other.

Abstract: A distributed electrostatic discharge (ESD) protection circuit is provided. At frequencies beyond 10 GHz, the parasitic capacitance of primary ESD protection voltage clamping devices, such as diodes, hampers adequate insertion and return loss, in spite of lumped inductor tuning. An ESD protection circuit according to an embodiment of the present disclosure solves the problem by distributing the diode, or voltage clamping device, capacitance among several sections of an artificial transmission line. A transmission line is provided between a single input pad and the protected circuit, with a plurality of voltage clamping sections being distributed along the transmission line. The power and ground ESD return paths are also distributed to ensure a constant current density in the voltage clamping segments, even for fast charged-device model (CDM) discharge events. By sharing the ESD return paths between differential inputs (or outputs), these return paths have no impact on differential return or insertion loss.

Abstract: A light fixture includes a surge protection circuit for a non-isolated DC-DC converter. The converter is coupled to a circuit ground and further provides output power to a light source chassis configured to house a light source. The chassis is coupled to earth ground. The surge protection circuit includes a voltage triggering device having a breakdown voltage value and coupled to either the circuit ground or an output of the converter. A first capacitor is coupled in series between the voltage triggering device and the earth ground, and a second capacitor is coupled in parallel with the voltage triggering device. The first capacitor is configured with a sufficiently large capacitance wherein a voltage across the first capacitor, and likewise a voltage between the chassis and the earth ground, is effectively clamped to a light source threshold value during a surge condition.

Abstract: An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies.

Abstract: A surge protection circuit, related to the power electronics field. The surge protection circuit includes: an input configured to provide direct current power supply, an output configured to connect to a next circuit, and a cutoff circuit connected to the output; the surge protection circuit further includes: a discharge circuit connected between the input and the cutoff circuit; the discharge circuit includes: a diode and a field-effect transistor; the cathode of the diode is connected to the positive end of the input, and the anode of the diode is connected to the source of the field-effect transistor; the gate of the field-effect transistor is connected to the positive end of the input, the drain of the field-effect transistor is connected to the negative end of the input, and the direction of the parasitic diode of the field-effect transistor is opposite to the direction of the diode.

Abstract: In one aspect, the present subject matter discloses a method for overvoltage protection of an electrical system. The method may generally include detecting an overvoltage condition on an electrical system; and switching on, in response to the detected overvoltage condition, an impedance connected to the electrical system, wherein the impedance clamps voltage on the electrical system.

Abstract: A high voltage protection circuit for a non-tolerant integrated circuit is described herein. A non-tolerant integrated circuit may be a powered down integrated circuit or a low voltage tolerant integrated circuit, that may be exposed to a high voltage source such as an external circuit, device or power supply. The high voltage protection circuit includes a limiting transistor circuit, a control transistor circuit, and an isolation transistor circuit. The limiting transistor circuit limits or holds the voltage at the signal bump to be less than a voltage that can damage the circuit. The isolation transistor circuit disconnects input/output signal circuitry from normal protection circuitry. Both the limiting transistor circuit and the isolation transistor circuit are controlled by the control transistor circuit and are responsive to the power supply voltage being off.

Abstract: Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.

Abstract: A resistor device includes a resistor plate having opposite first and second surfaces; a first metal layer including first and second portions which are disposed on the first surface of the resistor plate at opposite first and second sides, respectively; and a second metal layer including a first sensing pad, a second sensing pad, a first current pad and a second current pad, separate from one another, wherein the first sensing pad and the first current pad are disposed on the first portion of the first metal layer and the second sensing pad and the second current pad are disposed on the second portion of the first metal layer. A protective layer is preferably provided, overlying the resistor plate and the first metal layer uncovered by the second metal layer.

Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit generates a detection signal in response to a transient electrical stress. First and second driver circuits of an integrated circuit, each driver having one or more bipolar junction transistors, activate based on the detection signal and generate activation signals. The one or more bipolar junction transistors of the first and second driver circuits are configured to conduct current substantially laterally across respective base regions. A discharge circuit, having an upper discharge element and a lower discharge element, receives the activation signals and activates to attenuate the transient electrical event.

Abstract: An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors. A gate region is common to all the MOS transistors and a semiconductor substrate region includes the substrates of all the MOS transistors.

Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.

Abstract: A semiconductor apparatus includes a first power supply pad configured to supply a first power; a second power supply pad configured to supply a second power; a first power line configured to be directly electrically coupled to the first power supply pad; and a second power line configured to be directly electrically coupled to the second power supply pad.