Abstract: Electrostatic discharge protection circuits and methods of fabricating an electrostatic discharge protection circuit, as well as methods of protecting an integrated circuit from a transient electrostatic discharge event. The electrostatic discharge protection circuit includes a power clamp device, a first timing circuit with a first resistor and a first capacitor that is coupled with the first resistor at a first node, and a second timing circuit including a second resistor and a second capacitor that is coupled with the second resistor at a second node. The electrostatic discharge protection circuit further includes a logic gate with a first input coupled with the first node, a second input coupled with the second node, and an output coupled with the power clamp device. The logic gate responds to voltages at the first and second nodes to control the impedance state of the power clamp device.

Abstract: A method of fabricating an electronic device is provided, where the electronic device includes a port, an A/D converter, a memory, and a determination circuit. The determination circuit is configured to determine whether or not there is an abnormality by comparing an A/D converted value as a result of the A/D converter converting a voltage based on a power-supply voltage inputted to the port with a limit value stored in the memory. The method includes a step of inputting a predetermined voltage to the port of the electronic device to be fabricated, and a step of recording an A/D converted value as a result of the A/D converter converting a voltage based on the predetermined voltage inputted to the port as the limit value in the memory.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit and configuration method thereof. The ESD protection circuit includes first and second power supply terminals, first and second detection units, a control unit, a clamping unit, and a voltage-dividing output node defined between the first and second power supply terminals. The first detection unit detects an electrostatic signal, based on a signal between the first power supply terminal and the voltage-dividing output node, and outputs a first signal. Likewise, the second detection unit outputs a second signal. The control unit is configured to be driven by the first signal to convert into a first discharge control signal and by the second signal to convert into a second discharge control signal. The clamping unit is configured to receive the first and second discharge control signals to discharge an electrostatic current between the first and the second power supply terminals.

Abstract: A body of a memory card reader, which has an overall rectangular parallelepiped shape including a slot for inserting a memory card. The reader body includes, on a rear surface thereof, a recess for receiving a memory card connector, the receiving recess being of a predetermined volume shape and including at least one conductive track.

Abstract: A voltage-resistant switch is described. The switch comprises a signal input, a first FET transistor with a first channel with an extended drain and a first gate connector and a second FET transistor with a first channel with an extended drain and a second gate connector. A control signal connector is connected with the first gate connector and with the second gate connector via a second node and with the first channel and the second channel via a second resistor, and a signal connector is connected with the second channel. The voltage-resistant switch can be switched on and off.

Abstract: A semiconductor device and a method for testing the semiconductor device are provided. The semiconductor device includes a diode (protection element) and a semiconductor element having a withstand voltage that is higher than that of the diode provided on one and the same first-conductive-type semiconductor substrate, the diode having a second-conductive-type first semiconductor region selectively provided in a front surface layer of the semiconductor substrate. A high concentration region is open in a normal time, but is short-circuited to a potential higher than that of a GND pad through a second wiring layer in a screening test time. Thus, a semiconductor device and a method for testing the semiconductor device are provided, in which a protection element can be prevented from breaking down and initial failure of a device which is formed on one and the same semiconductor substrate as the protection element can be detected accurately.

Abstract: A unit pixel driver circuit includes a capacitor configured to store a voltage corresponding to a desired pixel brightness and a control block. The control block may include a first, second third and fourth transistors, all of which are connected together, both in parallel and in series. The control block controls, based on the voltage stored in the capacitor, the amount of current flowing through a pixel LED. The first transistor, second transistor, third transistor and fourth transistor all share a common gate geometry size.

Abstract: A ground-loss detection circuit for an integrated circuit, (IC) device including a first dynamic threshold metal oxide semiconductor (DTMOS) device operably coupled between a first ground plane of the IC device and at least one further ground plane of the IC device, at least one of the first and at least one further ground planes comprising an external ground connection of the IC device, at least one further DTMOS device operably coupled between the first and at least one further ground planes of the IC device in an opposing manner to the first DTMOS device, and at least one ground-loss detection component operably coupled to at least one of the first and at least one further DTMOS devices and arranged to detect a ground-loss for at least one of the first and at least one further ground planes based at least partly on a drain current of the at least one of the first and at least one further DTMOS device(s).

Abstract: A surge protection circuit for an electronic device such as an HVAC controller. In one example, the surge protection circuit may include a first voltage clamp, a second voltage clamp, a resistor, and an output port. The first voltage clamp may provide a first clamping voltage between a power input terminal and a common terminal. The second voltage clamp may provide a second clamping voltage that is less than the first clamping voltage. The resistor may be connected in series with the second voltage clamp, and the series connected resistor and second voltage clamp may be connected in parallel with the first voltage clamp. As such, a surge current at the power input terminal may be split between the first voltage clamp and the second voltage clamp. The amount of surge current that is provided to the second voltage clamp may be set by the value of the resistor.

Abstract: A current transformer support device includes three plate-like conductors, each of which has a first connection portion at one end and a second connection portion at the other end, and which are aligned linearly side by side while being spaced apart from one another, and a current transformer case which integrally insulates and supports the three conductors between the one end and the other end. The current transformer support device is characterized in that the current transformer case has current transformer attachment portions provided at positions corresponding to at least two of the three conductors, to which ring-like current transformer coils formed so as to insert the conductors are attached, and that the current transformer case and the current transformer coils attached to the current transformer attachment portions are formed into one unit with a hardening insulating material.

Abstract: Embodiments of the systems and methods of direct cell attachment for battery cells disclosed herein operate without the protection FETs and the protection IC, thereby enabling the direct attachment of battery cells to the system without compromising safety. A charger IC comprises a switching regulator whose output is used to charge the battery through a pass device. In example embodiments of the disclosed systems and methods of direct cell attachment, a combination of switching FETs and the pass device are used as a protection device instead of the charge and discharge FETs. During normal operation, the pass device may be used to charge the battery using the traditional battery charging profile. Under fault condition, the switching FETs and pass device may be driven appropriately to protect the system.

Abstract: A method, apparatus, and energy metering system obtains mains samples of a mains power line signal, performs non-white noise (NWN) filtering of the mains power line signal, obtains adjustable clock source samples of an adjustable clock signal of an adjustable clock oscillator, determines a difference based on the mains samples and the adjustable clock source samples, adjusts an adjustable clock source frequency of the adjustable clock oscillator based on the difference, and applies the adjustable clock source frequency to an analog to digital converter (ADC) to determine a conversion rate of the ADC.

Abstract: A plug connector suitable for use as an airbag squib connector is presented. The plug connector includes a connector housing, having a plug-in portion and at least one female contact terminal that is arranged at least partially in the plug-in portion. The plug connector further includes a grounding contact, having an intermediate section and a contact section formed from sheet metal. The sections have respective main surfaces and circumferential edges. The contact section is configured to electrically contact a corresponding grounding contact of a counter-connector. The intermediate section branches off from the contact section. The main surfaces of the intermediate section and the contact section are parallel to the mating direction.

Abstract: A circuit comprises an alternating current (AC) feed line, a solid state power controller portion connected to the AC feed line, a load connected to the solid state power controller portion, a positive clamp rail, a negative clamp rail, a ground, a first diode connected to the AC feed line and the positive clamp rail, a second diode connected to the AC feed line and the negative clamp rail, a third diode connected to the load and the positive clamp rail, a fourth diode connected to the load and the negative clamp rail, a fifth diode connected to the positive clamp rail and the ground, a sixth diode connected to the negative clamp rail and the ground, and a capacitor connected to the positive clamp rail and the negative clamp rail.

Abstract: A surge protection device includes an isolating transformer configured to conduct an Ethernet data signal on a wire pair and configured to provide voltage surge protection for Ethernet equipment coupled to the wire pair, and a power supply coupled to the isolating transformer and configured to conduct a DC voltage signal from the wire pair and configured to provide voltage surge protection for the Ethernet equipment coupled to the wire pair.

Abstract: Provided is a deterioration diagnosis system which diagnoses deterioration of an N-phase rotational machine (N denotes a natural number). The deterioration diagnosis system includes a first current sensor to be attached individually to at least lead wires of (N-1)-phases in a rotational machine, the first current sensor being able to detect a current amplitude arising from a plurality of deterioration causes, and a second current sensor to be attached collectively to the lead wires of all phases in the rotational machine, the second current sensor being able to detect a current amplitude arising from a plurality of deterioration causes.

Abstract: This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.

Abstract: An electronic device includes an exterior portion of a conductive material, a circuit portion including circuit elements, and a protection circuit portion connected between the exterior portion and the circuit portion. The protection circuit portion includes a switching unit to intercept leakage current that flows from the circuit portion and leaks to the exterior portion, and a conversion unit to reduce a voltage level of an electrostatic component that flows through the exterior portion and to transfer the electrostatic component to the switching unit.

Abstract: A semiconductor device includes: a voltage-dividing resistor circuit including first and second resistors connected in series between a power supply potential and a reference potential and outputting a potential at a point of connection between the first and second resistors; a transient response detection circuit including a third resistor having a first end connected to the power supply potential and a capacitor connected between a second end of the third resistor and the reference potential, and outputting a potential at a point of connection between the third resistor and the capacitor; an AND circuit ANDing an output signal of the voltage-dividing resistor circuit and an output signal of the transient response detection circuit; and an output circuit, wherein switching of the output circuit is controlled by an output signal of the AND circuit.

Abstract: A high efficiency bridgeless power factor correction converter includes a power factor correction control unit, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first inductor, a second inductor and a bulk capacitor. The power factor correction control unit is configured to turn on or turn off the first switch, the second switch, the third switch, the fourth switch, the fifth switch and the sixth switch, so that the high efficiency bridgeless power factor correction converter converts an input alternating current voltage into an output direct current voltage.

Abstract: An example method for monitoring the operation of a metal-oxide varistor (MOV) may involve monitoring an operating value of at least one parameter of the MOV using at least one sensor. Further, the method may involve determining, using one or more processors, that a difference between the operating value and a reference value corresponding to the at least one parameter satisfies a predetermined threshold condition corresponding to the at least one parameter. And the method may involve responsive to determining that the difference between the operating value and the reference value satisfies the predetermined threshold condition, transmitting a notification indicative of a potential failure of the MOV to at least one device.

Abstract: A circuit comprises a first circuit and a second circuit. The first circuit is configured to operate at a first-circuit supply voltage value, and to generate a first reference voltage value based on a voltage rated for transistors in a second circuit. The second circuit is configured to operate at a second-circuit supply voltage value, to receive a first signal and the first reference voltage value, and to clamp an input node of the second circuit based on the first reference voltage value. The second-circuit supply voltage value is less than the first-circuit supply voltage value. The first signal is configured to swing between a low voltage value and a voltage value higher than the second-circuit supply voltage value.

Abstract: Semiconductor devices and related electrostatic discharge (ESD) protection methods are provided. An exemplary semiconductor device includes an interface for a signal and a multi-triggered protection arrangement coupled between the interface and a reference node to initiate discharge of the signal between the interface and the reference node based on any one of a plurality of different characteristics of the signal. Discharge of the signal at the interface is initiated based on a first characteristic of the signal, and thereafter, the discharge of the signal at the interface is maintained based on another characteristic of the signal.

Abstract: An optoelectronic module (100) is defined, comprising at least one semiconductor chip (10) provided for emitting electromagnetic radiation and at least one holding device (20) which is adapted to fix in place a device (50) for encoding at least one optical or electronic parameter of the optoelectronic module (100). Furthermore, a process for the production of the optoelectronic module (100) is defined.

Abstract: In accordance with an embodiment, a circuit includes a snubber circuit configured to be coupled to outputs of n half-bridge driver circuits that are coupled to n corresponding inductive loads, such that n is an integer greater than one. The snubber circuit includes n diodes and n capacitors. Each of the n diodes are coupled between a corresponding output of the n half-bridge driver circuits and a floating common node, and each of the n capacitors coupled between a corresponding output of the n half-bridge driver circuits and the floating common node.

Abstract: The design of the triggering circuit 1 of the overvoltage protection, connected via three poles 4 to the spark gap of the overvoltage protection, provided with the first input terminal 2 and the second main terminal 3, whose principle consists that an auxiliary electrode 7 of the spark gap 4 is connected in series to the first varistor 8 and one end of the secondary winding 14 of the transformer 13, the other end of which is connected to the second main electrode 6 of the spark gap 4 and the second input terminal 3, whereas one end of the primary winding 15 of the transformer 13 is connected in series to the gas discharge tube 10, the second varistor 9, resistor 11 and capacitor 12, connected to the other end of the primary winding 15 of the transformer 13, connected to the second input terminal 3, whereas the junction connecting the second varistor 9 to the resistor 11 is interconnected with the junction, connecting the first input terminal 2 to the first main electrode 5 of the spark gap 4.

Abstract: A device includes a transistor cascode circuit including a first transistor configured to pull up voltage of a bulk and a node in response to a first control signal, and a second transistor configured to pull up voltage of an interface (I/O) pin in response to a second control signal. The device further includes a third transistor configured to pull down voltage of the I/O pin in response to a third control signal, and a feedback circuit configured to turn off the first transistor when the voltage of the I/O pin is above a predetermined level during a failsafe period.

Abstract: A limiter circuit is integrated into an RF power amplifier. The limiter circuit automatically starts adding attenuation at the input of the RF power amplifier after a predetermined input power level threshold is exceeded, thereby extending the safe input drive level to protect the amplifier. In a preferred embodiment of the invention, the limiter circuit is implemented using a pseudomorphic high electron mobility transistor (PHEMT) device or a metal semiconductor field effect transistor (MESPET) device. Diode connected transistors or Schottky diodes may also be used in the limiter circuit.

Abstract: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.

Abstract: A system for distributing broadband signals via twisted pair wiring is disclosed. Various aspects of the system involve use of a broadband signal distribution interface device and/or a broadband line driver. In one aspect, a broadband signal distribution interface device includes a broadband signal interface configured to receive broadband radio frequency signals, and a plurality of broadband signal connections configured to distribute broadband radio frequency signals. The interface device also includes circuitry defining an upstream signal path and a downstream signal path and including a gain control circuit and a slope control circuit each positioned along the downstream signal path. The circuitry is configured to accommodate downstream transmission of the broadband signals onto twisted pair wiring.

Abstract: A surge protector having a hot line, a load line, a neutral line, and a ground line, the surge protector is provided. The surge protector has a fuse coupled between the hot line and the load line to protect loads from current surges. A differential mode protection circuit is coupled between the load line and the neutral line to protect loads from differential mode transient voltage surges. A common mode protection circuit is coupled to the load line, the neutral line and the ground line to protect loads from common mode transient voltage surges. An indicator circuit monitors the differential mode protection circuit and the common mode protection circuit to provide an indication as to the operational status of the surge protector.

Abstract: An electrostatic discharge protection circuit comprises at least two electrostatic discharge protection units connected in series between respective pairs of at least three input terminals, one of the input terminals being a reference input terminal. Each of the units comprises a silicon controlled rectifier and a current mirror. The output of the silicon controlled rectifier constitutes a first output of the respective unit and is connected to an input terminal of the circuit. The output of the current mirror constitutes a second output of the respective unit and is connected with the reference input terminal of the circuit. Thus the units are connected in series but the output terminals of the current mirrors are all connected with the reference input terminal, which may be a ground terminal, so as to minimize the breakdown resistance of the circuit.

Abstract: A motor drive includes a DC power supply unit for rectifying electric power supplied from an AC power supply using a rectifier and smoothing the electric power using a capacitor; and a plurality of independent voltage measurement circuits for measuring the voltage of the DC power supply unit. The motor drive, which converts a DC voltage into an AC voltage to drive a motor, includes a voltage collection unit for collecting voltage information obtained from the voltage measurement circuits; a normal operation voltage information storage unit for storing a normal operation voltage; and an abnormality determination unit for identifying an intersection voltage of output signals based on voltage values collected by the voltage collection unit, comparing the intersection voltage with the normal operation voltage, and detecting a broken portion owing to entering foreign matter based on the difference between the intersection voltage and the normal operation voltage.

Abstract: A semiconductor unit includes: a transistor configured to provide electrical conduction between a first terminal and a second terminal, based on a trigger signal; and a trigger device formed in a transistor region where the transistor is formed, and configured to generate the trigger signal, based on a voltage applied to the first terminal.

Abstract: A semiconductor device including: an output stage, including a PMOS, an NMOS and an output terminal, wherein a source terminal of the PMOS is connected to a first supply voltage, a drain terminal of the PMOS is connected to a drain terminal of the NMOS and the output terminal, a source terminal of the NMOS is connected to a second supply voltage, and the output terminal outputs an output signal; and a protection circuit, including a first voltage clamping circuit, including a first transistor, a second transistor and a first switch, wherein the first transistor and the second transistor are for clamping a gate voltage of the PMOS of the output stage and are connected in series, the first switch is coupled to the first supply voltage and a node between the first transistor and the second transistor for selectively coupling the first supply voltage to the node.

Abstract: A high voltage input buffer having a first transistor having a first drain, a first source and a first gate configured to receive an input signal and a second transistor having a second drain, a second source and a second gate, wherein the second source is coupled to the first source to form an output, the second gate is coupled to the first drain and the second drain is coupled to the first gate and wherein when the input signal is less than a high voltage power on the first drain an output signal at the output follows the input signal and when the input signal is greater than the high voltage power on the first drain the output follows the high voltage power and a hysteretic circuit adapted to receive the output signal.

Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.

Abstract: Described herein is a device and method for current flow control for dual battery vehicle architecture. The dual battery vehicle architecture includes a second energy source that is used to support electrical loads, such as radio and navigation systems, during re-cranking in stop-start situations. A quasi-diode device is configured to effectively split a main battery and starter circuit from the rest of the vehicle electrical system including the second energy source. The quasi-diode device includes a plurality of field effect transistors (FET) that conducts current in both directions between the main battery and starter circuit and the rest of the vehicle electrical system when the FETs are turned on and conducts current only from the main battery and starter circuit to the rest of the vehicle electrical system when the FETs are turned off, i.e. when re-cranking is occurring during a start-stop situation.

Abstract: ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event.

Abstract: An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

Abstract: A semiconductor arrangement and method of formation are provided. A semiconductor arrangement includes a first semiconductor device adjacent a second semiconductor device. The first semiconductor device includes a first gate over a first shallow well in a substrate. A first active area is in the first shallow well on a first side of the first gate. The second semiconductor device includes a second gate over a second shallow well. A third active area is in the second shallow well on a first side of the second gate. The second shallow well abuts the first shallow well in the substrate to form a P-N junction. The P-N junction increases capacitance of the semiconductor arrangement, as compared to a device without such a P-N junction.

Abstract: The circuit of the present disclosure is a high-speed precision clamp (voltage limiter) for overvoltage or undervoltage protection. One aspect of the circuit includes using a peak detector in the feedback path of a clamp having a super-diode architecture. The resulting circuit performs well for high-speed applications. The peak detector can be replicated (at least in part) to accommodate a multiplicity of phase-shifted input voltages by using only one common peak detection capacitor and ensuring area savings in integrated-circuit implementations.

Abstract: A connector and a method of manufacturing the same are disclosed. The connector includes a module including at least one protection device and a connector frame formed by a mold, and the module is buried in the mold. The connector further includes a plurality of connection pins that are connected to the connector frame, and each of the plurality of connections pins has an exposed portion. Each of the plurality of connection pins is exposed, and at least a first set of the plurality of connection pins is electrically connected to the at least one protection device.

Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

Abstract: A discharge circuit includes a discharge switch trigger unit, a discharge switch unit and a discharge resistor unit. The discharge switch unit is coupled connected to the discharge switch trigger unit. The discharge resistor unit is coupled connected to the discharge switch unit. The discharge switch trigger unit and the discharge resistor unit are coupled connected to a voltage output side. When the output voltage of a power supply reaches a predetermined rated limitation, an over voltage protection circuit is activated, and the discharge switch unit is turned on by the discharge switch trigger unit, then the output voltage starts to decrease through the discharge resistor unit.

Abstract: Provided is an ESD protection circuit including: a power MOS transistor provided between an external connection terminal and a reference voltage terminal; a clamping circuit that is provided between the external connection terminal and a gate of the power MOS transistor and clamps a voltage between the external connection terminal and the gate of the power MOS transistor at a predetermined value or less; a first resistive element provided between the gate and a source of the power MOS transistor; and a MOS transistor that is provided in series with the power MOS transistor and has a gate and a source which are commonly connected to each other.

Abstract: A telecommunications system uses a breakout device to connect a primary power cable to different secondary power cables that connect to different remote radio units (RRUs). For example, the breakout device may include a power distribution terminal that connects ?48 VDC and return power lines in the primary power cable to different ?48 VDC and return power lines in the secondary power cables. In another example, the breakout device may connect a hybrid cable that includes both power lines and fiber optic lines. A surge protection system may be located in the breakout device to protect the RRUs and other electrical device from power surges. Alternatively, the surge protection system may be located in jumper power cables connected between the breakout device and the RRUs.

Abstract: Apparatus and methods for providing transient overstress protection with active feedback are disclosed. In certain configurations, a protection circuit includes a transient detection circuit, a bias circuit, a clamp circuit, and a sense feedback circuit that generates a positive feedback current when the clamp circuit is clamping. The transient detection circuit can detect a presence of a transient overstress event, and can generate a detection current in response to detection of the transient overstress event. The detection current and the positive feedback current can be combined to generate a combined current, and the bias circuit can turn on the clamp circuit in response to the combined current. While the transient overstress event is present and the clamp circuit is clamping, the sense feedback circuit can generate the positive feedback current to maintain the clamp circuit turned on for the event's duration.

Abstract: An ESD protection circuit includes a plurality of resistors, at least a capacitor, a driving circuit and an ESD clamping device, wherein a first node of each resistor is connected to a first supply voltage, and a second node of each of at least a portion of the resistors is selectively connected to an input node via a corresponding switch respectively, and a first node of the capacitor is connected to a second supply voltage, and a second node of the capacitor is connected to the input node; the driving circuit is arranged to generate a driving signal according to a voltage on the input node; and the ESD clamping device is coupled to the driving circuit, and connected between the first supply voltage and the second supple voltage, and the ESD clamping device is arranged to selectively bypass an ESD current according to the driving signal.

Abstract: An electrostatic discharge (ESD) logging system includes ESD detection circuitry having at least one input electrically connected coupled to a node of an ESD protection circuit. The ESD detection circuitry provides a detector signal in response to detecting an ESD event at the node of the ESD protection circuit. Capture circuitry is electrically connected to an output of the ESD detection circuitry. The capture circuitry asserts a capture signal to indicate the occurrence of the ESD event in response to the detector signal. A logic circuit provides a logic output in response to the capture signal.