Abstract: A laminated ceramic capacitor having high electrostatic capacitance and excellent lifetime characteristics, even when in a high electric field intensity employs a dielectric ceramic including crystal grains and crystal grain boundaries which contains, as its main constituent, a perovskite-type compound including Ba, Ca, and Ti, and further contains Mg, R (Y, La, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and/or Yb), and Zr, such that when the laminated body is dissolved, the contents in terms of parts by mol are Ca: 3 to 15 parts by mol, Mg: 0.01 to 0.09 parts by mol, R: 2.5 to 8.4 parts by mol, and Zr: 0.05 to 3.0 parts by mol with respect to 100 parts by mol of Ti, and there is Ca at least at the centers of the crystal grains.

Abstract: A capacitive device includes a first capacitor including a first wiring layer, a first dielectric film, a first conductive layer, a first insulating layer on the first capacitor, a second capacitor on the first insulating layer including a second conductive layer, a second dielectric film, and a third conductive layer, a second insulating layer on the second capacitor, a second wiring layer on the second insulating layer including first and second connection wires, a first via connecting the first wiring layer to the second conductive layer, a second via connecting the third conductive layer to the second wiring layer, a third via connecting the first connection wire to the first conductive layer, and a fourth via connecting the second connection wire to the first wiring layer.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at % carbon. The method includes forming an opening through at least the support material where the opening has an aspect ratio of at least 20:1 within a thickness of the support material. After forming the opening, the method includes processing the support material to effect a reduction in conductivity, and forming a capacitor structure in the opening.

Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.

Abstract: An element array and a footprint layout for an element array are disclosed. The element array can have a rectangular configuration defining two side surfaces and two end surfaces. The element array can include a plurality of stacked dielectric-electrode layers. One dielectric-electrode layer can include a plurality of element electrodes, such as eight element electrodes. Each of the plurality of element electrodes forms a part of an individual element for the element array. The element array device can further include a common electrode. The common electrode is used as part of each of the individual elements for the element array. The common electrode can include a lead for termination to one of the two end surfaces of the element array or, in a particular embodiment, to one of the two side surfaces of the element array.

Abstract: An electrical multi-layered component includes a monolithic base member that has a plurality of ceramic layers and electrode layers disposed one on top of the other in alternating fashion. The base member includes two end surfaces opposite to one another and two side surfaces opposite to one another. The multi-layered component includes a plurality of external electrodes and a plurality of internal electrodes designed into the electrode layers. The internal electrodes at least partially overlap and form overlap areas. Each internal electrode is associated with a respective external electrode. At least one first internal electrode extending from an end surface overlaps with at least one second internal electrode (8) extending from an opposite end surface. At least a third internal electrode extends from an end surface.

Abstract: Disclosed herein is a mounting structure of a circuit board having a multi-layered ceramic capacitor thereon, the multi-layered ceramic capacitor including dielectric sheets laminated thereon and external terminal electrodes formed at both ends thereof, the dielectric sheets having internal electrodes formed thereon, and the external terminal electrodes being connected in parallel with the internal electrode, wherein the internal electrodes are disposed to be in parallel with the circuit board, the external terminal electrodes are bonded to lands of the circuit board by a conductive material, and a bonding height (Ts) of the conductive material is lower than a sum of a gap (Ta) between the circuit board and a bottom surface of the multi-layered ceramic capacitor and a thickness (Tc) of a cover layer on a lower portion of the multi-layered ceramic capacitor, whereby vibration noise can be greatly reduced.

Abstract: Disclosed herein are a stacked chip device including: a stacked body in which a plurality of sheets having an internal electrode made of a conductive material are stacked; external electrodes provided at both sides of the stacked body; and connection electrodes extending from the internal electrode and electrically connecting the internal electrode with the external electrodes, wherein the connection electrodes include: a plating solution permeation preventing section extending from the internal electrode, however, extending with a thickness smaller than the thickness of the internal electrode; and a contact reinforcement section extending from the plating solution permeation preventing section, however, extending in the form in which the thickness thereof is gradually extended toward the external electrode, and a manufacturing method thereof.

Abstract: The present disclosure discloses a structural capacitor, a connector comprising the structural capacitor and a communication apparatus using the connector. The structural capacitor comprises a rod and a holder. The rod comprises a first section and a second section connected with the first section, and the holder comprises a through hole. The first section and the second section are fitted into the through hole to accomplish the connection between the first section and the second section in an axial direction. The connector of the present disclosure features a simple structure, a convenient manufacturing process and a low cost. The communication apparatus of the present disclosure has advantages such as a simple manufacturing process, parameters that can be easily guaranteed, a low processing cost and a stable product performance.

Abstract: A vertical semiconductor charge storage structure includes a substrate, at least one lower electrode, a dielectric layer and an upper electrode. The lower electrode includes a lower conductor, and a first side conductor and a second side conductor connected to the lower conductor. The first side conductor and the second side conductor are parallel to each other and form an included angle with the lower conductor. A height of the first side conductor from the substrate is greater than a height of the second side conductor from the substrate. The dielectric layer and the upper electrode are sequentially formed on surfaces of the substrate and the lower electrode. Accordingly, by forming the first side conductor and the second side conductor at different heights, an aperture ratio is increased to reduce difficulty in filling or deposition in subsequent processes to further enhance an overall yield rate.

Abstract: A multilayer ceramic capacitor, having a plurality of electrode layers and a plurality of substantially titanium dioxide dielectric layers, wherein each respective titanium dioxide dielectric layer is substantially free of porosity, wherein each respective substantially titanium dioxide dielectric layer is positioned between two respective electrode layers, wherein each respective substantially titanium dioxide dielectric layer has an average grain size of between about 200 and about 400 nanometers, wherein each respective substantially titanium dioxide dielectric layer has maximum particle size of less than about 500 nanometers. Typically, each respective substantially titanium dioxide dielectric layer further includes at least one dopant selected from the group including P, V, Nb, Ta, Mo, W, and combinations thereof, and the included dopant is typically present in amounts of less than about 0.01 atomic percent.

Abstract: An electrical multi-layered component includes a monolithic base member that has a plurality of ceramic layers and electrode layers disposed one on top of the other in alternating fashion. The base member includes two end surfaces opposite to one another and two side surfaces opposite to one another. The multi-layered component includes a plurality of external electrodes and a plurality of internal electrodes designed into the electrode layers. The internal electrodes at least partially overlap and form overlap areas. Each internal electrode is associated with a respective external electrode. At least one first internal electrode extending from an end surface overlaps with at least one second internal electrode (8) extending from an opposite end surface. At least a third internal electrode extends from an end surface.

Abstract: A clad capacitor and method of manufacture includes assembling a preform comprising a ductile, electrically conductive fiber; a ductile, electrically insulating cladding positioned on the fiber; and a ductile, electrically conductive sleeve positioned over the cladding. One or more preforms are then bundled, heated and drawn along a longitudinal axis to decrease the diameter of the ductile components of the preform and fuse the preform into a unitized strand.

Abstract: Disclosed herein are a multilayer ceramic electronic component and a method for manufacturing the same. The multilayer ceramic electronic component includes a multilayer body in which dielectric layers and internal electrode layers are alternately stacked and external electrodes, wherein a portion in the internal electrode layers positioned in a marginal portion in which vertically neighboring internal electrode layers in the multilayer body is not overlapped with each other has a thickness thicker than that of a portion of the internal electrode layer positioned in an overlapped portion in which the vertically neighboring internal electrode layers are overlapped with each other, such that an accumulated stepped height difference in the marginal portion is reduced.

Abstract: In a laminate type ceramic electronic component, when an external electrode for a laminated ceramic capacitor is formed directly by plating onto a surface of a component main body, the film that is directly plated may have a low fixing strength with respect to the component main body. As the external electrode, a first plating layer composed of a Ni—P plating film with a P content rate of about 9 weight % or more is first formed such that a plating deposition deposited with the exposed ends of respective internal electrodes as starting points is grown on at least an end surface of a component main body. Then, a second plating layer composed of a Ni plating film containing substantially no P is formed on the first plating layer. Preferably, the first plating layer is formed by electroless plating, whereas the second plating layer is formed by electrolytic plating.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A multifunction charge transfer device that limits and controls a current and voltage to a circuit or load, comprising at least one input and at least one output electrode as the charging electrode 10a and the discharging electrode 10b respectively, both in the form of closed continuous electrical loops. The charging electrode 10a and discharging electrode 10b in the form of closed continuous electrical loops are arranged side by side so that the edges of the electrical conducting material and the dielectric material 11a and 11b forming each closed continuous electrical loop are in alignment. The two closed continuous electrical loops are separated by a gap 12 to prevent any electrical contact between them and so that the charging electrode 10a and discharging electrode 10b can only be coupled by the electrostatic field concentrated at the side of the closed continuous electrical loop forming the charging electrode 10a.

Abstract: A stacked film capacitor including a resin protective film having excellent durability is provided which can stably secure desired properties. The stacked film capacitor includes a capacitor element including a plurality of dielectric layers, and a plurality of vapor-deposited metal film layers. Each dielectric layer and each vapor-deposited metal film layer are stacked with each other so as to be arranged alternately. The stacked film capacitor further includes a pair of external electrodes provided on opposing side surfaces of the capacitor element, and at least one resin protective film formed on at least one side surfaces other than the side surfaces on which the external electrodes are formed, in which the at least one resin protective film is provided by deposition polymerization.

Abstract: An electronic device package includes first and second electrodes of a package substrate. The first electrode has fingers formed from a first metal level and is configured to operate at a first DC potential. The second electrode has fingers formed from the first metal level interdigitated with the fingers of the first electrode. A via conductively connects the second electrode to a second metal level. The second metal level is configured to operate at a second DC potential. The first and second DC potentials are thereby capacitively coupled through the interdigitated electrodes.

Abstract: A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.

Abstract: A capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one dielectric layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.

Abstract: A dielectric thin film element having a high humidity resistance is provided. A dielectric thin film element includes a capacitance section having a dielectric layer and a pair of electrode layers formed on the respective upper and lower surfaces of the dielectric layer 22. Furthermore, a protection layer is provided on the capacitance section, a pair of interconnect layers are drawn out to an upper surface of the protection layer, and external electrodes are formed to be electrically connected to the interconnect layers. Further, first surface metal layers cover a portion of the interconnect layers that extends along the inner surface of the openings and second surface metal layers are formed at end of the first surface metal layers.

Abstract: In a capacitor structure and method of forming the same, a first electrode, a second electrode, and a first insulation layer are sequentially formed on a substrate. The first and second electrodes and the first insulation layer are covered with a second insulation layer on the substrate. A first plug is in contact with the second electrode through the second insulation layer. A second plug is in contact with the first electrode through the first and second insulation layer. A third insulation layer is formed on the second insulation layer. Third and fourth comb-shaped electrodes are formed in the third insulation layer. The third electrode is contact with the first plug and the fourth electrode is contact with the second plug while facing the third electrode. Thus, the teeth of the comb-shaped electrodes are alternately arranged and spaced apart in the third insulation layer.

Abstract: A multilayer capacitor which can control ESR in a wide frequency band is provided. In a multilayer capacitor 1, inner electrodes 8a, 8b oppose each other as different polarities through a dielectric layer 7 in a capacitance unit 10, inner electrodes 8c to 8f oppose each other as different polarities through dielectric layers 7 in ESR control units 11A, 11B, and the inner electrodes 8a, 8b of the capacitance unit 10 connected to the outer electrodes 3, 4 and the inner electrodes 8c, 8f of the ESR control units 11A, 11B connected to the outer electrodes 3, 4 are kept from opposing each other as different polarities through the dielectric layer 7 at boundaries between the capacitance unit 10 and the ESR control units 11A, 11B.

Abstract: A capacitor structure includes a plurality of conductive line levels located over the substrate. Each of the conductive line levels includes a first conductive line and a second conductive line. The first conductive lines in the conductive line levels form a first conductive line co-plane and the second conductive lines in the conductive line levels form a second conductive line co-plane. A first conductive end is electrically connected to the first conductive lines on the conductive line levels. A second conductive end is electrically connected to the second conductive lines on the conductive line levels. A plurality of vias are located between the neighboring conductive line levels and placed on only one of the first and second conductive line co-planes on a same level.

Abstract: The instant article of manufacture is made by applying optical energy to one or more layers of nanoparticulate materials under predetermined conditions to produce a nanostructure. The nanostructure has layers of optically fused nanoparticles including a predetermined pore density, a predetermined pore size, or both. The predetermined conditions for applying the optical energy may include a predetermined voltage, a predetermined duration, a predetermined power density, or combinations thereof.

Abstract: A thin-film device system includes a substrate and a plurality of pillars. The plurality of pillars project from a surface of the substrate. Each of the plurality of pillars have a perimeter that includes at least four protrusions that define at least four recessed regions between the at least four protrusions. Each of the at least four recessed regions of each of the plurality of pillars receives one protrusion from an adjacent one of the plurality of pillars. A thin-film device is fabricated over the plurality of pillars.

Abstract: Dielectric ceramic composition includes a hexagonal type barium titanate as a main component shown by a generic formula (Ba1-?M?)A(Ti1-?Mn?)BO3 and having hexagonal structure wherein an effective ionic radius of 12-coordinated “M” is ?20% or more to +20% or less with respect to an effective ionic radius of 12-coordinated Ba2+ and the A, B, ? and ? satisfy relations of 0.900?(A/B)?1.040, 0.003???0.05, 0.03???0.2, and as subcomponents, with respect to the main component, certain contents of alkaline earth oxide such as MgO and the like, Mn3O4 and/or Cr2O3, CuO, Al2O3, rare earth element oxide and glass component including SiO2. According to the present invention, it can be provided the hexagonal type barium titanate powder and dielectric ceramic composition which are preferable for producing electronic components such as a capacitor and the like showing high specific permittivity, having advantageous insulation property and sufficient reliability.

Abstract: A capacitor includes a substrate, a plurality of first storage electrodes, a plurality of second storage electrodes, a first supporting layer pattern, a dielectric layer and a plate electrode. A plurality of contact pads is formed I the substrate. The first storage electrodes are arranged along lines parallel with a first direction and electrically connected to the contact pads, respectively. The second storage electrodes are respectively stacked on the first storage electrodes. The first supporting layer pattern extends in a direction parallel with the first direction between adjacent second storage electrodes and makes contact with the adjacent second storage electrodes to support the second storage electrodes. The dielectric layer is formed on the first and second storage electrodes. The plate electrode is formed on the dielectric layer.

Abstract: A device for saving electric power of the present invention comprises a case body; a tourmaline intermediate layer accommodated in the case body, which is a mixture layer of tourmaline power, permanent magnet power and moisture (H2O); ionization plates respectively positioned on upper and lower surfaces of the tourmaline intermediate layer interposed therebetween in the case body; and a conductive plate embedded in the tourmaline intermediate layer.

Abstract: A method for manufacturing a capacitor includes the steps of: sequentially laminating, on a substrate, a lower electrode layer, a dielectric layer and an upper electrode layer; forming a patterned mask layer on the upper electrode layer; patterning at least the upper electrode layer and the ferroelectric layer using the mask layer as a mask; removing the mask layer; and conducting a plasma treatment to contact plasma with an exposed surface of the dielectric layer.

Abstract: Capacitive coupling devices and methods of fabricating a capacitive coupling device are disclosed. The coupling device could include a stack of layers forming electrodes and at least one insulator. The insulator could include a region of doped silicon. The silicon could be doped with a species selected from Ce, Cr, Co, Cu, Dy, Er, Eu, Ho, Ir, Li, Lu, Mn, Pr, Rb, Sm, Sr, Tb, Tm, Yb, Y, Ac, Am, Ba, Be, Cd, Gd, Fe, La, Pb, Ni, Ra, Sc, Th, Hf, Tl, Sn, Np, Rh, U, Zn, Ag, and Yb in relief and forming roughnesses relative to the neighboring regions of the same level in the stack. The electrodes and the insulator form conformal layers above the doped silicon region.

Abstract: A multi-segment capacitor fabricated on a semiconductor substrate includes MxN capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.

Abstract: A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at % carbon. The method includes forming an opening through at least the support material where the opening has an aspect ratio of at least 20:1 within a thickness of the support material. After forming the opening, the method includes processing the support material to effect a reduction in conductivity, and forming a capacitor structure in the opening.

Abstract: The invention relates to a control cabinet for a wind turbine including a cabinet body (24) defining an inner chamber (23) and having a peripheral wall (40). One or more electric circuits (19, 20, 21) are arranged in the inner chamber (23) and one or more electric energy storage modules (50) which are secured to the cabinet body (24). The energy storage modules (50) are arranged on an exterior side of the cabinet body and are detachably secured thereto.

Abstract: A capacitor structure includes: a first electrode configured to include a plurality of openings; a second electrode formed in each center of the openings; and a dielectric layer formed to surround the second electrode and fill the openings of the first electrode.

Abstract: A multilayer capacitor array 1 comprises a capacitor element body 2 having first, second, third, and fourth inner electrodes 13 to 16, and first to fourth terminal electrodes 3 to 6 disposed on the outer surface of the capacitor element body 2 and respectively connected to the inner electrodes 13 to 16. The first and second inner electrodes 13, 14 form a first capacitor section C1, while the third and fourth inner electrodes 15, 16 form a second capacitor section C2. The multilayer capacitor array 1 is mounted to a circuit board such that the first and third terminal electrodes 3, 5 are connected to first leads 22, 23, while the second and fourth terminal electrodes 4, 6 are connected to a second lead 24.

Abstract: The present invention is directed to a microfabricated RF capacitor. The capacitor includes two signal wirebond pads configured for being connected to an electrical current source. The capacitor further includes two backbone structures which are connected to the wirebond pads and receive electrical current from the electrical current source via the wirebond pads, each backbone structure including a first backbone portion and a second backbone portion. The capacitor further includes a plurality of protrusions which are connected to the backbone portions of the backbone structures. The protrusions are spaced apart from each other and parallel to each other. Further, the protrusions are configured for distributing current received by the backbone structures and for promoting structural stability of the capacitor. The capacitor further includes a ground wall structure which may be configured for receiving ground current from a ground current source.

Abstract: An improved DC and/or audio-frequency output for RF paths has the following features: an earth connection is provided, in particular in the form of an electrically conductive housing (17), an output path (13) branches off from a connection point (117, 117?) on an RF path (3, 5), the output path (13) comprises a branch line (7, 9), originating from the connection point (117, 117?), in the form of a ?/4 line, where ? represents a wavelength which corresponds to a wavelength within the RF band to be transmitted on the RF path (3, 5), and having a capacitor device (27a, 27b), which is connected to the branch line (7, 9), in the form of a low-pass filter and/or an RF short, with at least one sealed dipole connection (127a, 127h) also being provided on the output path (13), in addition to the at least one capacitor device (27a, 27b).

Abstract: A discoidal feedthrough capacitor has its active electrode plates disposed within a dielectric body so that an edge of the active electrode plates is exposed at a surface of a through-hole for a conductive lead. The conductive lead is conductively coupled to the exposed edge of the electrode plates without an intervening conductive termination surface. Similarly, a ground electrode plate set of the feedthrough capacitor may have an edge exposed at the outer periphery of the capacitor for conductively coupling the exposed edge of the ground electrode plate to a conductive ferrule without an intervening conductive termination surface.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material for an electrolyte and a manufacturing method thereof is provided.

Abstract: Some embodiments of the invention include thin film capacitors formed in a package substrate of an integrated circuit package. At least one of the thin film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.

Abstract: A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.

Abstract: A method of forming a capacitor includes forming a cylindrical lower electrode structure having an internal support structure on a substrate, forming a dielectric layer on the cylindrical lower electrode structure and the support structure, and forming an upper electrode on the dielectric layer.

Abstract: An electronic device includes at least one trench capacitor that can also take the form of an inverse structure, a pillar capacitor. An alternating layer sequence of at least two dielectric layers and at least two electrically conductive layers is provided in the trench capacitor or on the pillar capacitor, such that the at least two electrically conductive layers are electrically isolated from each other and from the substrate by respective ones of the at least two dielectric layers. A set of internal contact pads is provided, and each internal contact pad is connected with a respective one of the electrically conductive layers or with the substrate. A range of switching opportunities is opened up that allows tuning the specific capacitance of the capacitor to a desired value.

Abstract: A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.

Abstract: A method that employs a novel combination of conventional fabrication techniques provides a ceramic short-resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The method allows thinner and more flexible ceramic capacitors to be made. The method includes forming a first thin metal layer on a substrate; depositing a thin, ceramic dielectric layer over the metal layer; depositing a second thin metal layer over the dielectric layer to form a capacitor exhibiting a benign failure mode; and separating the capacitor from the substrate.

Abstract: A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material for an electrolyte and a manufacturing method thereof is provided.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material for an electrolyte and a manufacturing method thereof is provided.