Abstract: A plurality of thin film capacitor parts are provided in respective regions each surrounded by a plurality of gate metal lines (12) and a plurality of data signal lines (11) intersecting perpendicularly to each other on a glass substrate (1), and each of the thin film capacitor parts has a lower electrode (3), a gate insulating film, and an upper electrode (5), which are provided in this order. Adjacent upper electrodes (5) are electrically connected to each other via a corresponding first wire (8), which is positioned above the adjacent upper electrodes (5) and intersects with one of the data signal lines (11). This makes it possible to provide a thin film capacitor, which includes the lower electrodes (3) each having the same thickness in a center portion and an edge portion, and the upper electrodes (5) that are connected to each other by using a corresponding connecting wire with low possibility of disconnection.

Abstract: A device for saving electric power of the present invention comprises a case body; a tourmaline intermediate layer accommodated in the case body, which is a mixture layer of tourmaline powder, permanent magnet powder and moisture (H O); ionization plates respectively positioned on upper and lower surfaces of the tourmaline intermediate layer interposed therebetween in the case body; and a conductive plate embedded in the tourmaline intermediate layer.

Abstract: A digitally controlled capacitor includes a first set of N capacitors, wherein the first set has a first capacitance value and each of the M capacitors has a second capacitance value, and at least one second set of N capacitors. The second set has the first capacitance value and each of the N capacitors has a third capacitance value that is greater than the second capacitance value. M and N are integers greater than one and M is not equal to N.

Abstract: A through-type multilayer capacitor array comprises a capacitor body, and two first signal terminal electrodes, two second signal terminal electrodes, two grounding terminal electrodes, a first outer connecting conductor, and a second outer connecting conductor. The capacitor body includes a grounding inner electrode, and first to fourth signal inner electrodes. The grounding inner electrode is arranged to oppose the first or second signal inner electrode with an insulator layer in between and oppose the third or fourth signal inner electrode with an insulator layer in between while being connected to the grounding terminal electrodes. The first signal inner electrode is connected to the first signal terminal electrodes and first outer connecting conductor. The third signal inner electrode is connected to the second signal terminal electrodes and the second outer connecting conductor. The second and fourth signal inner electrodes are respectively connected to the first and second outer connecting conductor.

Abstract: An exemplary embodiment providing one or more improvements includes a capacitor with a segmented end electrode and methods for segmenting an end electrode of a capacitor for reducing or eliminating instances of thermally induced damage of the capacitor.

Abstract: A feedthrough terminal assembly for active implantable medical devices includes a structural wire bond pad for a convenient attachment of wires from either the circuitry inside the implantable medical device or wires external to the device. Direct attachment of wire bond pads to terminal pins enables thermal or ultrasonic bonding of lead wires, while shielding the capacitor or other delicate components from the forces applied to the assembly during attachment of the wires.

Abstract: According to one embodiment, a capacitor arrangement support system includes a resonance analysis module configured to perform a resonance analysis based on data of a component producing electromagnetic radiation, a resonance point extraction module configured to extract a resonance point from an analysis result of the resonance analysis module, an electromagnetically radiated energy analysis module configured to analyze the ease of collection of electromagnetically radiated energy with respect to a resonance point extracted by the resonance point extraction module, a determination module configured to determine whether or not an absolute value of a value showing the ease of collection of electromagnetically radiated energy is larger than a preset absolute value, and a capacitor arrangement module configured to arrange a capacitor for suppressing electromagnetic radiation at a resonance point where the determination module determines that data of the component is larger the preset absolute value.

Abstract: A communications device (125) and capacitor assembly (100) having a first capacitor electrode formed by a conductive keypad mount (110) coupled to a conductive part of a housing (120) of the communications device (125). The keypad mount (110) has keypad apertures (210) aligned with keys (140) of a keypad (145) and the conductive part of the housing (120) has an external housing covering insulator in the form of the window sub-housing (121). There is a circuit board (130) providing support for a second capacitor electrode (150). The circuit board (130) has an array of keypad actuators (135) aligned with the keys (140).

Abstract: Terminal pins comprising an outer coating of palladium coating a core material other than of palladium for incorporated into feedthrough filter capacitor assemblies are described. The feedthrough filter capacitor assemblies are particularly useful for incorporation into implantable medical devices such as cardiac pacemakers, cardioverter defibrillators, and the like, to decouple and shield internal electronic components of the medical device from undesirable electromagnetic interference (EMI) signals.

Abstract: A method of forming a conductor on a substrate including steps of depositing tantalum on a glass layer of the substrate; oxidizing the tantalum; and depositing a noble metal on the oxidized tantalum to form the conductor. The method can be used to form a ferroelectric capacitor or other thin film ferroelectric device. The device can include a substrate comprising a glass layer; and an electrode connected to the glass layer. The electrode comprising can include a noble metal connected to the glass layer by an adhesion layer comprising Ta2O5.

Abstract: A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.

Abstract: A sintered body electrode for a sintered body electrode capacitor, which enables production of a solid electrolytic capacitor having a good capacitance appearance factor, including at least one member selected from an earth-acid metal, an alloy mainly comprising an earth-acid metal, an electrically conducting oxide of an earth-acid metal, and a mixture of two or more thereof. The value (pseudo-closed porosity) obtained by dividing the difference between the volume of a sintered body measured under atmospheric pressure and the volume measured in a vacuum, which are determined according to the Archimedes method, by the volume measured under atmospheric pressure is 11% or less. Also disclosed is a solid electrolytic element using the sintered body, a solid electrolytic capacitor using the element and use of the solid electrolytic capacitor.

Abstract: A flat type capacitor-use polypropylene film having a Ad(thickness determined by micrometer method—thickness determined by weighing method) of 0.05-0.2 ?m and a lengthwise shrinkage dimensional change rate of 3% or less, or a flat type capacitor-use polypropylene film having a ?d of 0.1-0.3 ?m and a lengthwise F5 value of 50 MPa or more, and a flat type capacitor using it. A film excellent in handling ability in a capacitor element winding process is obtained, and a small, a large-capacity flat type capacitor excellent in withstand voltage characteristics such as self-recovering property, and used suitably under a high rated voltage, is obtained.

Abstract: A capacitor includes a hollow capacitor element formed by rolling a pair of flat sheet-like electrodes and, with separators interposed therebetween, a bottom-closed metallic casing receiving the capacitor element and a drive electrolyte therein, and an opening-sealing plate sealing an opening portion of the metallic casing, the opening-sealing plate having an external connection terminal. A rubber-like elastic member is provided on a surface of the opening-sealing plate at a peripheral edge portion thereof, and an electrically-insulating layer is formed on the metallic casing to cover at least a region extending from the open end of the metallic casing to a recess provided for fixing the opening-sealing plate, and the rubber-like elastic member is pressed by the open end portion of the metallic casing.

Abstract: Systems and methods are provided for a stacked die configuration of a high isolation switch and a rejection filter where transmit and receive signals are desired to have a high out-of-band rejection and a low loss band-pass region. In some aspects of the invention the high isolation switch is a double pole double throw switch modified to operate as a high isolation single pole double throw (SPDT) switch. In some aspects of the invention the high isolation switch is a conventional high isolation SPDT switch. The switch is mounted on a low profile rejection filter having metallization on a portion of an outer surface of the rejection filter. The metallization on the outer surface of the rejection filter provides an AC ground layer in close proximity to the switch that provides a short coupling path between the switch and the AC ground. The resulting switch-filter component also results in a smaller footprint than if the two devices were mounted individually and/or adjacently.

Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set includes a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.

Abstract: An electrical storage device, such as a capacitor, which includes a high surface area material such as zeolite as a substrate, a suitable dielectric layer proximate to the substrate, and necessary electrically conductive layers. The substrate is non-planar and has a rigid, sponge-like internal structure with a high surface area to volume ratio defined by nanometer scale openings connected by passageways.

Abstract: A capacitor having a first nickel electrode. A BCTZ dielectric covers a side of the first nickel electrode. A second nickel electrode sandwiches the BCTZ.

Abstract: Apparatus and method for depositing a banding material on the interior substrate of a tubular device, and the products formed therefrom. The tubular device is, generally, of relatively small diameter and comprises at least one band deposited from a first composition on the interior substrate. When the tubular device is a tubular capacitor and the band is a plating mask, the tubular capacitor comprises at least two electrodes deposited on the substrate in the presence of a deposited plating mask and comprises at least one conductive layer, deposited from a first composition, on the substrate and separated by the plating mask.

Abstract: An on-chip bypass capacitor and method of manufacturing the same, the on-chip bypass capacitor including at least two capacitor arrays, each capacitor array including a first layer connecting the at least two capacitor arrays in series, each capacitor array including a plurality of capacitors, each of the plurality of capacitors including a second layer connecting the plurality of capacitors in parallel. The on-chip bypass capacitor may be part of a chip which also includes a memory cell array including at least one cell capacitor.

Abstract: A power supply apparatus and a power supply method are described, wherein the non-polar characteristics of the electrodes of a capacitor is utilized to improve the energy utilization efficiency of a battery through reciprocating switches of polarity connection between the battery and the capacitor. The voltages of the capacitors can also stay at a near constant level using the polarity reversal mechanism.

Abstract: A stacked capacitor includes a dielectric member, a plurality of internal electrodes, and a plurality of extraction electrodes. The dielectric member is a stacked member formed of stacked dielectric layers and having at least one side surface. The internal electrodes are stacked alternately with the dielectric layers and have first edges positioned near the side surface. Each of the extraction electrodes leads from each first edge to the side surface. Each of the extraction electrodes has a width W on the side surface in a direction orthogonal to the stacking direction and is separated from adjacent extraction electrodes by a distance G on the side surface in the direction orthogonal to the stacking direction. The width W and distance G are set such that 1.2?W/G?4.0.

Abstract: A C-shaped combination capacitor assembly has a C-shaped shell, multiple capacitors, two conducting wires, two lead wires and encapsulant. The capacitors are mounted in the C-shaped shell. The conducting wires connect the capacitors in parallel. The two lead wires connect respectively to the conducting wires and protrude from the C-shaped shell. The encapsulant fills the C-shaped shell and covers and seals the capacitors, the conducting wires and the lead wires inside the C-shaped shell.

Abstract: An energy conditioning structure comprised of any combination of multilayer or monolithic energy conditioners with operable conductors, all selectively arranged and shielded for attachment to at least a conductive substrate.

Abstract: A capacitor for use within a microelectronic product employs a first capacitor plate layer that includes a first series of horizontally separated and interconnected tines. A capacitor dielectric layer separates the first capacitor plate layer from a second capacitor plate layer. The second capacitor plate layer includes a second series of horizontally separated and interconnected tines horizontally interdigitated with the first series of horizontally separated and interconnected tines. The capacitor is formed employing a self-aligned method and the capacitor dielectric layer is formed in a serpentine shape.

Abstract: A MIM (metal-insulator-metal) capacitor is provided with a substrate; a first metal area; a second metal area formed between the substrate and the first metal area; and a first insulating layer formed between the first metal area and the second metal area; wherein a capacitance value is determined by opposing surface areas of the first metal area and the second metal area; and the MIM capacitor is further provided with: a third metal area formed between the second metal area and the substrate; and a second insulating layer formed between the third metal area and the second metal area; wherein the third metal area is connected to a ground potential.

Abstract: A tunable capacitor includes a substrate, a stationary electrode and a movable electrode supported by the substrate, piezoelectric actuators that are supported by the substrate and drive the movable electrode, and a dielectric layer interposed between the stationary electrode and the movable electrode.

Abstract: An electronic circuit device having a power-supply structure capable of supporting fast signals in and above a GHz band is offered. A driver transistor is formed in a surface of a semiconductor substrate. Power-supply/ground pair transmission lines which provide the driver transistor with power and signal/ground pair transmission lines which transmit signals to a receiver are formed on the semiconductor substrate. The power-supply/ground pair transmission lines are connected to a drain layer of the driver transistor and a P+ layer in a P well. The signal/ground pair transmission lines are connected to a source layer of the driver transistor and a P+ layer in the P well.

Abstract: A voltage supply bypass capacitor for use with a semiconductor integrated circuit chip or module comprising a ferroelectric dielectric having electromechanical properties designed to provide maximum losses at selected frequencies.

Abstract: A multi-level metal interconnect structure and method for forming the same for improving a resistance of CMOS transistors to electrostatic discharge (ESD) transient events is disclosed. A semiconductor device including at least one NMOS transistor electrically connected along at least one circuit pathway to an input/output signal source and a reference voltage potential; and, electrically connecting at least the input/output signal source to the at least one NMOS transistor with a metal interconnect line extended in length by compacting at least a portion of the metal interconnect line length portion into a serpentine shape within a predetermined volume of the semiconductor device.

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates.

Abstract: A dielectric ceramic includes, in composition, a perovskite-type compound having the general formula ABO3 containing Ba, Ca and Ti, and an additive component containing Si, R(La or the like), and M (Mn or the like), the additive component not being solid-dissolved and, moreover, the major component existing in at least 90% of the cross-section of each of the crystal grains of which the number is equal to at least 85% of that of all of the crystal grains contained in the dielectric ceramic, at least the Ba, the Ca, the Ti, the Si, the R, and the M being contained at at least 85% of the analytical points in the crystal grain boundaries of the dielectric ceramic.

Abstract: A method of fabricating an SrRuO3 thin film is disclosed. The method utilizes a multi-step deposition process for the separate control of the Ru reagent, relative to the Sr reagent, which requires a much lower deposition temperature than the Sr reagent. A Ru reagent gas is supplied by a bubbler and deposited onto a substrate. Following the deposition of the Ru reagent, the Sr liquid reagent is vaporized and deposited onto the Ru layer.

Abstract: A method and apparatus is provided that pertains to a low inductance capacitor. The capacitor has a first surface electrically interconnected to a plurality of conductive electrodes and one or more second surfaces electrically interconnected to a plurality of electrodes interposed between the electrodes electrically interconnected to the first conductive surface. A dielectric layer separates the layered plurality of electrodes. The one or more second conductive surfaces are positioned within the body of the layered electrodes, such that the distance between the terminations of the first conductive surface and the one or more second conductive surfaces is shortened to lower inductance.

Abstract: Methods for fabricating a capacitor in a microelectronic device utilizing a sputter deposition technique for forming a capacitor dielectric material on a copper-containing plate of the capacitor. Such a sputter deposition technique can be achieved at about room temperature, which should not induce stresses on the copper-containing plate, and, thus, should not generate hillocks.

Abstract: A semiconductor device (10) is formed on a semiconductor substrate (12) whose surface (24) is formed with a trench (18). A capacitor (20) has a first plate (22) formed over the substrate surface with first and second portions lining first and second sidewalls (25) of the trench, respectively. A second plate (35, 38) is formed over the first plate and extends into the trench between the first and second portions.

Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.

Abstract: A decoupling capacitor suitable for use with 0.11 micron or less, for example 0.09 micron, CMOS technology is provided herein. The decoupling capacitor includes a decoupling structure that minimizes leakage current associated with the decoupling capacitor.

Abstract: In a semiconductor chip are arranged power pads, ground pads and signal pads. A ground line is provided which is formed as one in the vicinity of the chip and branches off at some distance from the chip. Signal lines and power lines are each formed over one of the branched ground lines. The signal lines and the power lines are extended radially together with the underlying ground lines. Each of the signal lines and the power lines are extended together with the corresponding ground line to form a stacked pair line.

Abstract: A structure which exhibits magnetic properties when it receives electromagnetic radiation is formed from an array of capacitive elements each of which is smaller, and preferably much smaller, than the wavelength of the radiation. Each capacitive element has a low resistance conducting path associated with it and is such that a magnetic component of the received electromagnetic radiation induces an electrical current to flow around the path and through the associated element. The creation of internal magnetic fields generated by the flow of the induced electrical current gives rise to the structure's magnetic properties.

Abstract: A voltage supply bypass capacitor for use with a semiconductor integrated circuit chip or module comprising a ferroelectric dielectric having electromechanical properties designed to provide maximum losses at selected frequencies.

Abstract: A method for configuring a bypass capacitor for use in conjunction with an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes selecting mechanical dimensions for the bypass capacitor, the mechanical dimensions causing the bypass capacitor to exhibit electrical losses at a clock frequency of the integrated circuit device. The bypass capacitor preferably includes a ferroelectric dielectric material. In addition, the selection of mechanical dimensions for the bypass capacitor determines a mechanical resonance frequency for the bypass capacitor, with the mechanical resonance frequency corresponding to the clock frequency.

Abstract: A capacitor circuit has a first electrode, a second electrode, and a dielectric interposed between the first and second electrodes, and a plurality of first wiring lines, each functioning as the first electrode, and a plurality of second wiring lines, each functioning as the second electrode, are formed alternately one adjacent to the other within the same wiring layer. With this arrangement, the capacitance of the capacitor circuit can be made large without incurring an increase in the area it occupies.

Abstract: A plastic film capacitor shield wherein the shield is secured to an outer surface of plastic film capacitor. The shield is sufficient to protect the plastic film capacitor from excessive radiant infrared energy during infrared reflow soldering which could damage the plastic film capacitor. The plastic film capacitor shield can be composed of many different materials such as electrical grade tape, electrical grade plastic, metal tape, or epoxy. The shield can be attached to the capacitor in various ways, which includes: securing a shield to an upper surface of the capacitor; having a shield on an upper and lower surface of the capacitor, wrapping and securing a shield to the plastic film capacitor on four sides of the capacitor; securing a shield on all sides of the capacitor; and securing a combination of different shields to the outer surfaces of the capacitor.

Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.

Abstract: A multi-layer metallization capacitive structure is provided to a conductive line, such as a power line or signal transmission line in an integrated circuit, where the undesired effect of simultaneous switching noise (SSN) is adverse due to rapid switching of pulses in a digital signal. The multi-layer metallization capacitive structure can help reduce the SSN effect in the integrated circuit by providing at least one metallization layer which extends substantially beneath the conductive line; and at least one dielectric layer sandwiched between the power line and the metallization layer. The multi-layer metallization capacitive structure has an optimal effect if the metallization layer is designed to be precisely equal in width to the power line. The multi-layer metallization capacitive structure has an advantage over the prior art in that it can be formed together with the processing for forming multiple interconnects in the integrated circuit without the need to devise additional processes.

Abstract: A capacitor network has an uncomplicated construction enabling the capacitance of the capacitor network to be easily increased or decreased. The capacitor network has a plurality of component capacitors formed from two metallic foil layers on opposite sides of a printed circuit board interconnected by lines disposed on both sides of said printed circuit board. The component capacitors of the capacitor network are arranged into at least one series circuit section and at least one parallel circuit section. The series circuit section includes two or more component capacitor, each including at least one component capacitor, connected in series. The parallel circuit section includes two or more parallel-connected component capacitor circuits, each including at least one component capacitor.