Material Patents (Class 361/305)
  • Patent number: 11123457
    Abstract: A material comprising an ionically conducting polymer (ICP) positioned between and in direct contact with two electronically conducting polymers (ECP).
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 21, 2021
    Assignee: SUPERDIELECTRICS LTD
    Inventor: Donald James Highgate
  • Patent number: 11114239
    Abstract: A device includes a leadframe and an electronic component. The leadframe includes a first leadframe element having a first surface and a second leadframe element adjacent to the first leadframe element, the first and second leadframe elements being separate from one another, the second leadframe element having a second surface. A first flange extends from a first outer edge of the first leadframe element and extends away from the first surface of the first leadframe element. A second flange extends from a second outer edge of the second leadframe element and extends away from the second surface of the second leadframe element. The electronic component is coupled to the first and second surfaces of the first and second leadframe elements such that the first and second flanges are located at opposing first and second sidewalls of the electronic component.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: September 7, 2021
    Assignee: NXP B.V.
    Inventors: Chayathorn Saklang, Wiwat Tanwongwan, Amornthep Saiyajitara, Chanon Suwankasab
  • Patent number: 11101065
    Abstract: An electronic component includes a body having an internal electrode disposed therein, and an external electrode disposed on the body and connected to the internal electrode, wherein in a cross section of the body cut in length and thickness directions, the external electrode includes a first electrode layer disposed below the body and a second electrode layer covering at least the first electrode layer and a side portion of the body, and the internal electrode is connected to the second electrode layer through the side portion of the body.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 24, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ji Sook Yoon, Sang Ho Shin, Byung Kug Cho, Sung Jin Park, Jae Wook Lee
  • Patent number: 11088140
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate comprising an array region and a peripheral region surrounding the array region, a plurality of capacitor structures positioned above the peripheral region of the substrate, a first semiconductor element positioned above the peripheral region and having a first threshold voltage, and a second semiconductor element positioned above the peripheral region and having a second threshold voltage. The first threshold voltage of the first semiconductor element is different from the second threshold voltage of the second semiconductor element.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: August 10, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11062849
    Abstract: A method of manufacturing a multilayer ceramic electronic component includes: preparing a dielectric magnetic composition including base material powder particles including BaTi2O5 or (Ba(1-x)Cax)Ti2O5 (0?x<0.1), the base material powder particles having surfaces coated with one or more of Mg, Mn, V, Ba, Si, Al and a rare earth metal; preparing ceramic green sheets using dielectric slurry including the dielectric magnetic composition; applying an internal electrode paste to the ceramic green sheets; preparing a green sheet laminate by stacking the ceramic green sheets to which the internal electrode paste is applied; and preparing a ceramic body including dielectric layers and a plurality of first and second internal electrodes arranged to face each other with each of the dielectric layers interposed therebetween by sintering the green sheet laminate.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Du Won Choi, Seok Kyoon Woo, Ji Hong Jo
  • Patent number: 11011307
    Abstract: An electronic component includes a laminate and an external electrode provided on an end surface of the laminate. The external electrode includes a Ni layer provided on the end surface, a Ni—Sn alloy layer provided on the Ni layer, and a resin layer that is provided on the Ni—Sn alloy layer and includes metal grains including Sn grains. The Ni layer and the Ni—Sn alloy layer reduce or prevent intrusion of moisture from the external electrode into an interior of the laminate, and the resin layer reduces or prevents generation of cracks when a bending stress is applied to the external electrode.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: May 18, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Toshihiro Harada
  • Patent number: 10981833
    Abstract: A multi-layered ceramic electronic component has a ceramic body including a dielectric layer and an internal electrode, and an external electrode formed outside of the ceramic body and electrically connected to the internal electrode. The internal electrode includes a conductive metal and a fiber-shaped ceramic additive. For example, the fiber-shaped ceramic additive can include barium titanate (BaTiO3) and, optionally, dysprosium (Dy) and/or barium (Ba). The fiber-shaped ceramic additive may have a diameter of 10 to 200 nm, and a ratio of length to diameter of 10 to 100.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 20, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byung Yong Wang, Kwang Sic Kim, Ji Hun Lee
  • Patent number: 10978731
    Abstract: A battery comprising a high capacity electrode construction may include layering of the electrode and/or low active material loading.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 13, 2021
    Assignee: HHELI, LLC
    Inventor: Paige L. Johnson
  • Patent number: 10950389
    Abstract: A thin-film capacitor satisfies a relationship of CTE1>CTE2>CTE3 regarding a linear expansion coefficient CTE1 of a base, a linear expansion coefficient CTE2 of a capacitance unit, and a linear expansion coefficient CTE3 of a barrier layer. The inventors have newly found that in a case in which such a relationship is satisfied, when a temperature falls from a deposition temperature, cracking occurring in the capacitance unit of the thin-film capacitor is prevented, and cracking occurring in the barrier layer is also prevented.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: March 16, 2021
    Assignee: TDK CORPORATION
    Inventors: Daiki Ishii, Kazuhiro Yoshikawa, Koichi Tsunoda, Mitsuhiro Tomikawa, Junki Nakamoto, Kenichi Yoshida
  • Patent number: 10861651
    Abstract: A multilayer capacitor includes a body including an internal electrode alternately disposed with a dielectric layer, and an external electrode disposed on the body. The external electrode includes a first electrode layer contacting the internal electrode, an oxide layer disposed on the first electrode layer and including a metal oxide and glass, and a second electrode layer disposed on the oxide layer.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Ho Lee, Duk Hyun Chun, Myung Jun Park, Eun Jin Kim, Hye Min Bang
  • Patent number: 10840008
    Abstract: An electronic component includes an electronic component body and an external electrode. The external electrode is disposed on the electronic component body. The external electrode includes a Pd plating layer and a Ni plating layer. The Pd plating layer defines an outermost layer. The Ni plating layer is disposed inside the Pd plating layer. The Ni plating layer is partly exposed from the Pd plating layer.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: November 17, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuaki Kainuma, Seiji Katsuta, Akihiro Motoki
  • Patent number: 10832871
    Abstract: A wet electrolytic capacitor that contains a cathode, fluidic working electrolyte, and anode that includes a sintered porous pellet is provided. A dielectric layer is also formed on a surface of the pellet and within its pores through anodic oxidation. The present inventors have discovered that through selective control over the anodic oxidation process, a substantially amorphous, low crystalline dielectric layer can be formed which, among other things, exhibits a leakage current that is smaller than previously thought possible for the high voltage capacitors employed in implantable medical devices.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: November 10, 2020
    Assignee: AVX Corporation
    Inventors: Jan Petrzilek, Ilja Michalin
  • Patent number: 10770227
    Abstract: A capacitor includes a body including dielectric layers and internal electrodes; and external electrodes disposed on the body. The capacitor includes Sn, the Sn having an alpha particle emission rate equal to or less than 0.02 cph/cm2.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seon Jae Mun, Jae Yeol Choi, Seung Heui Lee, Jong Ho Lee, Kyoung Jin Cha
  • Patent number: 10770232
    Abstract: A multilayer electronic component for enhancing damp proof reliability includes: a capacitor body including a plurality of dielectric layers, and first and second internal electrodes, alternately disposed across the dielectric layers to expose one end of the first and second electrodes through third and fourth surfaces of the capacitor body; first and second conductive layers disposed on the third and fourth surfaces of the capacitor body and connected to the first and second internal electrodes, respectively; first and second plating layers covering surfaces of the first and second conductive layers; and a plurality of coating layers configured in a multilayer structure on a surface of the capacitor body to expose the first and second plating layers and having an entire thickness of 10 nm to 200 nm.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Hun Han, Sung Min Cho, Dong Joon Oh
  • Patent number: 10734164
    Abstract: A capacitor that includes a conductive metal substrate having a high porosity portion and a low porosity portion with a porosity lower than that of the high porosity portion; a dielectric layer on the conductive metal substrate; an upper electrode on the dielectric layer; an upper extended electrode on one principal face of the conductive metal substrate and electrically connected to the upper electrode; a lower extended electrode on the other principal face of the conductive metal substrate and electrically connected to the conductive metal substrate; and insulating layer on the upper electrode at a position overlapping with the low porosity portion through the dielectric layer and the upper electrode.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 4, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yoshifumi Saito
  • Patent number: 10679790
    Abstract: A multilayer ceramic capacitor includes a ceramic body including a dielectric layer and having first and second surfaces opposing each other in a width direction, third and fourth surfaces connecting the first and second surfaces in a length direction, and fifth and sixth surfaces opposing each other in a thickness direction, internal electrodes disposed inside the ceramic body, exposed through the first and second surfaces, and having one end portion exposed through the third or fourth surface, and first and second side margin portions disposed on edges of the internal electrodes, exposed through the first and second surfaces. In a cross-section cut along a width-thickness plane of the ceramic body, an area of an oxide region disposed on the edges of the internal electrodes is less than 10% of an overall area of the internal electrodes exposed through the first and second surfaces.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 9, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Park, Jang Yeol Lee, Ji Hong Jo
  • Patent number: 10597025
    Abstract: Methods and systems for operating a hybrid driveline that includes an engine and an electric machine are presented. In one non-limiting example, the engine and electric machine are operated according to a solution of a Hamiltonian that includes a first co-state and a second co-state, an engine fuel flow parameter, a rate of change of battery state of charge parameter, and an emissions flow rate parameter.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: March 24, 2020
    Assignee: Ford Global Technologies, LLC
    Inventors: Kukhyun Ahn, Mohammad Shakiba-herfeh, David Richens Brigham, Alexander T. Zaremba, Mark John Jennings
  • Patent number: 10566415
    Abstract: Provided is a capacitor structure including a substrate, a cup-shaped lower electrode, a top supporting layer, a capacitor dielectric layer, and an upper electrode. The cup-shaped lower electrode is located on the substrate. The top supporting layer surrounds the upper portion of the cup-shaped lower electrode. The top supporting layer includes a high-k material. Surfaces of the cup-shaped lower electrode and the top supporting layer are covered by the capacitor dielectric layer. A surface of the capacitor dielectric layer is covered by the upper electrode.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: February 18, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Cheol Soo Park, Ming-Tang Chen, Chun-Chieh Wang
  • Patent number: 10526487
    Abstract: Solvents for macromolecules generally believed to be insoluble in their pristine form are identified by generation of a “solvent resonance” in the relationship between solvent quality (deduced by Rayleigh scattering) and an intrinsic property of solvents. A local extreme of the solvent resonance identifies the ideal intrinsic property of an ideal solvent which may then be used to select a particular solvent or solvent combination. A solvent for graphene is used in the production of transparent conductive electrodes.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: January 7, 2020
    Assignee: WiSys Technology Foundation
    Inventors: James P. Hamilton, Philip V. Streich
  • Patent number: 10502638
    Abstract: A temperature detector is configured to detect the temperature of a housing while in contact with the housing, and a spring pin is in contact with the temperature detector in a separable manner. Thus, at mounting of the temperature detecting device on an electronic device, it is possible to fix the temperature detector to the housing, and the spring pin to a circuit board of the electronic device. At disassembly of the electronic device, it is easy to separate the spring pin from the temperature detector by removing, from the housing, the spring pin together with the circuit board. At assembly of the electronic device, it is easy for the spring pin to contact the temperature detector by attaching, to the housing, the spring pin together with the circuit board.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: December 10, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tadamasa Miura, Kazuto Miyagawa, Akihito Naito
  • Patent number: 10483346
    Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-hyung Nam, Bong-Soo Kim, Yoosang Hwang
  • Patent number: 10468662
    Abstract: An electrode for a secondary battery including an electrode laminated assembly that has a configuration in which electrodes and a separator are laminated, includes current collector 3 and active material layer 2 formed on a surface of current collector 3. Active material layer 2 includes a thick-layer portion and a thin-layer portion that is positioned at an edge portion of the active material layer and that is smaller in thickness than the thick-layer portion, and is formed by discharging slurry containing an active material from discharge port 12a of die head 12 toward the surface of current collector 3, the slurry being supplied to die head 12 through coating valve 13.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: November 5, 2019
    Assignee: Envision AESC Energy Devices Ltd.
    Inventors: Masanori Hirai, Takashi Nakajima, Tetsuya Sato
  • Patent number: 10403434
    Abstract: A capacitor component includes a body, and first and second external electrodes formed on external surfaces of the body. The body includes a first connection electrode connected to the first external electrode, a second connection electrode disposed on the first connection electrode to partially cover the first connection electrode and connected to the second external electrode, and a porous capacitor portion disposed to cover the first and second connection electrodes and connected to each of the first and second connection electrodes.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Il Lee, Byeong Cheol Moon
  • Patent number: 10395838
    Abstract: In a multilayer ceramic capacitor, A>B is satisfied by an atomic concentration ratio B of Si to Cu in a first organic layer disposed on a first base electrode layer located on a first end surface, an atomic concentration ratio A of Si to Cu in the first organic layer disposed on the first base electrode layer located on a first principal surface and a second principal surface, and an atomic concentration ratio A of Si to Cu in the first organic layer located directly on the first principal surface and the second principal surface.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: August 27, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroshi Asano, Nobuyasu Hamamori
  • Patent number: 10373759
    Abstract: A multilayer ceramic electronic component includes a ceramic body including dielectric layers and first and second internal electrodes alternately stacked with each of the dielectric layers interposed therebetween. First and second external electrodes are disposed on outer surfaces of the ceramic body, connected to the first and second internal electrodes respectively, and disposed to cover at least five of eight corners of the ceramic body. The first and second external electrodes include, respectively, first and second base electrode layers at least partially in contact with the outer surfaces of the ceramic body and first and second plating layers disposed to cover the first and second base electrode layers, respectively. The first and second plating or base electrode layers have one or more to three or less holes positioned adjacent to one or more to three or less of the eight corners of the ceramic body.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hye Young Choi, Jong Ho Lee, Eui Hyun Jo, Jang Yeol Lee, Jin Woo Lee, Hyun Hee Gu
  • Patent number: 10366838
    Abstract: A laminated ceramic electronic component that includes a laminate having a plurality of dielectric layers and a plurality of internal electrode layers laminated together. External electrodes having underlying electrode layers and plating layers are formed on both end surfaces of the laminate. When a cross-section including the underlying electrode layers is observed, the underlying electrode layers contain a plurality of Cu crystals and glass, and an average value of lengths of demarcation lines of the Cu crystals having different crystal orientations is 3 ?m or less.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 30, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Nishisaka, Masato Kimura
  • Patent number: 10297390
    Abstract: An element body includes first and second end surfaces opposing each other in a first direction, first and second side surfaces opposing each other in a second direction, and first and second principal surfaces opposing each other in a third direction. The length of the element body in the third direction is shorter than that of the element body in the first direction and is shorter than that of the element body in the second direction. A pair of first external electrodes is disposed at both ends of the element body in the first direction. Each of the first external electrodes includes a first conductor part disposed on one main surface and a second conductor part disposed on the end surface and coupled to the first conductor part. The porosity of the first conductor part is smaller than that of the second conductor part.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: May 21, 2019
    Assignee: TDK CORPORATION
    Inventors: Fumiaki Satoh, Takehisa Tamura, Yuma Hattori, Toru Onoue, Daisuke Himeta, Ken Morita, Takuto Okamoto
  • Patent number: 10290861
    Abstract: A composite positive active material includes: a composite including a first metal oxide represented by Formula 1 and having a layered structure, and a second metal oxide having at least one crystal structure selected from a layer structure, a perovskite structure, a rock salt structure, and a spinel structure, wherein a content of the second metal oxide is greater than 0 and equal to or less than 0.2 moles, per mole of the composite, LiNixM11-xO2-eM2e??Formula 1 wherein, in Formula 1, M1 is at least one element selected from Group 4 to Group 14 of the Periodic Table of the Elements; Ma is at least one element selected from F, S, Cl, and Br; 0.7?x<1; and 0?e<1. Also, a positive electrode including the composite positive active material, and a lithium battery including the positive electrode.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 14, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SAMSUNG SDI CO., LTD.
    Inventors: Byungjin Choi, Andrei Kapylou, Donghan Kim, Jinhwan Park, Jayhyok Song, Sungjin Ahn, Donghee Yeon, Byongyong Yu
  • Patent number: 10292269
    Abstract: An inductor-capacitor (LC) filter includes an inductor having an asymmetric shape including at least one turn. The LC filter also includes serial capacitors coupled to the inductor at only one end of a continuous portion of the inductor. The serial capacitors continues the shape of the inductor. The capacitors are outside of a footprint of the continuous portion of the inductor.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: May 14, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Niranjan Sunil Mudakatte, Changhan Hobie Yun, Jonghae Kim, Xiaoju Yu, Nosun Park, Mario Francisco Velez
  • Patent number: 10269492
    Abstract: A multilayer ceramic electronic component and a method of manufacturing the same are provided. The multilayer ceramic electronic component includes: a ceramic body including dielectric layers; and internal electrodes disposed on the dielectric layers within the ceramic body and containing a ceramic material trapped therein. The ceramic material is a dielectric material doped with an additive.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: April 23, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kum Jin Park, Chang Hak Choi, Chi Hwa Lee, Min Gi Sin, Woo Sup Kim, Jong Hoon Yoo
  • Patent number: 10204744
    Abstract: A capacitor that includes a porous metallic base material; a phosphorus-containing layer on the porous metallic base material; a dielectric layer on the phosphorus-containing layer; and an electrode on the dielectric layer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: February 12, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takeo Arakawa, Hiromasa Saeki, Noriyuki Inoue, Naoki Iwaji
  • Patent number: 10163569
    Abstract: A multilayer ceramic capacitor includes: a pair of external electrodes; a first internal electrode containing a base metal and coupled to one of the external electrodes; a dielectric layer stacked on the first internal electrode and containing a ceramic material and the base metal; and a second internal electrode stacked on the dielectric layer, containing the base metal, and coupled to another one of the external electrodes, wherein a concentration of the base metal in each of five regions is within ±20% of an average of the concentrations of the base metal in the five regions, the five regions being obtained by dividing a region from a location 50 nm away from the first internal electrode of the dielectric layer to a location 50 nm away from the second internal electrode of the dielectric layer in a stacking direction between the first and second internal electrodes equally into five.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Koichiro Morita, Minoru Ryu, Katsuya Taniguchi, Yoshiki Iwazaki
  • Patent number: 10134533
    Abstract: A multilayer ceramic capacitor includes a multilayer body that includes ceramic layers and inner conductor layers arranged in a stacking direction and that includes a first surface in which the inner conductor layers are exposed, and an outer electrode on the first surface of the multilayer body. The inner conductor layers contain Ni. The outer electrode includes a base layer that directly covers at least a portion of the first surface and is connected to the inner conductor layers. The base layer contains a metal and glass and includes a Ni diffusion portion connected to the inner conductor layers, the Ni diffusion portion containing Ni. A ratio of a diffusion depth of the Ni diffusion portion to a thickness of the base layer is smaller on two of the inner conductor layers that are located outermost than on other inner conductor layers.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: November 20, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masato Kimura, Yasuhiro Nishisaka
  • Patent number: 10062512
    Abstract: A multilayer ceramic electronic component has a dimension in a longitudinal direction of no less than about 0.12 mm and no more than about 0.27 mm, a dimension in a width direction of no less than about 0.06 mm and no more than about 0.14 mm, and a dimension in a lamination direction of no less than about 0.06 mm and no more than about 0.14 mm, for example. Each of a first outer electrode and a second outer electrode includes an underlying electrode layer disposed on a surface of a multilayer body, a nickel-plated layer covering the underlying electrode layer, and a tin-plated layer covering the nickel-plated layer. The nickel-plated layer in each of the first outer electrode and second outer electrode has surface roughness of no less than about 3 ?m and no more than about 6 ?m, for example.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: August 28, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yasuharu Yamashita
  • Patent number: 10008331
    Abstract: A multilayer ceramic electronic component includes a ceramic element body including internal electrodes and external electrodes electrically connected to respective internal electrodes. Each of the external electrodes includes a sintered metal layer including glass and metal and a conductive resin layer including resin and metal particles. In a cross section of the multilayer ceramic capacitor, at an interface between the sintered metal layer and the conductive resin layer, recesses having a shape in which a dimension of an inner portion is larger than a dimension of an inlet are present, and L1/L2 is about 0.2 or more and about 1.5 or less, where L1 is a length along the interface at which the glass of the sintered metal layer is exposed at the interface, and L2 is a length along the interface at which the metal of the sintered metal layer is exposed at the interface.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: June 26, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Jun Ikeda, Kota Zenzai
  • Patent number: 10008326
    Abstract: A multilayer ceramic electronic component in which an interface of an edge region of an external electrode that extends around to a side surface of a ceramic body and the ceramic configuring a surface of the ceramic body, an inorganic matter is present containing 26 mol % or more and less than 45 mol % of SiO2 and having a molar ratio (TiO2+ZrO2)/(SiO2+TiO2+ZrO2) of 0.154 or more, or an inorganic matter is present containing 45 mol % or more of SiO2 and having a molar ratio (TiO2+ZrO2)/(SiO2+TiO2+ZrO2) of 0.022 or more. Furthermore, the inorganic matter may contain B2O3 having a molar ratio relative to SiO2 within 0.25?B2O3/SiO2?0.5.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: June 26, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Seiji Koga, Takashi Omori, Jun Ikeda
  • Patent number: 9978764
    Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: May 22, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Fausto Piazza, Sebastien Lagrasta, Raul Andres Bianchi, Simon Jeannot
  • Patent number: 9926200
    Abstract: Highly purified carbon nanotubes (CNT) having virtually no carbonaceous impurities (amorphous carbon) nor inorganic impurities (metal and metal oxides), and methods of their preparation are described. The purified CNT feature excellent electrical, mechanical, and thermal properties due to the near total absence of detrimental impurities. The CNT starting material is preferably in the form of wafer, film, or buckypaper for efficient diffusion of purifying media. The highly pure CNT are prepared by heat treating a CNT starting material in a specified amount of oxygen, then treating the CNT in a solution comprising water and acid, or further heat treating the CNT in an atmosphere comprising chlorine (Cl2). Extremely low levels of inorganic impurities may be achieved by treating sequentially with a treatment solution followed by chlorine. Removal of chloride from purified CNT may be achieved by further treating the chlorine-treated material in an atmosphere comprising hydrogen (H2).
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: March 27, 2018
    Assignee: YAZAKI CORPORATION
    Inventors: Yongan Yan, Satyabrata Raychaudhuri
  • Patent number: 9865690
    Abstract: A method for fabricating a metal structure for a semiconductor device is disclosed. The method begins with providing a wafer with a current input contact and current output contact. Remaining steps include loading the wafer into a deposition apparatus, depositing a layer of metal onto a predefined metal region, removing the wafer from the deposition apparatus, and performing an ex-situ passivation process. If additional layers are to be deposited and passivated, the steps are repeated until a predetermined number of layers of metal are deposited onto the predefined metal region. The predefined metal region is a gate metal opening if the metal structure is a gate contact for a field effect transistor. The ex-situ passivation process is achievable through oxidation or nitridation of the wafer using either oxygen plasma or a nitrogen plasma, respectively. Alternately, oxidation is also achievable through exposing the wafer to air at an elevated temperature.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: January 9, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Liping Daniel Hou, Chuanxin Lian
  • Patent number: 9859065
    Abstract: An electrolytic capacitor is disclosed having a housing in an arced-trapezoidal shape. Disposed within the housing are one or more anodes, one or more cathodes, one or more separators disposed between anodes that are adjacent anodes cathodes, and an electrolyte disposed around the one or more anodes, the one or more cathodes, and the one or more separators within the housing. The housing of the electrolytic capacitor includes front and back walls shaped as arced-trapezoids and four sidewalls that substantially follow the outline of the front and back walls. The electrolytic capacitor is configured to connect in series with one or more electrolytic capacitors of the same shape to form a capacitor assembly. In the capacitor assembly, electrolytic capacitors are placed such that sidewalls are adjacent to each other to form a D-shaped capacitor assembly.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 2, 2018
    Assignee: PACESETTER, INC.
    Inventors: Wisit Lim, Ralph Jason Hemphill, Troy L. McCurry, Peter Fernstrom
  • Patent number: 9852846
    Abstract: A self-healing capacitor comprises a first electrode, a second electrode, and a dielectric layer disposed between said first and second electrodes and having first surface faced the first electrode and second surface faced the second electrode. At least one of the electrodes can include metal foam. The dielectric layer can have electrically conductive channels that each has an exit point located on the first surface of the dielectric layer and another exit point located on the second surface of the dielectric layer. The electrodes can include local contact breakers each of which is located within the electrode at an interface between the dielectric layer and the electrode and opposite at least one exit point of each electrically conductive channel in the dielectric layer. The local contact breakers can prevent electric current through the conductive channels in dielectric layer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: December 26, 2017
    Assignee: CAPACITOR SCIENCES INCORPORATED
    Inventors: Pavel Ivan Lazarev, Ian S. G. Kelly-Morgan
  • Patent number: 9831038
    Abstract: A multilayer ceramic capacitor includes a multilayer unit, thickness-direction first and second outer layer sections, length-direction first and second outer layer sections, and width-direction first and second outer layer sections. A dimension of the thickness-direction second outer layer section is greater than a dimension of the thickness-direction first outer layer section. The thickness-direction second outer layer section includes an inner portion and an outer portion. A composition ratio of Si to Ti in a ceramic dielectric layer included in the outer portion is higher than that in the inner portion. A boundary portion between the outer portion and the inner portion has a larger Si content than the outer portion. The inner portion has a higher composition ratio of Mn to Ti than the outer portion.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: November 28, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shota Kitano, Takanobu Katsuyama, Hiroaki Sugita
  • Patent number: 9818543
    Abstract: An electronic component includes: a chip having first and second end surfaces oriented in a direction of a first axis, first and second main surfaces oriented in a direction of a second axis orthogonal to the first axis, first and second side surfaces oriented in a direction of a third axis orthogonal to the first and second axes, and first and second external electrodes respectively covering the first and second end surfaces and each extending to the first and second main surfaces and side surfaces; a covering portion covering the chip from the first main surface toward the second main surface; and exposed portions provided to the second main surface, including regions where the first and second external electrodes are exposed without being covered with the covering portion, and being pushed out toward the first main surface along ridges connecting the first and second end surfaces and side surfaces.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: November 14, 2017
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Mikio Tahara, Tomoaki Nakamura, Kayoko Hirayama, Reiko Shimoda
  • Patent number: 9819065
    Abstract: A passive radiofrequency microelectronic components for an integrated circuit which includes a dielectric substrate and at least one metal conductive layer positioned on said substrate. The conductive layer including at least one first metal conductive portion and a second metal conductive portion separated by an insulation. A microelectronic component according to the invention includes at least one graphene layer positioned so that a radiofrequency or hyperfrequency signal crosses said at least one graphene layer when it is transmitted between said first metal conductive portion and said second metal conductive portion, said graphene layer being able, when it is subject to an electric potential, to transmit said radiofrequency or hyperfrequency signal along a first direction and to attenuate said radiofrequency or hyperfrequency signal along a second direction opposite to said first direction.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: November 14, 2017
    Assignee: THALES
    Inventors: Afshin Ziaei, Matthieu Le Baillif, Shailendra Bansropun, Paolo Martins
  • Patent number: 9793053
    Abstract: There is provided a multilayered ceramic capacitor, including: a ceramic body; an active layer including a plurality of first and second internal electrodes; an upper cover layer; a lower cover layer formed below the active layer, the lower cover layer being thicker than the upper cover layer; first and second external electrodes; at least one pair of first and second internal electrodes repeatedly formed inside the lower cover layer, wherein, when A is defined as ½ of an overall thickness of the ceramic body, B is defined as a thickness of the lower cover layer, C is defined as ½ of an overall thickness of the active layer, and D is defined as a thickness of the upper cover layer, a ratio of deviation between a center of the active layer and a center of the ceramic body, (B+C)/A, satisfies 1.063?(B+C)/A?1.745.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Ghyu Ahn, Sang Soo Park, Min Cheol Park, Byoung Hwa Lee
  • Patent number: 9761376
    Abstract: In a multilayer ceramic capacitor in which an outer electrode is arranged on a ceramic element body to be electrically connected to an inner electrode, the outer electrode includes a metal electrode layer on the ceramic element body, and a conductive resin layer on the metal electrode layer. When a dielectric layer between a pair of the inner electrodes adjacent in a stacking direction among a plurality of the inner electrodes extending to one of a pair of end surfaces of the ceramic element body is an inter-electrode dielectric layer, a gap extends a direction connecting the adjacent inner electrodes sandwiching the inter-electrode dielectric layer at a position near or adjacent to at least the one of the end surfaces.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: September 12, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Toshiki Nagamoto
  • Patent number: 9653533
    Abstract: An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: May 16, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Uei-Ming Jow, Young Kyu Song, Jong-Hoon Lee, Xiaonan Zhang
  • Patent number: 9642260
    Abstract: There is provided an embedded multilayer ceramic electronic component including: a ceramic body including a dielectric layer; a plurality of first and second internal electrodes; and first and second external electrodes formed on both end portions of the ceramic body, wherein the first and second external electrodes are extended to first and second main surfaces of the ceramic body, and when a thickness of the ceramic body is defined as ts, a maximum thickness of the first and second external electrodes formed on the first and second main surfaces of the ceramic body is defined as tb, a minimum distance of the first and second external electrodes formed on first and second end surfaces of the ceramic body in a length direction of the ceramic body is defined as ta, tb/ts and ta/tb satisfy the following Equations, respectively: 0.1?tb/ts?1.0 and 0.5?ta/tb?2.0.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 2, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Woo Lee, Hai Joon Lee, Byoung Hwa Lee, Jin Man Jung
  • Patent number: 9604883
    Abstract: A dielectric composition includes a main ingredient and accessory ingredients. The main ingredient is represented by Bam(Ti(1-y)My)O3 (0.990<m<1.015, 0.001?y?0.010), where M is a transition metal including at least one of a pentavalent transition metal and a trivalent transition metal.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: March 28, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Du Won Choi, Sung Hyung Kang, Chang Hoon Kim
  • Patent number: 9455313
    Abstract: A capacitor can be fabricated within an integrated circuit (IC) by creating, in a top surface of a dielectric layer of the IC, a recess having at least one side and a bottom, the bottom adjacent to a first conductive structure. A first plate of the capacitor may be formed by depositing a conductive liner onto the at least one side and the bottom of the recess. A conformal dielectric film may be deposited onto the first plate within the recess, and a second plate of the capacitor may be formed by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the first plate.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: September 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Todd A. Christensen, John E. Sheets, II