For Decoupling Type Capacitor Patents (Class 361/306.2)
  • Patent number: 10170247
    Abstract: In a multilayer capacitor, both a minimum distance in a thickness direction between a first effective portion of a first inner electrode and a second main surface and a minimum distance in the thickness direction between a second effective portion of a second inner electrode and the second main surface are shorter than any of a dimension in the thickness direction of a first extending portion of the first inner electrode, a dimension in the thickness direction of a second extending portion of the first inner electrode and a dimension in the thickness direction of the third extending portion of the second inner electrode.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: January 1, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yohei Mukobata, Takashi Sawada, Kazuhiro Nishibayashi
  • Patent number: 9989584
    Abstract: Example automatic test equipment (ATE) may include: a device interface board (DIB) on which the DUT is mounted; a system for sending signals to, and receiving signals from, the DUT; and an energy source unit (ESU) to provide current to the DUT via the DIB, where the ESU includes current paths to provide the current, and where the current paths are configured to limit a combined inductance of the current paths.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: June 5, 2018
    Assignee: Teradyne, Inc.
    Inventors: Jack E. Weimer, Steven C. Price, David R. Hanna, Jeffry Baenen, Scott Skibinski
  • Patent number: 9978671
    Abstract: A power semiconductor device is provided. The power semiconductor device includes a leadframe, which includes a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive, at least one first power semiconductor component applied on the first chip carrier part, at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, and a capacitor. The capacitor is mounted on two adjacent external leads.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: May 22, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Ralf Otremba, Fabio Brucchi, Teck Sim Lee, Xaver Schloegel, Franz Stueckler
  • Patent number: 9653219
    Abstract: A mesoporous, nanocrystalline, metal oxide construct particularly suited for capacitive energy storage that has an architecture with short diffusion path lengths and large surface areas and a method for production are provided. Energy density is substantially increased without compromising the capacitive charge storage kinetics and electrode demonstrates long term cycling stability. Charge storage devices with electrodes using the construct can use three different charge storage mechanisms immersed in an electrolyte: (1) cations can be stored in a thin double layer at the electrode/electrolyte interface (non-faradaic mechanism); (2) cations can interact with the bulk of an electroactive material which then undergoes a redox reaction or phase change, as in conventional batteries (faradaic mechanism); or (3) cations can electrochemically adsorb onto the surface of a material through charge transfer processes (faradaic mechanism).
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: May 16, 2017
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Bruce S. Dunn, Sarah H. Tolbert, John Wang, Torsten Brezesinski, George Gruner
  • Patent number: 9472344
    Abstract: An electronic component includes a multilayer capacitor and an interposer. The multilayer capacitor includes an element body and a pair of external electrodes. The interposer includes a substrate having first and second principal faces, a pair of first electrodes disposed on the first principal face, and a pair of second electrodes disposed on the second principal face so as to be separated from the pair of first electrodes in a first direction or in a second direction. Widths of the pair of external electrodes and the pair of first electrodes are smaller than a width of the element body. The element body has a first portion covered by the external electrode, and a pair of second portions located on both sides of the first portion. The pair of second portions are separated from the interposer and overlap the pair of second electrodes when viewed from a third direction.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: October 18, 2016
    Assignee: TDK CORPORATION
    Inventors: Tomoyoshi Fujimura, Atsushi Sato, Masahiro Mori
  • Patent number: 9305704
    Abstract: There is provided a multilayer ceramic capacitor including, a ceramic body having a plurality dielectric layers stacked therein and a groove portion recessed inwardly in a lower surface thereof in a width direction, a plurality of first and second internal electrodes disposed in the ceramic body to be alternately exposed through both end surfaces of the ceramic body, having the dielectric layers therebetween, and first and second external electrodes respectively formed on both end portions of the ceramic body and electrically connected to the first and second internal electrodes, respectively.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: April 5, 2016
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Min Cheol Park
  • Patent number: 9209190
    Abstract: The present disclosure relates to a method of forming a capacitor structure, including depositing a plurality of first polysilicon (POLY) layers of uniform thickness separated by a plurality of oxide/nitride/oxide (ONO) layers over a bottom and sidewalls of a recess and substrate surface. A second POLY layer is deposited over the plurality of first POLY layers, is separated by an ONO layer, and fills a remainder of the recess. Portions of the second POLY layer and the second ONO layer are removed with a first chemical-mechanical polish (CMP). A portion of each of the plurality of first POLY layers and the first ONO layers on the surface which are not within a doped region of the capacitor structure are removed with a first pattern and etch process such that a top surface of each of the plurality of first POLY layers is exposed for contact formation.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Szu-Yu Wang, Chung-Yi Yu
  • Patent number: 9177948
    Abstract: A switching element unit comprising a switching element and a smoothing capacitor that suppresses variation in DC voltage to be supplied to the switching element. An element mounting surface may be formed in an outer surface of the smoothing capacitor and may be formed integrally with a dielectric portion interposed between electrodes of the smoothing capacitor. A capacitor connection electrode as an electrode may be electrically connected to a terminal of the smoothing capacitor formed on the element mounting surface, and the switching element is placed on the element mounting surface such that a terminal of the switching element is electrically connected to the capacitor connection electrode.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: November 3, 2015
    Assignee: AISIN AW CO., LTD.
    Inventor: Hirohisa Totani
  • Patent number: 9107323
    Abstract: A bandpass filter module includes a mounting board and a BPF chip mounted on a surface thereof. The BPF chip includes three or more resonators; a first-stage resonator located closest to an input terminal, a final-stage resonator located closest to an output terminal, and a middle-stage resonator connected between the first-stage and the final-stage resonators and located in a chip middle zone. The mounting board includes an area overlapping with the chip middle zone, viewed in plan, defining a ground-free space in which no ground electrode is disposed. The ground-free space is formed at least from the surface of the mounting board to a depth position at which a topmost internal wiring layer is located. The middle-stage resonator is prevented from being coupled to ground electrodes on the mounting board and from a lower Q-value and increased insertion loss.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: August 11, 2015
    Assignee: TDK Corporation
    Inventors: Shigemitsu Tomaki, Yoshikazu Tsuya, Masamichi Tanaka, Isao Abe
  • Patent number: 8988852
    Abstract: In one embodiment, an apparatus includes a first reference voltage coupled to a first metal layer and a second reference voltage coupled to a second metal layer. A first finger type in the plurality of fingers is coupled to the first metal layer at a first area and coupled to the first metal layer and the second metal layer at a second area. A second finger type in the plurality of fingers is coupled to the second metal layer at the first area and coupled to the first metal layer and the second metal layer at the second area. Also, the first finger type and the second finger type alternately positioned next to each other.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: March 24, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: David M. Signoff, Wayne A. Loeb
  • Patent number: 8941972
    Abstract: There are provided a multilayer ceramic electronic component and a method of manufacturing the same. The multilayer ceramic electronic component includes: a ceramic body including a dielectric layer; first and second internal electrodes disposed within the ceramic body to face each other, while having the dielectric layer interposed therebetween; and first external electrodes electrically connected to first and second internal electrodes and second external electrodes formed on the first external electrodes, wherein the first and second external electrodes include a conductive metal and a glass, and when the second external electrodes are divided into three equal parts in a thickness direction, an area of the glass in central parts thereof with respect to an area of the central parts is 30 to 80%. Therefore, sealing properties of a chip is improved, whereby a multilayer ceramic electronic component having improved reliability may be implemented.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: January 27, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung Jun Park, Sang Hoon Kwon, Chang Hoon Kim, Hyun Hee Gu, Jae Young Park, Da Young Choi, Kyu Ha Lee, Byung Jun Jeon
  • Patent number: 8860114
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor structure disposed on the substrate. The capacitor structure includes a first conductive component; a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component. The first, second and third conductive components are separated from each other by respective dielectric material.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Min-Chie Jeng
  • Patent number: 8842411
    Abstract: A multi-layer capacitor includes a first capacitor layer and a second capacitor layer adjacent and substantially parallel to the first capacitor layer. The second capacitor layer has a surface area that is less than the surface area of the first capacitor layer.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: September 23, 2014
    Assignee: Pacesetter, Inc.
    Inventors: Jin Zhang, Wisit Lim, Conor Flannery
  • Patent number: 8842412
    Abstract: A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8829356
    Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: September 9, 2014
    Assignee: Unimicron Technology Corporation
    Inventors: Shih-Ping Hsu, Zhao-Chong Zeng
  • Patent number: 8787003
    Abstract: According to one embodiment of a capacitor module, the capacitor module includes a substrate having a metallization on a first side of the substrate, a plurality of connectors electrically coupled to the metallization and a plurality of capacitors disposed on the metallization. The plurality of capacitors includes a first set of capacitors electrically connected in parallel between a first set of the connectors and a second set of the connectors. The capacitor module further includes a housing enclosing the plurality of capacitors within the capacitor module.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: July 22, 2014
    Assignee: Infineon Technologies AG
    Inventors: Daniel Domes, Reinhold Bayerer
  • Patent number: 8779849
    Abstract: Apparatuses, multi-chip modules, capacitive chips, and methods of providing capacitance to a power supply voltage in a multi-chip module are disclosed. In an example multi-chip module, a signal distribution component may be configured to provide a power supply voltage. A capacitive chip may be coupled to the signal distribution component and include a plurality of capacitive units. The capacitive chip may be configured to provide a capacitance to the power supply voltage. The plurality of capacitive units may be formed from memory cell capacitors.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: July 15, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Patent number: 8767404
    Abstract: Integrated circuits with decoupling capacitor circuitry are provided. The decoupling capacitor circuitry may include density-compliance structures. The density-compliance structures may be strapped to metal paths driven by power supply lines. Strapping density-compliance dummy structures in this way may increase the capacitance per unit area of the decoupling capacitor circuitry. Strapping density-compliance dummy structures in this way may shield the decoupling capacitor from nearby noisy signal sources.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: July 1, 2014
    Assignee: Altera Corporation
    Inventor: Chin Hieang Khor
  • Patent number: 8760843
    Abstract: A capacitive device includes a first capacitor including a first wiring layer, a first dielectric film, a first conductive layer, a first insulating layer on the first capacitor, a second capacitor on the first insulating layer including a second conductive layer, a second dielectric film, and a third conductive layer, a second insulating layer on the second capacitor, a second wiring layer on the second insulating layer including first and second connection wires, a first via connecting the first wiring layer to the second conductive layer, a second via connecting the third conductive layer to the second wiring layer, a third via connecting the first connection wire to the first conductive layer, and a fourth via connecting the second connection wire to the first wiring layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: June 24, 2014
    Assignee: Dongbu Hitek Co., Ltd.
    Inventors: Jong Taek Hwang, Han Choon Lee, Oh Jin Jung, Jin Youn Cho
  • Patent number: 8749022
    Abstract: A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second voltage applied thereto; and a gate electrode disposed on an upper portion of the first well or an upper portion of the second well in such a way that the gate electrode is insulated from the first well or the second well, wherein capacitances of the capacitor device include a first capacitance between the first well and the second well and a second capacitance between the first well or the second well and the gate electrode.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Ryul Chang, Hwa-Sook Shin
  • Patent number: 8749949
    Abstract: In a structure or device having a pair of electrical conductors separated by an insulator across which a voltage is placed, resistive layers are formed around the conductors to force the electric potential within the insulator to distribute more uniformly so as to decrease or eliminate electric field enhancement at the conductor edges. This is done by utilizing the properties of resistive layers to allow the voltage on the electrode to diffuse outwards, reducing the field stress at the conductor edge. Preferably, the resistive layer has a tapered resistivity, with a lower resistivity adjacent to the conductor and a higher resistivity away from the conductor. Generally, a resistive path across the insulator is provided, preferably by providing a resistive region in the bulk of the insulator, with the resistive layer extending over the resistive region.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: June 10, 2014
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: George J. Caporaso, Stephen E. Sampayan, David M. Sanders
  • Patent number: 8743555
    Abstract: Substrates having power planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a first power plane and a second power plane. The at least one noise suppression structure may include a first power plane extension that extends from the first power plane generally toward the second power plane, and a second power plane extension that extends from the second power plane generally toward the first power plane. Methods for suppressing noise in at least one of the first power plane and second power plane include providing such noise suppression structures between the power planes.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: June 3, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Houfei Chen, Shiyou Zhao
  • Patent number: 8743529
    Abstract: A capacitor having a stem that is designed to be inserted into a single, large-diameter via hole drilled in a printed circuit board is provided, wherein the stem may have conductive rings for making the positive and negative connections to the printed circuit board power distribution planes. Inside the capacitive stem, current, or at least a portion thereof, may be carried to the main body of the capacitor through low-inductance plates that are interleaved to maximize their own mutual inductance and, therefore, minimize the connection inductance. Alternatively, the capacitor may include a coaxial stem that forms a coaxial transmission line with the anode and cathode terminals forming the inner and outer conductors.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: June 3, 2014
    Assignee: Clemson University Research Foundation
    Inventors: Todd Hubing, Hocheol Kwak, Haixin Ke
  • Patent number: 8737037
    Abstract: There are provided a ceramic electronic component and a method of manufacturing the same. The ceramic electronic component includes: a ceramic element; and an internal electrode layer formed within the ceramic element, having a thickness of 0.5 ?m or less, and including a non-electrode region formed therein, wherein an area ratio of the non-electrode region to an electrode region of the internal electrode layer, in a cross section of the internal electrode layer is between 0.1% and 10%, and the non-electrode region includes a ceramic component.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong Han Kim, Hyun Chul Jeong
  • Patent number: 8724290
    Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: May 13, 2014
    Assignee: Intel Corporation
    Inventors: Nachiket R. Raravikar, Rahul Panat
  • Patent number: 8593782
    Abstract: A clad capacitor and method of manufacture includes assembling a preform comprising a ductile, electrically conductive fiber; a ductile, electrically insulating cladding positioned on the fiber; and a ductile, electrically conductive sleeve positioned over the cladding. One or more preforms are then bundled, heated and drawn along a longitudinal axis to decrease the diameter of the ductile components of the preform and fuse the preform into a unitized strand.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: November 26, 2013
    Assignee: UT-Battelle, LLC
    Inventor: Enis Tuncer
  • Patent number: 8593816
    Abstract: A connector assembly for an implantable medical device includes a plurality of feedthroughs mounted in a conductive array plate, each feedthrough in the plurality of feedthroughs including a feedthrough pin electrically isolated from the conductive array plate by an insulator and an electronic module assembly including a plurality of conductive strips set in a non-conductive block. The plurality of conductive strips is in physical and electrical contact with the feedthrough pins at an angle of less than 135 degrees. The connector assembly further includes at least one circuit, the circuit including a plurality of conductors corresponding to the plurality of feedthroughs. The plurality of conductors of the circuit is in physical and electrical contact with a corresponding one of the conductive strips of the plurality of conductive strips of the electronic module assembly at an angle of less than 135 degrees.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: November 26, 2013
    Assignee: Medtronic, Inc.
    Inventors: Rajesh V. Iyer, Michael G. Marinkov, Lea A. Nygren, Jeffrey J. Clayton, James Strom, Thomas E. Meyer, Steven T. Deininger, Wayne R. Kuechenmeister
  • Patent number: 8570707
    Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 29, 2013
    Assignee: Broadcom Corporation
    Inventors: Victor Chiu-Kit Fong, Eric Bruce Blecker, Tom W. Kwan, Ning Li, Sumant Rangnathan, Chao Tang, Pieter Vorenkamp
  • Patent number: 8564966
    Abstract: Embodiments of the present invention provide an arrangement structure capable of reducing noise caused by a laminated ceramic capacitor mounted on a printed circuit board. A unit arrangement structure includes ceramic capacitors. Among the laminated ceramic capacitors, capacitors are arranged so that capacitor axes thereof extend along a first axis, while the other ceramic capacitors are arranged so that capacitor axes thereof extend along a second axis crossing the first axis. In accordance with such an arrangement structure, it is possible to effectively suppress noise even in the case of single-side mounting.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: October 22, 2013
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Wataru Kitagawa, Shigeru Yuzawa
  • Patent number: 8547681
    Abstract: An electronic device package includes first and second electrodes of a package substrate. The first electrode has fingers formed from a first metal level and is configured to operate at a first DC potential. The second electrode has fingers formed from the first metal level interdigitated with the fingers of the first electrode. A via conductively connects the second electrode to a second metal level. The second metal level is configured to operate at a second DC potential. The first and second DC potentials are thereby capacitively coupled through the interdigitated electrodes.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: October 1, 2013
    Assignee: LSI Corporation
    Inventors: Shawn M. Logan, Ellis E. Nease
  • Patent number: 8508950
    Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The at least one noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: August 13, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Houfei Chen, Shiyou Zhao
  • Patent number: 8481861
    Abstract: A die having a base formed of a first material is connected to a board having a base formed of a second material. An interposer having a coefficient of thermal expansion intermediate coefficients of thermal expansion of the first and second materials is positioned between the die and the board.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: July 9, 2013
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Robert C. Cooney, Joseph M. Wilkinson
  • Patent number: 8461462
    Abstract: A circuit substrate includes a resin layer; and an inorganic insulating layer including a groove portion penetrating the inorganic insulating layer in a thickness direction thereof. A part of the resin layer is in the groove portion.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: June 11, 2013
    Assignee: Kyocera Corporation
    Inventor: Katsura Hayashi
  • Publication number: 20130120903
    Abstract: A decoupling device including a lead frame, multiple capacitor units, a protective layer and a packaging element is provided. The lead frame includes a cathode terminal portion and at least two opposite anode terminal portions disposed at two ends of the cathode terminal portion. The two anode terminal portions are electrically connected with each other through a conductive line. The capacitor units are connected in parallel and disposed on the lead frame. Each capacitor unit has a cathode portion and an opposite anode portion. The cathode portion is electrically connected with the cathode terminal portion. The anode portion is electrically connected with the anode terminal portion. The protective layer wraps at least one of the anode portion and the cathode portion of the capacitor unit. The packaging element covers the lead frame, the capacitor units and the protective layer. The packaging element exposes a bottom surface of the lead frame.
    Type: Application
    Filed: January 15, 2012
    Publication date: May 16, 2013
    Applicant: Industrial Technology Research Institute
    Inventors: Yi-Hsiu Pan, Yu-Ting Cheng, Li-Duan Tsai, Chi-Lun Chen, Cheng-Liang Cheng
  • Patent number: 8395902
    Abstract: An electronic apparatus includes an electronic component electrically connected to a substrate positioned beneath the electronic component. A member includes a plurality of decoupling capacitors having different voltages, and the decoupling capacitors are electrically connected to the electronic component. A plurality of voltage planes in the member are electrically connected to the decoupling capacitors. The decoupling capacitors, via the voltage planes in the member, provide different voltages to the voltage planes and thus the electronic component.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: March 12, 2013
    Assignee: International Business Machines Corporation
    Inventor: John U. Knickerbocker
  • Patent number: 8395880
    Abstract: A thin-film device system includes a substrate and a plurality of pillars. The plurality of pillars project from a surface of the substrate. Each of the plurality of pillars have a perimeter that includes at least four protrusions that define at least four recessed regions between the at least four protrusions. Each of the at least four recessed regions of each of the plurality of pillars receives one protrusion from an adjacent one of the plurality of pillars. A thin-film device is fabricated over the plurality of pillars.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: March 12, 2013
    Assignee: Medtronic, Inc.
    Inventor: James R. Wasson
  • Patent number: 8395881
    Abstract: A multilayer feedthrough capacitor has a capacitor element body of a substantially rectangular parallelepiped shape, a signal internal electrode, a ground internal electrode, first and second signal terminal electrodes, and a first ground terminal electrode. The capacitor element body includes first and second end faces opposed in a longitudinal direction thereof, and a mounting surface perpendicular to a direction in which a plurality of insulator layers are laminated. The first signal terminal electrode and the first ground terminal electrode are arranged in proximity to each other in a first region near the first end face in the mounting surface. The second signal terminal electrode is arranged in a second region near the second end face in the mounting surface. No conductor is arranged in a third region between the first region and the second region in the longitudinal direction of the capacitor element body, in the mounting surface.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 12, 2013
    Assignee: TDK Corporation
    Inventor: Masaaki Togashi
  • Patent number: 8389870
    Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: March 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kevin Bills, Mahesh Bohra, Jinwoo Choi, Tae Hong Kim, Rohan Mandrekar
  • Patent number: 8385047
    Abstract: A multi-layer film-stack and method for forming the multilayer film-stack is given where a series of alternating layers of conducting and dielectric materials are deposited such that the conducting layers can be selectively addressed. The use of the method to form integratable high capacitance density capacitors and complete the formation of an integrated power system-on-a-chip device including transistors, conductors, inductors, and capacitors is also given.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: February 26, 2013
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Huikai Xie, Khai D. T. Ngo
  • Patent number: 8339767
    Abstract: A power capacitor is described herein. The power capacitor includes a housing and at least one capacitor winding. The power capacitor also includes at least one mechanical spring element between the housing and the at least one capacitor winding.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: December 25, 2012
    Assignee: EPCOS AG
    Inventors: Wilhelm Grimm, Wilhelm Hübscher, Harald Vetter
  • Patent number: 8339765
    Abstract: A capacitor includes a substrate, a plurality of first storage electrodes, a plurality of second storage electrodes, a first supporting layer pattern, a dielectric layer and a plate electrode. A plurality of contact pads is formed I the substrate. The first storage electrodes are arranged along lines parallel with a first direction and electrically connected to the contact pads, respectively. The second storage electrodes are respectively stacked on the first storage electrodes. The first supporting layer pattern extends in a direction parallel with the first direction between adjacent second storage electrodes and makes contact with the adjacent second storage electrodes to support the second storage electrodes. The dielectric layer is formed on the first and second storage electrodes. The plate electrode is formed on the dielectric layer.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: December 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoon-Sang Choi, Ki-Vin Im, Se-Hoon Oh, Sang-Yeol Kang, Cha-Young Yoo
  • Patent number: 8315032
    Abstract: A ductile preform for making a drawn capacitor includes a plurality of electrically insulating, ductile insulator plates and a plurality of electrically conductive, ductile capacitor plates. Each insulator plate is stacked vertically on a respective capacitor plate and each capacitor plate is stacked on a corresponding insulator plate in alignment with only one edge so that other edges are not in alignment and so that each insulator plate extends beyond the other edges. One or more electrically insulating, ductile spacers are disposed in horizontal alignment with each capacitor plate along the other edges and the pattern is repeated so that alternating capacitor plates are stacked on alternating opposite edges of the insulator plates. A final insulator plate is positioned at an extremity of the preform. The preform may then be drawn to fuse the components and decrease the dimensions of the preform that are perpendicular to the direction of the draw.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: November 20, 2012
    Assignee: UT-Battelle, LLC
    Inventor: Enis Tuncer
  • Patent number: 8304854
    Abstract: Disclosed are a semiconductor integrated circuit chip, a multilayer chip capacitor, and a semiconductor integrated circuit chip package. The semiconductor integrated circuit chip includes a semiconductor integrated circuit chip body, an input/output terminal disposed on the outside of the semiconductor integrated circuit chip body, and a decoupling capacitor disposed at a side face of the semiconductor integrated circuit chip body and electrically connected to the input/output terminal. The semiconductor integrated circuit chip cab be obtained, which can maintain an impedance of a power distribution network below a target impedance in a wide frequency range, particularly at a high frequency, by minimizing an inductance between a decoupling capacitor and a semiconductor integrated circuit chip.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: November 6, 2012
    Assignees: Samsung Electro-Mechanics Co., Ltd., Clemson University
    Inventors: Byoung Hwa Lee, Min Cheol Park, Ho Cheol Kwak, Haixin Ke, Todd Harvey Hubing
  • Patent number: 8295029
    Abstract: A multi-segment capacitor fabricated on a semiconductor substrate includes MxN capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: October 23, 2012
    Assignee: Altera Corporation
    Inventors: Shuxian Chen, Jeffrey T. Watt
  • Patent number: 8295028
    Abstract: Capacitive coupling devices and methods of fabricating a capacitive coupling device are disclosed. The coupling device could include a stack of layers forming electrodes and at least one insulator. The insulator could include a region of doped silicon. The silicon could be doped with a species selected from Ce, Cr, Co, Cu, Dy, Er, Eu, Ho, Ir, Li, Lu, Mn, Pr, Rb, Sm, Sr, Tb, Tm, Yb, Y, Ac, Am, Ba, Be, Cd, Gd, Fe, La, Pb, Ni, Ra, Sc, Th, Hf, Tl, Sn, Np, Rh, U, Zn, Ag, and Yb in relief and forming roughnesses relative to the neighboring regions of the same level in the stack. The electrodes and the insulator form conformal layers above the doped silicon region.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: October 23, 2012
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Benoit Froment
  • Patent number: 8263877
    Abstract: A printed circuit board includes a first signal layer, a second signal layer, and a dielectric layer sandwiched between the first signal layer and the second signal layer. The first signal layer includes two pads. The second signal layer includes two conducting pieces connected to two signal traces. The shape and material of the pads are the same as the shape and material of the conducting pieces. The projections of the pads on the second signal layer are overlapping with the conducting pieces.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: September 11, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Chien-Hung Liu, Po-Chuan Hsieh, Yu-Chang Pai, Shou-Kuo Hsu
  • Patent number: 8259434
    Abstract: There is provided a multilayer ceramic capacitor including: a capacitor main body formed by stacking a dielectric layer having a thickness of td and alternately stacking more than one opposing pair of a first internal electrode having a thickness of te and a second internal electrode having the same thickness as the first internal electrode, and having the dielectric layer therebetween; and a protective layer formed by stacking a second dielectric layer on at least one of an upper surface and a lower surface of the capacitor main body so that a dielectric material layer has a thickness of tc, wherein when a thickness from an end of a region where the first internal electrode and the second internal electrode oppose each other to side and end surfaces of the capacitor main body is a, it satisfies the following Equation 1 and a method of fabricating a multilayer ceramic capacitor are provided.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: September 4, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyo Jung Kim, Ji Hun Jeong, Dong Ik Chang, Doo Young Kim
  • Patent number: 8227894
    Abstract: A stepwise capacitor structure includes at least one stepwise conductive layer. The stepwise capacitor represents a feature of multiple capacitors. When currents flow through the stepwise capacitor, different current paths are presented in between an upper conductor and a bottom conductor of the stepwise capacitor in response to different current frequency; different inductor is induced in each path and decoupled by a stepwise capacitor structure as disclosed herein.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: July 24, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Min-Lin Lee, Shih-Hsien Wu, Shinn-Juh Lai, Shur-Fen Liu
  • Patent number: 8218286
    Abstract: An integrated circuit structure includes a capacitor, which further includes a first capacitor plate formed of polysilicon, and a second capacitor plate substantially encircling the first capacitor plate. The first capacitor plate has a portion configured to vibrate in response to an acoustic wave. The second capacitor plate is fixed and has slanted edges facing the first capacitor plate.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: July 10, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hau Wu, Chun-Ren Cheng, Jiou-Kang Lee, Shang-Ying Tsai, Jung-Huei Peng
  • Patent number: 8143697
    Abstract: Some embodiments of the invention include thin film capacitors formed in a package substrate of an integrated circuit package. At least one of the thin film capacitors includes a first electrode layer, a second electrode layer, and a dielectric layer between the first and second electrode layers. Each of the first and second electrode layers and the dielectric layer is formed individually and directly on the package substrate. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Huankiat Seh, Yongki Min