Abstract: A method of fabrication and device made by preparing a photosensitive glass substrate comprising at least silica, lithium oxide, aluminum oxide, and cerium oxide, masking a design layout comprising one or more holes to form one or more electrical conduction paths on the photosensitive glass substrate, exposing at least one portion of the photosensitive glass substrate to an activating energy source, exposing the photosensitive glass substrate to a heating phase of at least ten minutes above its glass transition temperature, cooling the photosensitive glass substrate to transform at least part of the exposed glass to a crystalline material to form a glass-crystalline substrate and etching the glass-crystalline substrate with an etchant solution to form one or more angled channels that are then coated.

Abstract: Provided is an in-vehicle power conversion device in which a smoothing capacitor includes a first electrical connection portion, a second electrical connection portion, a mechanical connection portion, and a smoothing capacitor main body. The first electrical connection portion is electrically connected to a first conductor. The second electrical connection portion is electrically connected to a second conductor. The mechanical connection portion functions as an additional electrical connection portion configured to fix the smoothing capacitor main body to the first conductor or the second conductor to be electrically connected to a fixing destination of the smoothing capacitor main body.

Abstract: A capacitor includes a capacitor element, a case housing the capacitor element, a filling resin filled in the case, and a board holder including a fixing part to which a circuit board mounted with an electronic circuit is to be fixed. The board holder is configured to hold the circuit board to be exposed from the filling resin.

Abstract: A component array can include a first multilayer ceramic component having a first terminal at a first end and a second terminal at a second end opposite the first end in a first direction. A second component can have a first terminal at a first end and a second terminal at a second end opposite the first end in the first direction. A heat sink layer can be arranged between the first component and the second component in a second direction that is perpendicular to the first direction. The heat sink layer can include a first metallization layer electrically connecting the first terminal of the first multilayer ceramic component with the first terminal of the second multilayer ceramic component and a second metallization layer electrically connecting the second terminal of the first multilayer ceramic component with the second terminal of the second multilayer ceramic component.

Abstract: The present invention is directed to a multilayer ceramic capacitor that includes a plurality of active electrodes and at least one shield electrode that are each arranged within a monolithic body and parallel with a longitudinal direction. The capacitor may exhibit a first insertion loss value at a test frequency, which may be greater than about 2 GHz, in a first orientation relative to the mounting surface. The capacitor may exhibit a second insertion loss value at about the test frequency in a second orientation relative to the mounting surface and the capacitor is rotated 90 degrees or more about the longitudinal direction with respect to the first orientation. The longitudinal direction of the capacitor may be parallel with the mounting surface in each of the first and second orientations. The second insertion loss value may differ from the first insertion loss value by at least about 0.3 dB.

Abstract: A capacitor includes a capacitor element, an electrode disposed on an end face of the capacitor element, a bus bar connected to the electrode, and a case housing the capacitor element. The bus bar is extended from an opening of the case to outside the case. Outside the case, the bus bar includes an extension part and a connection terminal. The extension part extends in a first direction along a side face of the case. The connection terminal is connected to the extension part. Further, the case includes a supporting part disposed on the side face of the case. The supporting part supports the bus bar to form a space between the side face and the extension part.

Abstract: A multilayer ceramic capacitor includes a stacked body and external electrodes. The stacked body includes stacked dielectric layers and internal electrodes. The external electrodes are disposed on lateral surfaces of the stacked body and are connected to the internal electrodes. The dielectric layers include outer layer portions and an effective layer portion. Each outer layer portion is adjacent to a corresponding main surface of the stacked body. Each outer layer portion is a dielectric layer located between a corresponding main surface and an internal electrode closest to the main surface. A ratio of a dimension of the effective layer portion in a stacking direction to a dimension of the stacked body in the stacking direction is not less than about 53% and not more than about 83%.

Abstract: There is provided a card or token for use in financial transactions. The financial transaction token or card has an onboard energy storage device that enables onboard electronics to operate when the card is not in the proximity of a merchant Point-Of-Service (POS) terminal. In one implementation, the onboard energy storage device includes a capacitor such as a thin-film capacitor that stores sufficient energy to power onboard electronics without the need for an onboard battery. The card may be incorporated within various conventional apparatus such as a see-through and/or protective substrate, an item of clothing, an item of jewelry, a cell phone, a Personal Digital Assistant (PDA), a credit card, an identification card, a money holder, a wallet, a personal organizer, a keychain payment tag, and like personality.

Abstract: Resistor voltage dividers are commonly used to create reference voltages, or to reduce the magnitude of a voltage so it can be measured. Many measurements in test and measurement or calibration applications regularly require accuracies within the sub-part per million (ppm) range, e.g. 0.1 ppm to 1.0 ppm. However, the continued drive for improved accuracy in calibration, standards, and measurements on circuits and components means many measurements and measurement systems are operating at 50 parts per billion (ppb) and below to approximately 10 ppb. At these levels even relatively simple passive elements such as voltage dividers cannot be used without calibration and that these calibrations may be required at frequencies substantially higher than the other elements within the test and measurement equipment. Accordingly, the inventors have established a self-contained voltage divider with internal calibration allowing the voltage divider to be calibrated for every measurement if necessary.

Abstract: A semiconductor device including a connection terminal that is electrically connected to a semiconductor chip, a bus bar with an opening through which the connection terminal passes, and a fusing portion including a jointing portion, which is provided over an upper surface of the bus bar from an upper part of the connection terminal that is positioned above the upper surface of the bus bar by making the connection terminal pass through the opening of the bus bar, is provided.

Abstract: In a multilayer capacitor, both a minimum distance in a thickness direction between a first effective portion of a first inner electrode and a second main surface and a minimum distance in the thickness direction between a second effective portion of a second inner electrode and the second main surface are shorter than any of a dimension in the thickness direction of a first extending portion of the first inner electrode, a dimension in the thickness direction of a second extending portion of the first inner electrode and a dimension in the thickness direction of the third extending portion of the second inner electrode.

Abstract: Example automatic test equipment (ATE) may include: a device interface board (DIB) on which the DUT is mounted; a system for sending signals to, and receiving signals from, the DUT; and an energy source unit (ESU) to provide current to the DUT via the DIB, where the ESU includes current paths to provide the current, and where the current paths are configured to limit a combined inductance of the current paths.

Abstract: A power semiconductor device is provided. The power semiconductor device includes a leadframe, which includes a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive, at least one first power semiconductor component applied on the first chip carrier part, at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, and a capacitor. The capacitor is mounted on two adjacent external leads.

Abstract: A mesoporous, nanocrystalline, metal oxide construct particularly suited for capacitive energy storage that has an architecture with short diffusion path lengths and large surface areas and a method for production are provided. Energy density is substantially increased without compromising the capacitive charge storage kinetics and electrode demonstrates long term cycling stability. Charge storage devices with electrodes using the construct can use three different charge storage mechanisms immersed in an electrolyte: (1) cations can be stored in a thin double layer at the electrode/electrolyte interface (non-faradaic mechanism); (2) cations can interact with the bulk of an electroactive material which then undergoes a redox reaction or phase change, as in conventional batteries (faradaic mechanism); or (3) cations can electrochemically adsorb onto the surface of a material through charge transfer processes (faradaic mechanism).

Abstract: An electronic component includes a multilayer capacitor and an interposer. The multilayer capacitor includes an element body and a pair of external electrodes. The interposer includes a substrate having first and second principal faces, a pair of first electrodes disposed on the first principal face, and a pair of second electrodes disposed on the second principal face so as to be separated from the pair of first electrodes in a first direction or in a second direction. Widths of the pair of external electrodes and the pair of first electrodes are smaller than a width of the element body. The element body has a first portion covered by the external electrode, and a pair of second portions located on both sides of the first portion. The pair of second portions are separated from the interposer and overlap the pair of second electrodes when viewed from a third direction.

Abstract: There is provided a multilayer ceramic capacitor including, a ceramic body having a plurality dielectric layers stacked therein and a groove portion recessed inwardly in a lower surface thereof in a width direction, a plurality of first and second internal electrodes disposed in the ceramic body to be alternately exposed through both end surfaces of the ceramic body, having the dielectric layers therebetween, and first and second external electrodes respectively formed on both end portions of the ceramic body and electrically connected to the first and second internal electrodes, respectively.

Abstract: The present disclosure relates to a method of forming a capacitor structure, including depositing a plurality of first polysilicon (POLY) layers of uniform thickness separated by a plurality of oxide/nitride/oxide (ONO) layers over a bottom and sidewalls of a recess and substrate surface. A second POLY layer is deposited over the plurality of first POLY layers, is separated by an ONO layer, and fills a remainder of the recess. Portions of the second POLY layer and the second ONO layer are removed with a first chemical-mechanical polish (CMP). A portion of each of the plurality of first POLY layers and the first ONO layers on the surface which are not within a doped region of the capacitor structure are removed with a first pattern and etch process such that a top surface of each of the plurality of first POLY layers is exposed for contact formation.

Abstract: A switching element unit comprising a switching element and a smoothing capacitor that suppresses variation in DC voltage to be supplied to the switching element. An element mounting surface may be formed in an outer surface of the smoothing capacitor and may be formed integrally with a dielectric portion interposed between electrodes of the smoothing capacitor. A capacitor connection electrode as an electrode may be electrically connected to a terminal of the smoothing capacitor formed on the element mounting surface, and the switching element is placed on the element mounting surface such that a terminal of the switching element is electrically connected to the capacitor connection electrode.

Abstract: A bandpass filter module includes a mounting board and a BPF chip mounted on a surface thereof. The BPF chip includes three or more resonators; a first-stage resonator located closest to an input terminal, a final-stage resonator located closest to an output terminal, and a middle-stage resonator connected between the first-stage and the final-stage resonators and located in a chip middle zone. The mounting board includes an area overlapping with the chip middle zone, viewed in plan, defining a ground-free space in which no ground electrode is disposed. The ground-free space is formed at least from the surface of the mounting board to a depth position at which a topmost internal wiring layer is located. The middle-stage resonator is prevented from being coupled to ground electrodes on the mounting board and from a lower Q-value and increased insertion loss.

Abstract: In one embodiment, an apparatus includes a first reference voltage coupled to a first metal layer and a second reference voltage coupled to a second metal layer. A first finger type in the plurality of fingers is coupled to the first metal layer at a first area and coupled to the first metal layer and the second metal layer at a second area. A second finger type in the plurality of fingers is coupled to the second metal layer at the first area and coupled to the first metal layer and the second metal layer at the second area. Also, the first finger type and the second finger type alternately positioned next to each other.

Abstract: There are provided a multilayer ceramic electronic component and a method of manufacturing the same. The multilayer ceramic electronic component includes: a ceramic body including a dielectric layer; first and second internal electrodes disposed within the ceramic body to face each other, while having the dielectric layer interposed therebetween; and first external electrodes electrically connected to first and second internal electrodes and second external electrodes formed on the first external electrodes, wherein the first and second external electrodes include a conductive metal and a glass, and when the second external electrodes are divided into three equal parts in a thickness direction, an area of the glass in central parts thereof with respect to an area of the central parts is 30 to 80%. Therefore, sealing properties of a chip is improved, whereby a multilayer ceramic electronic component having improved reliability may be implemented.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor structure disposed on the substrate. The capacitor structure includes a first conductive component; a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component. The first, second and third conductive components are separated from each other by respective dielectric material.

Abstract: A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.

Abstract: A multi-layer capacitor includes a first capacitor layer and a second capacitor layer adjacent and substantially parallel to the first capacitor layer. The second capacitor layer has a surface area that is less than the surface area of the first capacitor layer.

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

Abstract: According to one embodiment of a capacitor module, the capacitor module includes a substrate having a metallization on a first side of the substrate, a plurality of connectors electrically coupled to the metallization and a plurality of capacitors disposed on the metallization. The plurality of capacitors includes a first set of capacitors electrically connected in parallel between a first set of the connectors and a second set of the connectors. The capacitor module further includes a housing enclosing the plurality of capacitors within the capacitor module.

Abstract: Apparatuses, multi-chip modules, capacitive chips, and methods of providing capacitance to a power supply voltage in a multi-chip module are disclosed. In an example multi-chip module, a signal distribution component may be configured to provide a power supply voltage. A capacitive chip may be coupled to the signal distribution component and include a plurality of capacitive units. The capacitive chip may be configured to provide a capacitance to the power supply voltage. The plurality of capacitive units may be formed from memory cell capacitors.

Abstract: Integrated circuits with decoupling capacitor circuitry are provided. The decoupling capacitor circuitry may include density-compliance structures. The density-compliance structures may be strapped to metal paths driven by power supply lines. Strapping density-compliance dummy structures in this way may increase the capacitance per unit area of the decoupling capacitor circuitry. Strapping density-compliance dummy structures in this way may shield the decoupling capacitor from nearby noisy signal sources.

Abstract: A capacitive device includes a first capacitor including a first wiring layer, a first dielectric film, a first conductive layer, a first insulating layer on the first capacitor, a second capacitor on the first insulating layer including a second conductive layer, a second dielectric film, and a third conductive layer, a second insulating layer on the second capacitor, a second wiring layer on the second insulating layer including first and second connection wires, a first via connecting the first wiring layer to the second conductive layer, a second via connecting the third conductive layer to the second wiring layer, a third via connecting the first connection wire to the first conductive layer, and a fourth via connecting the second connection wire to the first wiring layer.

Abstract: In a structure or device having a pair of electrical conductors separated by an insulator across which a voltage is placed, resistive layers are formed around the conductors to force the electric potential within the insulator to distribute more uniformly so as to decrease or eliminate electric field enhancement at the conductor edges. This is done by utilizing the properties of resistive layers to allow the voltage on the electrode to diffuse outwards, reducing the field stress at the conductor edge. Preferably, the resistive layer has a tapered resistivity, with a lower resistivity adjacent to the conductor and a higher resistivity away from the conductor. Generally, a resistive path across the insulator is provided, preferably by providing a resistive region in the bulk of the insulator, with the resistive layer extending over the resistive region.

Abstract: A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second voltage applied thereto; and a gate electrode disposed on an upper portion of the first well or an upper portion of the second well in such a way that the gate electrode is insulated from the first well or the second well, wherein capacitances of the capacitor device include a first capacitance between the first well and the second well and a second capacitance between the first well or the second well and the gate electrode.

Abstract: Substrates having power planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a first power plane and a second power plane. The at least one noise suppression structure may include a first power plane extension that extends from the first power plane generally toward the second power plane, and a second power plane extension that extends from the second power plane generally toward the first power plane. Methods for suppressing noise in at least one of the first power plane and second power plane include providing such noise suppression structures between the power planes.

Abstract: A capacitor having a stem that is designed to be inserted into a single, large-diameter via hole drilled in a printed circuit board is provided, wherein the stem may have conductive rings for making the positive and negative connections to the printed circuit board power distribution planes. Inside the capacitive stem, current, or at least a portion thereof, may be carried to the main body of the capacitor through low-inductance plates that are interleaved to maximize their own mutual inductance and, therefore, minimize the connection inductance. Alternatively, the capacitor may include a coaxial stem that forms a coaxial transmission line with the anode and cathode terminals forming the inner and outer conductors.

Abstract: There are provided a ceramic electronic component and a method of manufacturing the same. The ceramic electronic component includes: a ceramic element; and an internal electrode layer formed within the ceramic element, having a thickness of 0.5 ?m or less, and including a non-electrode region formed therein, wherein an area ratio of the non-electrode region to an electrode region of the internal electrode layer, in a cross section of the internal electrode layer is between 0.1% and 10%, and the non-electrode region includes a ceramic component.

Abstract: A method of manufacturing an embedded passive device for a microelectronic application comprises steps of providing a substrate (110, 210, 310), nanolithographically forming a first section (121, 221, 321) of the embedded passive device over the substrate, and nanolithographically forming subsequent sections (122, 222, 322) the embedded passive device adjacent to the first section. The resulting embedded passive device may contain features less than approximately 100 nm in size.

Abstract: A clad capacitor and method of manufacture includes assembling a preform comprising a ductile, electrically conductive fiber; a ductile, electrically insulating cladding positioned on the fiber; and a ductile, electrically conductive sleeve positioned over the cladding. One or more preforms are then bundled, heated and drawn along a longitudinal axis to decrease the diameter of the ductile components of the preform and fuse the preform into a unitized strand.

Abstract: A connector assembly for an implantable medical device includes a plurality of feedthroughs mounted in a conductive array plate, each feedthrough in the plurality of feedthroughs including a feedthrough pin electrically isolated from the conductive array plate by an insulator and an electronic module assembly including a plurality of conductive strips set in a non-conductive block. The plurality of conductive strips is in physical and electrical contact with the feedthrough pins at an angle of less than 135 degrees. The connector assembly further includes at least one circuit, the circuit including a plurality of conductors corresponding to the plurality of feedthroughs. The plurality of conductors of the circuit is in physical and electrical contact with a corresponding one of the conductive strips of the plurality of conductive strips of the electronic module assembly at an angle of less than 135 degrees.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: Embodiments of the present invention provide an arrangement structure capable of reducing noise caused by a laminated ceramic capacitor mounted on a printed circuit board. A unit arrangement structure includes ceramic capacitors. Among the laminated ceramic capacitors, capacitors are arranged so that capacitor axes thereof extend along a first axis, while the other ceramic capacitors are arranged so that capacitor axes thereof extend along a second axis crossing the first axis. In accordance with such an arrangement structure, it is possible to effectively suppress noise even in the case of single-side mounting.

Abstract: An electronic device package includes first and second electrodes of a package substrate. The first electrode has fingers formed from a first metal level and is configured to operate at a first DC potential. The second electrode has fingers formed from the first metal level interdigitated with the fingers of the first electrode. A via conductively connects the second electrode to a second metal level. The second metal level is configured to operate at a second DC potential. The first and second DC potentials are thereby capacitively coupled through the interdigitated electrodes.

Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The at least one noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Abstract: A die having a base formed of a first material is connected to a board having a base formed of a second material. An interposer having a coefficient of thermal expansion intermediate coefficients of thermal expansion of the first and second materials is positioned between the die and the board.

Abstract: A circuit substrate includes a resin layer; and an inorganic insulating layer including a groove portion penetrating the inorganic insulating layer in a thickness direction thereof. A part of the resin layer is in the groove portion.

Abstract: A decoupling device including a lead frame, multiple capacitor units, a protective layer and a packaging element is provided. The lead frame includes a cathode terminal portion and at least two opposite anode terminal portions disposed at two ends of the cathode terminal portion. The two anode terminal portions are electrically connected with each other through a conductive line. The capacitor units are connected in parallel and disposed on the lead frame. Each capacitor unit has a cathode portion and an opposite anode portion. The cathode portion is electrically connected with the cathode terminal portion. The anode portion is electrically connected with the anode terminal portion. The protective layer wraps at least one of the anode portion and the cathode portion of the capacitor unit. The packaging element covers the lead frame, the capacitor units and the protective layer. The packaging element exposes a bottom surface of the lead frame.

Abstract: An electronic apparatus includes an electronic component electrically connected to a substrate positioned beneath the electronic component. A member includes a plurality of decoupling capacitors having different voltages, and the decoupling capacitors are electrically connected to the electronic component. A plurality of voltage planes in the member are electrically connected to the decoupling capacitors. The decoupling capacitors, via the voltage planes in the member, provide different voltages to the voltage planes and thus the electronic component.

Abstract: A multilayer feedthrough capacitor has a capacitor element body of a substantially rectangular parallelepiped shape, a signal internal electrode, a ground internal electrode, first and second signal terminal electrodes, and a first ground terminal electrode. The capacitor element body includes first and second end faces opposed in a longitudinal direction thereof, and a mounting surface perpendicular to a direction in which a plurality of insulator layers are laminated. The first signal terminal electrode and the first ground terminal electrode are arranged in proximity to each other in a first region near the first end face in the mounting surface. The second signal terminal electrode is arranged in a second region near the second end face in the mounting surface. No conductor is arranged in a third region between the first region and the second region in the longitudinal direction of the capacitor element body, in the mounting surface.

Abstract: A thin-film device system includes a substrate and a plurality of pillars. The plurality of pillars project from a surface of the substrate. Each of the plurality of pillars have a perimeter that includes at least four protrusions that define at least four recessed regions between the at least four protrusions. Each of the at least four recessed regions of each of the plurality of pillars receives one protrusion from an adjacent one of the plurality of pillars. A thin-film device is fabricated over the plurality of pillars.

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract: A multi-layer film-stack and method for forming the multilayer film-stack is given where a series of alternating layers of conducting and dielectric materials are deposited such that the conducting layers can be selectively addressed. The use of the method to form integratable high capacitance density capacitors and complete the formation of an integrated power system-on-a-chip device including transistors, conductors, inductors, and capacitors is also given.

Abstract: A capacitor includes a substrate, a plurality of first storage electrodes, a plurality of second storage electrodes, a first supporting layer pattern, a dielectric layer and a plate electrode. A plurality of contact pads is formed I the substrate. The first storage electrodes are arranged along lines parallel with a first direction and electrically connected to the contact pads, respectively. The second storage electrodes are respectively stacked on the first storage electrodes. The first supporting layer pattern extends in a direction parallel with the first direction between adjacent second storage electrodes and makes contact with the adjacent second storage electrodes to support the second storage electrodes. The dielectric layer is formed on the first and second storage electrodes. The plate electrode is formed on the dielectric layer.