Abstract: The invention includes a capacitor. The capacitor has a first conductive capacitor electrode, a second conductive capacitor electrode, and a capacitor dielectric material intermediate the first and second capacitor electrodes. The dielectric material contacts both of the first and second capacitor electrodes. All of the dielectric material intermediate the first and second capacitor plates consists of silicon nitride.

Abstract: A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.

Abstract: A composite dielectric material useful in advanced memory applications such as dynamic random access memory (DRAM) cells is provided. The composite dielectric material of the present invention includes a mixed oxide such as TiO.sub.2 or Ta.sub.2 O.sub.5 that is interdiffused into a Si.sub.3 N.sub.4 film. Capacitors including the composite dielectric material of the present invention are also disclosed.

Abstract: Metal alkoxycarboxylate-based liquid precursor solutions are used form electronic devices (100) that include mixed layered superlattice materials (112) of a type having discrete oxygen octahedral layers (124) and (128) collated with a superlattice-generator layer (116). The precursor solutions include a plurality of metal moieties in effective amounts for yielding the layered superlattice materials. These metal moieties are mixed to include an A/B portion capable of forming an A/B layer (124), a perovskite-like AB layer portion capable of forming a perovskite-like AB octahedral layer (128), and a superlattice-generator portion capable of forming the superlattice-generator layer (116). The precursors are deposited in liquid form upon a substrate and annealed to provide the layered superlattice materials.

Abstract: High dielectric constant capacitors and/or inductors are formed on a substrate by depositing an amorphous layer (10) of a metal oxide on the substrate (12). A pattern is formed in the metal oxide by wet or dry etching to remove portions (17) of the amorphous material so that only portions (18) of the substrate remain covered. This pattern subsequently becomes the dielectric portion of the capacitor or the inductor. The patterned amorphous layer of metal oxide is then heated under conditions sufficient to convert it from amorphous to crystalline (16), thus increasing the dielectric constant.

Abstract: A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

Abstract: A method for forming a dielectric layer onto a substrate having a silicon surface includes initially depositing an oxidizable metal thin film onto the surface and thereafter depositing a thin film of a metal titanate compound, such as the zirconium titanate. The metal thin film is preferably formed of tantalum, titanium or zirconium. Following deposition of the metal titanate thin film, the metal titanate is annealed by heating in an oxidizing atmosphere at a temperature effective to recrystalize the titanate to increase the dielectric properties. During annealing, the metal film reacts with oxygen to form a metal oxide thin film intermediate the metal titanate thin film and the silicon surface. The oxidation of the metal thin film inhibits oxidation of the underlying silicon that would otherwise reduce the effective capacitance of the dielectric layer.

Abstract: A structure for providing an interface with an oxide surface which exhibits both high adhesion and preferred electrical properties. An embodiment includes a capacitor structure having one or two electrodes abutting a high dielectric thin film, whereby the electrodes comprise first partial layers of metal having favorable electrical properties and second continuous layers adjacent the first partial layers, with the second layer material having been chosen for its physical properties, and wherein the second material adheres to exposed areas of the thin film through openings in the partial metal layer.

Abstract: Applicant has discovered that the dielectric constant of Ta.sub.2 O.sub.5 can be significantly enhanced by the addition of small quantities of TiO.sub.2. Specifically, if Ta.sub.2 O.sub.5 is doped with more than about 3 mole percent of TiO.sub.2 the doped material will have a dielectric constant higher than the undoped material. For example, at a ratio of 0.92 Ta.sub.2 O.sub.5 :0.08TiO.sub.2, the dielectric constant is enhanced by a factor of more than three. Because both Ta and Ti are compatible with current microelectronics processing, the new dielectric can be used to make capacitors of reduced size with but minor modifications of conventional processes.

Abstract: The present invention provides a dielectric thin film capacitor element in which leak current may be suppressed from increasing over time while energizing at high temperature and which has excellent insulating quality and reliability and a manufacturing method thereof. The dielectric thin film capacitor element is constructed by forming a lower electrode, a dielectric thin film and an upper electrode one after another on a substrate, wherein the dielectric thin film capacitor element is characterized in that the dielectric thin film is made of an oxide material composed of at least titanium and strontium and containing erbium.

Abstract: Vias are formed in a dielectric film overlying an electrode layer by sweeping a laser beam over the area in which the via is to be formed. In particular, a Nd:YAG laser, producing a beam of light having a 266 nm wave length, effectively ablates a barium strontium titanate dielectric film, without adversely affecting an underlying platinum electrode. The present invention overcomes the problem of wet chemical etching of dielectric films to form vias. Wet chemical etching often requires etchants that adversely affect the underlying metal electrode and typically require the use of environmentally undesirable chemicals.

Abstract: Novel structures for capacitors which are capable of withstanding heat treatments to at least 400.degree. C. while providing low defect densities and low electrical series resistance in its electrodes are disclosed. In one embodiment of the present invention, a capacitor structure includes a bottom capacitor electrode formed of a first sub-layer of aluminum, a second sub-layer of tantalum nitride, and a third sub-layer of tantalum. The capacitor structure further includes a sputtered dielectric layer of tantalum pentoxide over the tantalum sub-layer of the bottom electrode. The resulting structure is anodized such that the underlying tantalum layer is fully anodized, and preferably such that a portion of the tantalum nitride layer is converted to a tantalum oxy-nitride.

Abstract: In a multi-functional multilayer device including a body (10) having a varistor section (2) and a capacitor section (3) stacked and integrated therewith, the adhesion between a varistor layer and a dielectric layer is improved when the varistor layer (22) contains zinc oxide as a main component and at least one lanthanide oxide as an auxiliary component, and the dielectric layer (32) contains titanium oxide or lanthanum/titanium oxide as a main component. The device experiences little warpage upon firing when glass is added to the dielectric layer. A high resistivity intermediate layer (5) disposed between the varistor and capacitor sections (2 and 3) prevents the deterioration or loss of varistor and capacitor properties by interdiffusion of elements between the varistor and capacitor sections.

Abstract: It is beneficial for an FPGA, PROM, DRAM and superconductive circuit to use a protective ceramic as its insulating material. This protective ceramic can densely cover metal surface and is free of defects. As a result, a high yield can be ensured. The Pilling-Bedworth ratio is a good indicator of the protective nature of an insulating material. It is desirable to limit the Pilling-Bedworth ratio larger than 1 and preferably smaller than 2. Multiple layers of ceramics can be used to further reduce the defect density and improve yield.

Abstract: The present invention relates to a MOS capacitor. According to this invention, the MOS capacitor has a transistor structure. One electrode of the capacitor is connected to an emitter of the transistor and the other electrode of the capacitor is connected to a collector of the transistor. When the MOS capacitor is biased by static electricity the electrostatic durability is improved, since an electrostatic discharge path is formed by breakdown of a collector and an emitter.

Abstract: A composite functional device is provided. The device includes a magnetic ceramic including an Ni--Zn ferrite; and a semiconductive including zinc oxide and an oxide of at least one of nickel and iron in an amount of from about 0.001 to 0.1 mol % in terms of NiO or Fe.sub.2 O.sub.3.

Abstract: A capacitor for use on silicon or other substrate has a multilayer electrode structure. In a preferred embodiment, a bottom electrode situated on the substrate has a bottom layer of Pt--Rh--O.sub.x, an intermediate layer of Pt--Rh, and a top layer of Pt--Rh--O.sub.x. A ferroelectric material such as PZT (or other material) is situated on the bottom electrode. A top electrode, preferably of identical composition as the bottom electrode, is situated on the opposite side of the ferroelectric from the bottom electrode.

Abstract: A capacitor using a dielectric film wherein plural capacitor units each including one or two capacitor elements are formed on an insulator upper electrodes of at least two capacitor elements of different capacitors units are electrically connected. Each of the capacitors includes a lower filmy electrode, a dielectric film formed on the lower filmy electrode, and an upper filmy electrode formed on the dielectric film. Since plural capacitor units are suitably connected to have desired characteristics, a great deal of flexibility is realized.

Abstract: Dielectric material of nominal composition (Al.sub.2 O.sub.3).sub.x (Ta.sub.2 O.sub.5).sub.1-x, with 0.03<x<0.15, unexpectedly can exhibit a relatively small temperature variation of the dielectric constant (e.g., <50 ppm/.degree.C. at 1 MHz and 20.degree. C.) and a relatively large value of the dielectric constant. The dielectric according to the invention advantageously is used in capacitive elements, e.g., in MOS capacitors in integrated circuits for personal communication devices.

Abstract: A ferroelectric capacitor used as a memory cell in a ferroelectric random access memory (FRAM) is provided. The ferroelectric capacitor includes a substrate, an insulating layer formed on the substrate, a Rh lower electrode provided on the insulating layer, an adhesive layer between the insulating layer and the lower electrode, a ferroelectric layer provided on the lower electrode, and a Rh upper electrode provided on the ferroelectric layer. The Rh used as the electrode material is not affected by diffusion of Si due to its fine structure when compared to a Pt electrode, and has excellent electrical properties due to better electrical conductivity and good heat-transfer properties.

Abstract: A capacitor is formed of at least two metal conductors having a multilayer dielectric and opposite dielectric-conductor interface layers in between. The multilayer dielectric includes many alternating layers of amorphous zirconium oxide (ZrO.sub.2) and alumina (Al.sub.2 O.sub.3). The dielectric-conductor interface layers are engineered for increased voltage breakdown and extended service life. The local interfacial work function is increased to reduce charge injection and thus increase breakdown voltage. Proper material choices can prevent electrochemical reactions and diffusion between the conductor and dielectric. Physical vapor deposition is used to deposit the zirconium oxide (ZrO.sub.2) and alumina (Al.sub.2 O.sub.3) in alternating layers to form a nano-laminate.

Abstract: When forming a zinc-deposited base material for metallized capacitors, a primer layer for zinc-deposition made from at least one compound selected from the group comprised of an oxide of silicon, titanium and zirconium is formed on at feast one side surface of a base body comprised of a film or a thin condenser paper. Next, a zinc-deposited layer is formed on top of the primer layer. Then, a protective layer made from at least one compound selected from the group comprised of silicon-based oil, fluoro-based oil, alkylnaphthalene, polydiphenylether, fatty acids, fatty acid salts and paraffin wax is formed on top of the zinc-deposited layer. In this way, it becomes possible to form a zinc-deposited base material having excellent moisture resistance when used for metallized capacitors.

Abstract: In a ceramic substrate with a thin-film capacitor, having a ceramic substrate a lower electrode layer formed on the ceramic substrate, a dielectric layer formed on the lower electrode layer and made of an oxide of a material constituting the lower electrode layer, and an upper electrode layer formed on the dielectric layer, a plating layer is provided between the ceramic base and the lower electrode layer to serve as a basis for the lower electrode layer.

Abstract: An improved ferroelectric capacitor exhibiting reduced imprint effects in comparison to prior art capacitors. A capacitor according to the present invention includes top and bottom electrodes and a ferroelectric layer sandwiched between the top and bottom electrodes, the ferroelectric layer comprising a perovskite structure of the chemical composition ABO.sub.3 wherein the B-site comprises first and second elements and a dopant element that has an oxidation state greater than +4. The concentration of the dopant is sufficient to reduce shifts in the coercive voltage of the capacitor with time. In the preferred embodiment of the present invention, the ferroelectric element comprises Pb in the A-site, and the first and second elements are Zr and Ti, respectively. The preferred dopant is chosen from the group consisting of Niobium, Tantalum, and Tungsten. In the preferred embodiment of the present invention, the dopant occupies between 1 and 8% of the B-sites.

Abstract: A semiconductor device in which an SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 um) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.

Abstract: The invention provides a multilayer ceramic chip capacitor which satisfies X7R property or a temperature response of its capacitance and shows a minimal change of capacitance with time under a DC electric field, a long accelerated life of insulation resistance (IR) and good DC bias performance and also provides a multilayer ceramic chip capacitor which is resistant to dielectric breakdown in addition to the above advantages. In a first form of the invention, dielectric layers contain BaTiO.sub.3 as a major component and MgO, Y.sub.2 O.sub.3, at least one of BaO and CaO, and SiO.sub.2 as minor components in a specific proportion. In a second form, the dielectric layers further contain MnO and at least one of V.sub.2 O.sub.5 and MoO.sub.3 as minor components in a specific proportion. In the first form, the dielectric layer has a mean grain size of up to 0.45 .mu.

Abstract: A conductive paste comprises a conductive powder and a glass frit, the glass frit consisting of PbO, B.sub.2 O.sub.3, SiO.sub.2, Al.sub.2 O.sub.3 and Bi.sub.2 O.sub.3, the content of Bi.sub.2 O.sub.3 in the glass frit being 4.0 to 30.2 percent by weight.

Abstract: A film capacitor in which the unmetallized margin is provided with a semiconductive layer. The layer provides a parallel resistive path within the capacitor, itself, obviating the need for an external resistor. It also grades the electric field across the margin, i.e., makes the field more uniform, thus allowing the margin to be made narrower without electrical breakdown, permitting a reduction in the physical size of the capacitor. A refractory, semiconductive layer is provided between the metal layer and the dielectric film. The refractory layer accelerates the self-clearing process, by insulating the underlying dielectric film from the heat generated by the vaporizing metal, thus hastening vaporization and reducing the tendency of the dielectric film to carbonize. As a result, faults are cleared with substantially less energy consumption. Preferably, the refractory layer is also semiconductive, to reduce field emission effects, and thereby decrease the frequency of faults in the dielectric film.

Abstract: A method of forming an integrated circuit capacitor is disclosed comprising the steps of providing a substrate, forming a conductive region at the substrate, and forming an insulating layer on the conductive region and the substrate. The method further comprises the steps of removing selective portions of the insulating layer to expose a selective area of the conductive region thereby forming a storage node contact window and forming a first conductive layer on the insulating layer and within the storage node contact window wherein the first conductive layer is in electrical communication with the conductive region. Next a cavity is formed in the first conductive layer. Subsequently, selected portions of the first conductive layer are removed leaving at least a remaining portion of the first conductive layer in which the cavity is formed thereby isolating the remaining portion of the first conductive layer from surrounding circuit elements.

Abstract: In an electronic device using lead zirconate titanate (PZT) or lanthanum lead zirconate titanate (PLZT) as the main insulating material, a PZT film or a PLZT film is formed on a sub-insulating layer consisting essentially of lead titanate, lanthanum lead titanate, barium titanate, strontium titanate, barium strontium titanate, lead zirconate, or lanthanum lead zirconate. In an MIS structure, a semiconductor, the sub-insulating layer, the PZT film and metal are deposited in order. In a capacitor, the sub-insulating layer and the PZT film are sandwiched between a pair of electrodes. The sub-insulating layer improves crystallinity of PZT or PLZT, and the dielectric constant. An oxide of Pb, La, Zr or Ti can be added as the sub-insulating layer in order to further suppress current leakage.

Abstract: A technique for decreasing the effective gain of a bipolar phototransistor at high light levels makes the image usable over a greatly extended range of illumination conditions. The effective current gain at high light levels is reduced by fabricating a "non-ideal" emitter, such as by inserting a thin 20 521 tunnel oxide between the emitter and base junction. The tunnel oxide between the emitter and base serves as a variable resistor as well as a good junction for carrier injection from the emitter. The total base voltage is the sum of the oxide voltage and the intrinsic base voltage. At high image intensity, the bipolar phototransistor will gradually enter into the saturation mode, i.e., the base to collector junction is forward biased. The beta is thus reduced. The bias of the collector should be about 0.3-0.8 V higher than the emitter at the 20.ANG. tunnel oxide thickness for optimum operation.

Abstract: A capacitance change switch with a resiliently deformable conductive pad compressible against a dielectric coating on the surface of a pair of spaced coplanar thin foil plates formed on a refractory substrate. The pad forms with the plates a pair of capacitors electrically in series. User movement of an actuator causes pad compression and a significant electrically detectible change in capacitance for effecting a switching function. In one embodiment the pad is formed of conductive elastomer and in another embodiment the pad is formed of non-conductive elastomer with a conductive foil covering.

Abstract: The multi-source raw material are dissolved in the tetra-hydrofuran, in a liquid state and evaporated simultaneously and stably transported to the reactor, thereby the dielectric thin film used for capacitor having a good performance is formed with a good repeatability. The present invention provides CVD raw material for oxide-system dielectric thin film wherein organic metal raw material is dissolved in the tetra-hydrofuran and the metal atom of the organic metal raw material is selected at least among Pb, Ti, Zr or alkaline earth metal. As a result, a stable dielectric thin film can be formed by CVD method and the dielectric thin film can be used for a capacitor for memory devices.

Abstract: An integrated circuit includes a layered superlattice material having the formula A1.sub.w1.sup.+a1 A2.sub.w2.sup.+a2 . . . Aj.sub.wj.sup.+aj S1.sub.x1.sup.+s1 S2.sub.x2.sup.+s2 . . . Sk.sub.xk.sup.+ak B1.sub.y1.sup.+b1 B2.sub.y2.sup.+b2 . . . Bl.sub.yl.sup.+bl Q.sub.z.sup.-2, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . Bl represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in non-volatile memories. Others are high dielectric constant materials that do not degrade or breakdown over long periods of use and are applied in volatile memories.

Abstract: A multi-region material structure and process for forming capacitors and interconnect lines for use with integrated circuits provides (1) capacitor first or bottom electrodes comprising a transition-metal nitride; (2) a capacitor dielectric comprising a transition-metal oxide; (3) capacitor second or top electrodes comprising a transition-metal nitride, a metal or multiple conductive layers; (4) one or more levels of interconnect lines; (5) electrical insulation between adjacent regions as required by the application; and (6) bonding between two regions when such bonding is required to achieve strong region-to-region adhesion or to achieve a region-to-region interface that has a low density of electrical defects.

Abstract: An integrated circuit metal-oxide-metal capacitor and method of making it which involves a support layer; a first conductive electrode on the support layer; a dielectric film on the first conductive electrode; a second conductive electrode disposed on the dielectric film and formed from the first level metallization interconnect layer of the integrated circuit; an interlevel dielectric layer; a first contact via extending through the interlevel dielectric layer and the dielectric film to the first conductive electrode; a second contact via extending through the interlevel dielectric layer to the second conductive electrode; and first and second terminals formed from the second level metallization interconnect layer of the integrated circuit contacting the first and second vias, respectively.

Abstract: A semiconductor integrated circuit apparatus according to the present invention has a capacitor formed in such a manner that a ferroelectric thin film is formed after a MOS transistor has been formed on a substrate thereof, a ferroelectric thin film made of, for example, PbZrTiO.sub.3 or SrTiO.sub.3 or the like is formed into a columnar shape to form electrodes positioned in direct contact with the side wall portions of said columnar ferroelectric thin film, and the top portion is removed.

Abstract: A high performance capacitor fabricated from nano-structure multilayer materials, such as by controlled, reactive sputtering, and having very high energy-density, high specific energy and high voltage breakdown. The multilayer capacitors, for example, may be fabricated in a "notepad" configuration composed of 200-300 alternating layers of conductive and dielectric materials so as to have a thickness of 1 mm, width of 200 mm, and length of 300 mm, with terminals at each end of the layers suitable for brazing, thereby guaranteeing low contact resistance and high durability. The "notepad" capacitors may be stacked in single or multiple rows (series-parallel banks) to increase the voltage and energy density.

Abstract: A capacitor having a high dielectric constant and method of making the same is disclosed. The capacitor comprises a bottom electrode comprising a conductive oxide deposited upon a substrate by chemical vapor deposition. A dielectric layer having a high dielectric constant is deposited upon the conductive oxide. Lastly, a counter electrode is formed upon the dielectric layer.

Abstract: A single metal-plate bypass capacitor (10) includes a metal top plate (26) separated from a silicon substrate (12) by a thermally-grown, silicon dioxide dielectric (16) layer. An additional silicon plate (36) can be included intermediate to the metal top plate (26) and the silicon substrate (12) for multiple power supply devices. The silicon substrate (12) is electrically accessed through a metal contact pad (28) overlying a doped region (34) of the silicon substrate (12). The metal contact pad (28) is electrically isolated from the top plate (26) by an isolation structure (30). The bypass capacitor (10) is designed to be attached directly to the top surface of a semiconductor device (18), which enables the bypass capacitor (10) to be interconnected to the semiconductor device (18) by a plurality of bonding wires (25) having a minimal length. Because the capacitor dielectric (16) is formed as a very thin layer by the thermal oxidation of silicon, the self-inductance of bypass capacitor (10) is minimized.

Abstract: A polyemitter structure having a thin interfacial layer deposited between the polysilicon emitter contact and the crystalline silicon emitter, as opposed to a regrown SiO.sub.x layer, has improved reproducibility and performance characteristics. A n-doped hydrogenated microcrystalline silicon film can be used as the deposited interfacial film between a crystalline silicon emitter and a polycrystalline silicon contact.

Abstract: An active matrix substrate comprising storage capacitors each having an insulating film formed of a single perovskite oxide or a solid solution composed of a plurality of the perovskite oxides. Since the perovskite oxide has a significantly high relative dielectric constant, the area of storage capacitor can be reduced while keeping or increasing the capacitance thereof. Further, the insulating film can be thickened as far as the insulation property thereof is not affected without the capacitance thereof being reduced, thereby preventing leakage current.

Abstract: A semiconductor device has a capacitor insulating film composed of a first and a second silicon nitride film. The surface of a lower electrode of impurity-doped polysilicon is transformed into the first silicon nitride film by thermal nitriding, and thereafter the second silicon nitride film is formed by chemical vapor deposition. An upper electrode is formed on the second silicon nitride film. A silicon oxide film may be formed on the second silicon nitride film by thermal oxidation. The capacitor insulating film which has a thickness of 5 nm or less in equivalent thickness of an oxide film reduces a leakage current and improves a long-term product reliability.

Abstract: A stacked trench capacitor including a first trench formed in a semiconductor substrate, an insulating material, preferably BPSG, substantially filling the first trench to thereby define an isolation region of the substrate, a second trench formed in the first trench, the second trench being much narrower and shallower than the first trench, a storage electrode formed on the sidewalls and bottom surface of the second trench, a thin dielectric film formed on the storage electrode, and a plate electrode formed on the thin dielectric film. In a preferred embodiment, the isolation region serves to separate and electrically isolate adjacent memory cells of a semiconductor memory device, each of the memory cells including a MOSFET transistor and a stacked trench capacitor constructed as described above.

Abstract: A microminiature, large capacitor for a semiconductor memory is formed from a raw material compound of plural different kinds of metal atoms for deposition, irrespective of the material, temperature and surface condition of a substrate, thereby forming a thin dielectric film having uniform characteristics not affected by the interface even though the film is made as thin as approximately 0.1 .mu.m. The microminiature large capacitance capacitor has a capacitance unaffected by an oxide existing at the interface between a ferroelectric and electrodes without using precious metals such as platinum having the least degree of freedom in deposition of thin films and microminiature processing. The ferroelectric thin film is deposited using an organic metal comprising a plurality of kinds of metal elements in conformity with the composition of a desired dielectric. As electrodes for use in forming a capacitor, a substance exhibiting conductivity after oxidation is preferably employed.

Abstract: A high-permittivity dielectric capacitor (28) having a refractory-metal oxide layer (16) framing the first electrode (14) of the capacitor (28) and separating a high-permittivity dielectric layer (24) from an insulating layer (12) underlying the capacitor (28). The high-permittivity dielectric layer (16) makes contact with the first electrode (14) through an opening (18) in the refractory-metal oxide layer (16). The refractory-metal oxide layer (16) separates the high-permittivity dielectric layer (24) from the insulating layer (12) in all regions away from the opening (18) in the refractory-metal oxide layer (16). During fabrication of the capacitor (28), when the high-permittivity dielectric layer (24) is patterned, the refractory-metal oxide layer (16) provides an etch-stop.

Abstract: An condenser microphone element including a silicon core, a layer of silicon dioxide thereon, and a layer of tantalum pentoxide thereon.

Abstract: Capacitor structure capable of achieving increased energy storage density is disclosed together with a fabrication sequence for the capacitor and its anodic oxide dielectric material. Soft porous aluminum oxide which has been formed in a first anodization step and has been densified or transformed to hard barrier oxide in a second anodization step is preferred for the capacitor dielectric material. The first anodization may be performed in a sulfuric acid electrolyte while the second anodization may be performed in a boric acid electrolyte. The boric acid may be diluted with ethylene glycol. The disclosed capacitor is fabricated on a silicon wafer substrate.

Abstract: This invention relates to ceramic high dielectric composition with BaTiO.sub.3 as major component; and by containing 1-5 weight part of CaTiO.sub.3, 2-3 weight parts of Nb.sub.2 O.sub.5 to 100 weight parts of the BaTiO.sub.3, a composition having dielectric constant of 3000 or above, less voltage dependency, a large bending strength and good high frequency characteristic is provided; and it has a good characteristic when used as thin film type dielectric body like multilayered ceramic capacitor.

Abstract: The components, of a microwave circuit, such as a filter, and a solid oscillator, etc. consists of a dielectric ceramic composition. A known BaO-TiO.sub.2 compound exhibits properties which make it suitable for use as the components of a microwave circuit but the resonance frequency linearity and the resonance frequency temperature coefficient are not excellent. The dielectric ceramic composition of the present invention is expressed by the formula of BaO.x{(1-y)TiO.sub.2.ySnO.sub.2 }, wherein x is 4.4 moles and y is from 0.06 to 0.09 mole, and has a mixed crystal structure of Ba(Ti.Sn).sub.4 O.sub.9 and Ba.sub.2 (Ti.Sn).sub.9 O.sub.20.