Solid Dielectric Patents (Class 361/311)
  • Patent number: 11081281
    Abstract: A multilayer ceramic electronic component includes a ceramic body including dielectric layers and a plurality of internal electrodes disposed to face each other with each of the dielectric layers interposed therebetween, and external electrodes disposed on external surfaces of the ceramic body and electrically connected to the internal electrodes, respectively. The external electrodes include electrode layers electrically connected to the internal electrodes and conductive resin layers disposed on the electrode layers, and the conductive layers are disposed to extend first and second surfaces of the ceramic body. When a distance from an outer edge of one of the first or second external electrodes disposed on a first or second surface to an inner edge thereof is defined as BW and surface roughness of the ceramic body is defined as Ra, a ratio of 100 times the surface roughness Ra to the distance BW (Ra*100/BW) satisfies (Ra*100/BW)?1.0.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 3, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Roc Lee, Dong Hwi Shin, Sang Soo Park, Woo Chul Shin
  • Patent number: 11075379
    Abstract: Oxide compositions comprising a modified structure which includes the formula ABOz. The A component may comprise at a cation of least one element selected from the group consisting of Mg, Ca, Sr, Ba, Sc, Y, La, Ce, Pr, Nd, Gd, and Zn, and the B component may comprise a cation of at least one element selected from the group consisting of V, Cr, Mn, Fe, Co, and Ni. Batteries and supercapacitors comprising the oxide compositions of the present disclosure and methods of making the oxide compositions of the present disclosure are also provided.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: July 27, 2021
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Christopher Brooks, Eric Kreidler
  • Patent number: 11037733
    Abstract: A multilayer ceramic capacitor includes a ceramic body including a plurality of dielectric layers stacked therein in a stacking direction; first and second external electrodes disposed externally on the ceramic body; first and second internal electrodes alternately stacked with the plurality of dielectric layers, forming an internal active layer of the ceramic body, and respectively connected to the first and second external electrodes; a dummy layer, including a conductive material and having a mesh shape, disposed in at least one of an upper cover layer or a lower cover layer respectively disposed above or below the internal active layer of the ceramic body in the stacking direction.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho In Jun, Sun Cheol Lee, Kyeong Jun Kim
  • Patent number: 11037731
    Abstract: A multi-layer ceramic electronic component includes a ceramic body enclosing internal electrodes laminated in a first direction, wherein the ceramic body has a main surface having a flat face normal to the first direction, a first side surface having a flat face normal to a second direction orthogonal to the first direction, and a rounded ridge connecting the main surface and the first side surface to each other and curved in a convex shape; a maximum dimension of the ceramic body in the first direction is 120 ?m or less; and the rounded ridge satisfies a condition of Rb/Ra>3.0, where Ra represents a dimension of the rounded ridge in the first direction and Rb represents a dimension of the rounded ridge in the second direction on a cross-sectional surface of the ceramic body taken along a virtual cut plane parallel to the first direction and the second direction.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yasutomo Suga, Shota Yajima
  • Patent number: 10998133
    Abstract: A dielectric material includes a layered metal oxide including a first layer having a positive charge and a second layer having a negative charge, wherein the first layer and the second layer are alternately disposed; a monolayered nanosheet; a nanosheet laminate of the monolayered nanosheets; or a combination thereof, wherein the dielectric material includes a two-dimensional layered material having a two-dimensional crystal structure, wherein the two-dimensional layered material is represented by Chemical Formula 1 X2[A(n?1)MnO(3n+1)]??Chemical Formula 1 wherein, in Chemical Formula 1, X is H, an alkali metal, a cationic polymer, or a combination thereof, A is Ca, Sr, La, Ta, or a combination thereof, M is La, Ta, Ti, or a combination thereof, and n?1.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daejin Yang, Jong Wook Roh, Doh Won Jung, Chan Kwak, Hyungjun Kim, Woojin Lee
  • Patent number: 10955720
    Abstract: An optical apparatus may comprise: an electrically reconfigurable optical layer comprising at least one phase-change material, wherein an optical property of the phase-change material is reconfigurable by an electric field; an optically transparent top electrode and a bottom electrode, the top and bottom electrodes configured to apply the electric field to the electrically reconfigurable optical layer, wherein the electrically reconfigurable optical layer is disposed between the optically transparent top electrode and the bottom electrode; and a colossal-K dielectric layer disposed between the electrically reconfigurable optical layer and the bottom electrode. The phase-change material of the electrically reconfigurable optical layer may comprise phase-change nickelate or tungsten oxide. The phase-change material of the electrically reconfigurable optical layer may have a perovskite structure.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 23, 2021
    Assignee: HRL Laboratories, LLC
    Inventors: Kyung-Ah Son, Jeong-Sun Moon, Ryan G. Quarfoth
  • Patent number: 10957485
    Abstract: A multilayer ceramic capacitor includes: a multilayer structure in which each of a plurality of dielectric layers and each of internal electrode layers are alternately stacked; wherein a main component of the dielectric layers is a ceramic material, wherein a main phase of the ceramic material has a perovskite structure expressed by a general formula ABO3, wherein a B site of the ceramic material includes an element acting as a donor; wherein an A site and the B site of the ceramic material includes a rare earth element, wherein (an amount of the rare earth element substitutionally solid-solved in the A site)/(an amount of the rare earth element substitutionally solid-solved in the B site) is 0.75 or more and 1.25 or less.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Katsuya Taniguchi, Tsuyoshi Sogabe
  • Patent number: 10943733
    Abstract: A ceramic dielectric including: a bulk dielectric including barium (Ba) and titanium (Ti); a ceramic nanosheet; and a composite dielectric of the bulk dielectric and the ceramic nanosheet.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeon Cheol Park, Chan Kwak, Kyoung-Seok Moon, Daejin Yang, Tae Won Jeong
  • Patent number: 10872774
    Abstract: A plasma processing apparatus includes: a processing chamber in which a sample is subjected to plasma treatment; a radio frequency power supply configured to supply radio frequency power that generates plasma; a sample stage on which the sample is placed; and an ultraviolet light source configured to apply an ultraviolet ray. The apparatus further includes a controller configured to control the ultraviolet light source such that before the radio frequency power is supplied into the processing chamber, a pulse-modulated ultraviolet ray is applied into the processing chamber.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: December 22, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Hao Xu, Hiroshige Uchida, Shigeru Nakamoto, Kousuke Fukuchi, Satomi Inoue
  • Patent number: 10867904
    Abstract: An integrated circuit structure includes: a first conductive plate disposed in a first layer on a semiconductor substrate; a second conductive plate disposed in a second layer on the semiconductor substrate; a plurality of conductive lines disposed in the first layer, for surrounding the first conductive plate; and a plurality of conductive vias arranged to couple the plurality of conductive lines to the second conductive plate; wherein the second layer is different from the first layer, and the first conductive plate is physically separated from the second conductive plate, the plurality of conductive lines, and the plurality of conductive vias.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tai-Yi Chen, Yung-Chow Peng, Chung-Chieh Yang
  • Patent number: 10847859
    Abstract: Embodiments of the present disclosure provide an arrangement for single wire communications (SWC) for an electronic device. In one instance, the arrangement may comprise a cable assembly to connect with the electronic device, wherein the cable assembly may include a wire to conduct SWC and a cover portion to cover a portion of the wire. The cover portion may comprise a ferro-dielectric material. The arrangement may further include a control logic coupled with the cable assembly, to adjust characteristics associated with the ferro-dielectric material, to tune a signal termination impedance value associated with the cable assembly. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Arvind Sundaram, Ramaswamy Parthasarathy, Vikas Mishra
  • Patent number: 10840025
    Abstract: In a thin film capacitor, a first electrode layer 1 has one or more regions B in which a distance Hb between a boundary surface I of the first electrode layer 1 and a dielectric layer 2, and a surface of the first electrode layer 1, becomes maximum, and an outer layer 12 has one or more regions T in which a distance Ht between the boundary surface I and a surface of the outer layer 12 becomes maximum, as well as one or more regions t in which the distance Ht between the boundary surface I and the surface of the outer layer 12 does not become maximum. A projected area SHb, a projected area SHt, and a projected area S, satisfy equations (1) and (2): 60%?(SHb/S)??(1); 60%?(SHt/S)??(2).
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 17, 2020
    Assignee: TDK CORPORATION
    Inventors: Hitoshi Saita, Masahiro Yamaki, Yukihiro Azuma, Yoshihiko Yano
  • Patent number: 10813220
    Abstract: An electronic component embedded substrate includes: a substrate that includes an insulating layer and has a first principal surface and a second principal surface; an electronic component that is embedded in the substrate and has at least one first terminal, at least one second terminal, and a capacity part; at least one via conductor that are formed in the insulating layer and electrically connected to the second terminal; and an adhesion layer that is in contact with the second terminal on an end face of the second terminal which are close to the second principal surface. The electronic component is laminated with the insulating layer, and adhesion strength between the adhesion layer and the insulating layer is higher than that between the second terminal and the insulating layer.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: October 20, 2020
    Assignee: TDK CORPORATION
    Inventors: Mitsuhiro Tomikawa, Koichi Tsunoda, Kazuhiro Yoshikawa, Kenichi Yoshida
  • Patent number: 10726994
    Abstract: A multilayer ceramic capacitor having a ceramic sintered body with alternately laminated dielectric layers and internal electrodes. The dielectric layers are formed from a perovskite-type compound represented by the general formula ABO3, and the perovskite-type compound contains at least Ti and a volatile element that forms a solid solution at a B site thereof. The internal electrodes are formed from a base metal material and contain the volatile element. The content of the volatile element is greater than 0 parts by mole and less than or equal to 0.2 parts by mole with respect to 100 parts by mole of the constituent element at the B site, and excluding the volatile element at the B site.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: July 28, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takafumi Okamoto
  • Patent number: 10699848
    Abstract: A multilayer ceramic electronic component includes: a ceramic body including a dielectric layer and first and second internal electrodes stacked to be alternately exposed to one side surface and the other side surface with the dielectric layer disposed therebetween; and first and second external electrodes disposed on an external surface of the ceramic body to be connected to the first and second internal electrodes, respectively, in which the ceramic body includes an area of overlap in a thickness direction of the first and second internal electrodes, margin region, and/or cover region, and the margin region in the width direction and/or the cover region includes a phosphoric acid-based second phase.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sim Chung Kang, Eun Jung Lee, Ki Pyo Hong, Yong Park
  • Patent number: 10645819
    Abstract: A printed wiring board includes a core substrate having cavity to accommodate an electronic component and including a front conductor layer formed on front side of the core substrate, and a back conductor layer formed on back side of the core substrate, through-hole conductors formed through the core substrate such that the through-hole conductors connect the front and back conductor layers of the core substrate, a front build-up layer formed on front surface of the core substrate and including interlayer insulating layers and conductor layers, and a back build-up layer formed on back surface of the core substrate and including interlayer insulating layers and conductor layers. The conductor layers in the front build-up layer include a conductor layer sandwiching one of the interlayer insulating layers with the front conductor layer such that the conductor layer and the front conductor layer have the same electric potential in region surrounding the cavity.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: May 5, 2020
    Assignee: IBIDEN CO., LTD.
    Inventors: Toshiki Furutani, Takema Adachi, Toshihide Makino, Yasushi Usami
  • Patent number: 10643791
    Abstract: Disclosed are a dielectric material, a multi-layered capacitor, and an electronic device including the same. The dielectric material includes a dielectric material particle represented by ADO3, wherein A includes Sr, Ba, Ca, Pb, K, Na, or a combination thereof, D includes Ti, Zr, Mg, Nb, Ta, or a combination thereof, the dielectric material particle includes about 2.5 moles to about 4 moles of the donor element, based on 100 moles of D, and a diameter of the dielectric material particle is in a range of from about 100 nanometers to about 300 nanometers.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Sik Kim, Yoon Chul Son, Kyoung-Seok Moon, Daejin Yang, Chan Kwak
  • Patent number: 10622157
    Abstract: An improved multilayer ceramic capacitor is described. The multilayered ceramic capacitor comprises first internal electrodes and second internal electrodes. The first internal electrodes and said second internal electrodes are parallel with dielectric there between. A first external termination is in electrical connection with the first internal electrodes and a second external termination is in electrical contact with the second internal electrodes. A closed void layer, comprising at least one closed void, is between electrodes.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 14, 2020
    Assignee: KEMET Electronics Corporation
    Inventor: John Bultitude
  • Patent number: 10600573
    Abstract: A capacitor component includes a body in which a dielectric layer and an internal electrode are alternately stacked, and an external electrode disposed on the body and connected to the internal electrode. The dielectric layer includes a composite layer including a dielectric material powder and a metallic particle and first and second protective layers including a dielectric material powder and spaced apart by the composite layer. A thickness of each of the first and second protective layers is equal to or greater than ? of a thickness of the dielectric layer.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Soon Kwon, Hyoung Uk Kim, Tae Young Ham, Jong Han Kim, Ki Myoung Yun, Jae Sung Park
  • Patent number: 10545058
    Abstract: Sensors, sensing arrangements and devices, and related methods are provided. In accordance with an example embodiment, an impedance-based sensor includes a flexible dielectric material and generates an output based on pressure applied to the dielectric material and a resulting compression thereof. In certain embodiments, the dielectric material includes a plurality of regions separated by gaps and configured to elastically deform and recover in response to applied pressure.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 28, 2020
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Zhenan Bao, Stefan Christian Bernhardt Mannsfeld, Jason Locklin, Chee-Keong Tee
  • Patent number: 10541087
    Abstract: A multilayer ceramic capacitor includes a ceramic body with first and second internal electrodes facing each other and dielectric layers interposed therebetween. First and second external electrodes are on external surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively. A dielectric layer includes dielectric grains including, respectively, first regions in which dysprosium (Dy) is not present and second regions surrounding the first regions. Where a shortest distance between boundaries of the first regions (in which dysprosium (Dy) is not present) of two of the dielectric grains is “L,” the concentration of dysprosium (Dy) in a region within ±0.2 L from a halfway point between the boundaries is lower than that of dysprosium (Dy) in the second regions.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Soon Kwon, Kyoung Jin Cha, Ji Hong Jo
  • Patent number: 10535465
    Abstract: A multilayer ceramic capacitor includes a ceramic body with first and second internal electrodes facing each other and dielectric layers interposed therebetween. First and second external electrodes are on external surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively. A dielectric layer includes dielectric grains including, respectively, first regions in which dysprosium (Dy) is not present and second regions surrounding the first regions. Where a shortest distance between boundaries of the first regions (in which dysprosium (Dy) is not present) of two of the dielectric grains is “L,” the concentration of dysprosium (Dy) in a region within ±0.2L from a halfway point between the boundaries is lower than that of dysprosium (Dy) in the second regions.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Soon Kwon, Kyoung Jin Cha, Ji Hong Jo
  • Patent number: 10490353
    Abstract: A multilayer ceramic capacitor includes a ceramic body with first and second internal electrodes facing each other and dielectric layers interposed therebetween. First and second external electrodes are on external surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively. A dielectric layer includes dielectric grains including, respectively, first regions in which dysprosium (Dy) is not present and second regions surrounding the first regions. Where a shortest distance between boundaries of the first regions (in which dysprosium (Dy) is not present) of two of the dielectric grains is “L,” the concentration of dysprosium (Dy) in a region within ±0.2 L from a halfway point between the boundaries is lower than that of dysprosium (Dy) in the second regions.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Soon Kwon, Kyoung Jin Cha, Ji Hong Jo
  • Patent number: 10490804
    Abstract: A method for producing a galvanic element includes applying a first electrode to a substrate, applying a separator to the first electrode, and applying a second electrode to the separator. At least one of the electrodes is applied in the form of a composite electrode using an aerosol separation method.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 26, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Tjalf Pirk, Dominik Hanft, Michael Butzin, Christine Engel, Ralf Moos
  • Patent number: 10490351
    Abstract: A multilayer ceramic capacitor includes a ceramic body with first and second internal electrodes facing each other and dielectric layers interposed therebetween. First and second external electrodes are on external surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively. A dielectric layer includes dielectric grains including, respectively, first regions in which dysprosium (Dy) is not present and second regions surrounding the first regions. Where a shortest distance between boundaries of the first regions (in which dysprosium (Dy) is not present) of two of the dielectric grains is “L,” the concentration of dysprosium (Dy) in a region within ±0.2L from a halfway point between the boundaries is lower than that of dysprosium (Dy) in the second regions.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Soon Kwon, Kyoung Jin Cha, Ji Hong Jo
  • Patent number: 10475579
    Abstract: A multi-layer ceramic capacitor includes a multi-layer unit and a side margin. The multi-layer unit includes ceramic layers laminated in a first direction, and internal electrodes disposed between the ceramic layers. The side margin covers the multi-layer unit from a second direction orthogonal to the first direction, the side margin having a higher concentration of a rare-earth element and a higher concentration of vanadium than center portions of the ceramic layers in the second direction.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Daisuke Sakate, Kotaro Mizuno
  • Patent number: 10395829
    Abstract: A dielectric resin composition for a film capacitor is a mixture containing an organic material A and an organic material B. The organic material A includes at least two kinds of organic material components A1, A2, . . . having reactive groups (for example, OH, NCO) that cross-link each other. The organic material B does not have a reactive site capable of reacting with the organic material A and has a dielectric loss tan ? of 0.3% or less at a temperature of 125° C. The mixture has a glass transition temperature of 130° C. or higher and preferably 280° C. or lower.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: August 27, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tomomichi Ichikawa, Norihiro Yoshikawa, Ichiro Nakamura, Shinichi Kobayashi, Ichiro Nakaso, Yasunori Hioki, Tomoki Inakura
  • Patent number: 10347422
    Abstract: Prismatic polymer monolithic capacitor structure operating at temperatures exceeding 140° C. and including multiple interleaving radiation-cured polymer dielectric layers and metal layers. Method for fabrication of same. The geometry of structure is judiciously chosen to increase sheet resistance of metal electrodes while reducing the capacitor's equivalent series resistance. Metal electrode layers are provided with a thickened peripheral portion to increase strength of terminating connections and are passivated to increase corrosion resistance. Materials for polymer dielectric layers are devised to ensure that the capacitor's dissipation factor remains substantially unchanged across the whole range of operating temperatures, to procure glass transition temperature that is no less than the desired operating temperature, and to optimize the absorption of ambient moisture by the polymeric layers.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 9, 2019
    Assignee: SIGMA TECHNOLOGIES, INT'L, LLC
    Inventor: Angelo Yializis
  • Patent number: 10319522
    Abstract: A multilayer ceramic capacitor includes: a capacitance layer including dielectric layers and first and second internal electrodes disposed with respective dielectric layers interposed therebetween; a protection layer disposed on one surface of the capacitance layer; an alpha connection electrode provided in an alpha via penetrating through the protection layer; and a beta connection electrode provided in a beta via penetrating through the capacitance layer and connected to the alpha via. The alpha via has a diameter greater than that of the beta via.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Taek Jung Lee, Hyo Youn Lee, Seung Woo Song, Jong Pil Lee, Sung Kwon An
  • Patent number: 10304631
    Abstract: A ceramic electronic component includes a ceramic body and external electrodes. The ceramic body includes ceramic layers formed of a ceramic material and laminated in a first axis direction, and internal electrode layers each including an extracted portion and disposed between the ceramic layers, the extracted portion being extracted to a circumference of each of the ceramic layers and having a width of 100 ?m or less along the circumference. The external electrodes contain the ceramic material, the external electrodes being provided to a surface of the ceramic body and each connected to the extracted portion.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: May 28, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Koichiro Morita
  • Patent number: 10290701
    Abstract: A MIM capacitor includes a bottom electrode, a middle electrode disposed over the bottom electrode, a top electrode disposed over the middle electrode, a first dielectric layer sandwiched between the bottom electrode and the middle electrode, and a second dielectric layer sandwiched between the middle electrode and the top electrode. A surface of the bottom electrode and a surface of the top electrode respectively comprise a Ra value lower than 0.35 nm and a Rq value lower than 0.4 nm.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Yao-Wen Chang
  • Patent number: 10290426
    Abstract: A capacitor component includes a substrate, a body disposed on one region of an upper surface of the substrate and having a porous structure, and a capacitor part including a first electrode, a dielectric layer, and a second electrode, formed on the porous structure of the body. The first and second electrodes extend to other regions of the upper surface of the substrate, respectively.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: May 14, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Il Lee, Byeong Cheol Moon
  • Patent number: 10236125
    Abstract: A dielectric ceramic composition contains: a barium titanate-based powder as a main ingredient; a first accessory ingredient containing Na; a second accessory ingredient containing Ba; and a third accessory ingredient containing Si. A content of the first accessory ingredient (based on moles of Na) is 0.3 to 4.0 moles per 100 moles of the main ingredient, and a Ba/Si ratio is in a range of 0.16 to 1.44.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: March 19, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seok Hyun Yoon, Jung Deok Park, Chang Hak Choi, Dong Hun Kim, Seung Ho Lee, Chan Hee Nam
  • Patent number: 10175188
    Abstract: A trenched base capacitive humidity sensor includes a plurality of trenches formed in a conductive layer, such as polysilicon or metal, on a substrate. The trenches are arranged parallel to the each other and partition the conductive layer into a plurality of trenched silicon electrodes. At least two trenched silicon electrodes are configured to form a capacitive humidity sensor. The trenches that define the trenched silicon electrodes can be filled partially (e.g., sidewall coverage) or completely with polyimide (Pl) or silicon nitride (SiN). A polyimide layer may also be provided on the conductive layer over the trenches and trenched electrodes. The trenches and the trenched silicon electrodes may have different widths to enable different sensor characteristics in the same structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 8, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Gary O'Brien, Ando Feyh, Andrew Graham, Ashwin Samarao, Gary Yama
  • Patent number: 10176922
    Abstract: In an embodiment, a multilayer ceramic capacitor 10 is constituted in such a way that four capacitive components C1 to C4 that are connected in series are formed between a first internal electrode layer group 14 and a second internal electrode layer group 15 adjacent to it, wherein, among the four capacitive components C1 to C4, the facing area Sc1 that defines the capacitance value of the capacitive component C1 closest to the first external electrode 12 and the facing area Sc4 that defines the capacitance value of the capacitive component C4 closest to the second external electrode 13 are greater than the facing areas Sc2 and Sc3 that define the capacitance values of the two remaining capacitive components C2 and C3, respectively. The multilayer ceramic capacitor is capable of satisfying the needs for both size reduction and voltage resistance increase.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 8, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yasuyuki Inomata, Shintaro Hayashi
  • Patent number: 10176928
    Abstract: In one embodiment, a system, comprising: a first non-magnetic conductive electrode; a second non-magnetic conductive electrode; a dielectric layer disposed between the first and second electrodes, the dielectric layer extending between the first and second electrodes; and first and second layers comprising plural pairs of magnetically coupled pairings of discrete magnets, the first and second layers separated by a non-magnetic material, wherein the magnets of at least the first layer are conductively connected to the first non-magnetic conductive electrode.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 8, 2019
    Assignee: E1023 CORPORATION
    Inventors: Daniel Albert Gabig, Matthew B. Jore
  • Patent number: 10154594
    Abstract: A printed circuit board including a circuit board having a cavity between an upper surface of the circuit board and a lower surface of the circuit board that are substantially parallel to each other, and a connection board including insulating layers substantially parallel with metal layers, the metal layers including metal patterns. The connection board is disposed in the cavity with the insulating layers and the metal layers of the connection board substantially perpendicular to the upper and lower surfaces of the circuit board.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 11, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jeong-Ho Lee, Young-Do Kweon, Hyoung-Joon Kim, Kyoung-Moo Harr, Kyung-Seob Oh
  • Patent number: 10109423
    Abstract: In an electronic component, each of a distance between a first outer electrode and a third outer electrode along a length direction and a distance between a second outer electrode and the third outer electrode along a length direction is about 8% to about 13% of a dimension of the electronic component along the length direction.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: October 23, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takanobu Katsuyama, Yasunari Nakamura, Naoto Muranishi, Takashi Sawada
  • Patent number: 10102978
    Abstract: Improved electrodes and currents through the use of organic and organometallic high dielectric constant materials containing dispersed conductive particles in energy storage devices and associated methods are disclosed. According to an aspect, a dielectric material includes at least one layer of a substantially continuous phase material comprising a combination of organometallic having delocalized electrons, organic compositions and containing metal particles in dispersed form, in another aspect, the novel material is used with a porous electrode to further increase charge and discharge currents.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: October 16, 2018
    Assignee: Cleanvolt Energy, Inc.
    Inventors: Zakaryae Fathi, John James Felten, James Elliott Clayton
  • Patent number: 10079117
    Abstract: A electric storage device that includes a device body having a first end face that has a first portion and a second portion, and second end face that has a third portion and a fourth portion. The second portion is inclined relative to the first portion, and the fourth portion is inclined relative to the third portion. A first electrode film extends from the first portion to the second portion, and a second electrode film extends from the third portion to the fourth portion.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: September 18, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroki Horiguchi, Kyotaro Mano, Tatsuya Mizushima
  • Patent number: 10074479
    Abstract: A manufacturing method for a multilayer capacitor includes alternately laminating dielectric layers and conductor layers including less than 50 included in a first arrangement and a second arrangement different from the first arrangement when viewed from a lamination direction to form a laminate in which at least one pair of the conductor layers adjacent to each other with the dielectric layer interposed therebetween are included in the first or second arrangement, pressing the laminate to stretch the conductor layers in a direction perpendicular or substantially perpendicular to the lamination direction, pressing the laminate to bend the conductor layers in the lamination direction, and forming first and second outer electrodes on laminate surfaces such that the first outer electrode is connected to the conductor layers included in the first arrangement and the second outer electrode is connected to the conductor layers included in the second arrangement.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: September 11, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masaki Tsukida, Hiroshi Masai
  • Patent number: 10045444
    Abstract: A printed circuit board includes: a core board including, on a first surface thereof, an element mounting part and an element non-mounting part; an insulation layer disposed on the element non-mounting part; a copper-clad laminate plate disposed on the insulation layer; a first penetration via penetrating the insulation layer and the copper-clad laminate plate; and a second penetration via disposed in the core board and connected to the first penetration via.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: August 7, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae-Ean Lee, Jee-Soo Mok, Young-Gwan Ko, Kyung-Hwan Ko, Yong-Ho Baek
  • Patent number: 10037851
    Abstract: A multilayer ceramic capacitor includes a laminated body including an inner layer portion including ceramic dielectric layers and internal electrodes, and outer layer portions including ceramic dielectric layers. External electrodes connected to the internal electrodes are provided on both ends of the laminated body. The main constituent of the inner layer portion is a perovskite-type compound represented by ABO3. The outer layer portions include first outer layers and second outer layers respectively containing oxides that differ from each other in main constituents, and boundary reaction layers are provided between the first outer layers and the second outer layers. First ceramic dielectric layers outside the boundary reaction layers differ in color from second ceramic dielectric layers inside the boundary reaction layers.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: July 31, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroyuki Wada, Kohei Shimada, Kenji Takagi, Tomomi Koga, Tomotaka Hirata, Hitoshi Nishimura, Hiroki Awata, Sui Uno
  • Patent number: 9978479
    Abstract: An electrode coating composition that includes at least one crosslinkable monomer; at least one hydrophobic monomer; and at least one dielectric constant enhancing agent selected from dielectric enhancing monomers, ferroelectric particulates, and electroactive polymers. Coatings including the polymer of compositions, and articles including electrically isolating layers are also disclosed.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: May 22, 2018
    Assignee: Corning Incorporated
    Inventors: Lenwood Lynell Fields, Arthur Winston Martin, Shawn Michael O'Malley, Dean Michael Thelen
  • Patent number: 9892863
    Abstract: The disclosure provides for electrochemical supercapacitors with high energy densities, based on paired groups of carbon nanotube mounted to conductive substrates. In one variation, the electrochemical supercapacitors are double layer capacitors, or electrochemical double layer capacitors, containing opposing groups of carbon nanotubes on opposing substrates. In another variation, the capacitor is an interdigitated capacitor of alternating electrode containing carbon nanotubes, mounted on a common substrate. Processes and devices are also described.
    Type: Grant
    Filed: May 24, 2015
    Date of Patent: February 13, 2018
    Assignee: Georgia Tech Research Corporation
    Inventor: William Jud Ready
  • Patent number: 9847203
    Abstract: A multi layer fuse device includes a substrate and an elongated fuse element, having a pair of contact pads formed therewith at opposed longitudinal ends thereof formed on one surface of the substrate. A pair of passivation layers are provided covering the fuse and contact pads. Windows may be opened through both passivation layers above both of the contact pads, and conductive electrode material is electroplated through the windows to contact the contact pads and to extend partially above a top surface of the passivation layers. Exposed electroplated material may be coated with solderable conductive material or a surface mount termination may be provided. Electroplated material may cover a portion of the fuse surface prior to application of the passivation layers and extend to an end of the substrate so that windows are not required.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: December 19, 2017
    Assignee: AVX Corporation
    Inventors: Alona Goldstein, Irina Daynov, Herzl Ovadia, Elinor O'Neill, Michael Dakhyia, Evgeny Glickman
  • Patent number: 9824820
    Abstract: A multi-layered capacitor device is provided in which the multi-layered capacitor device includes a metal or metal-oxide ground electrode, a capacitor dielectric layer, a metal or metal-oxide top electrode, a hole blocking layer and an electron blocking layer. The hole blocking layer is located at the interface of the metal or metal-oxide ground electrode and the capacitor dielectric layer to increases the effective barrier height at the interface. The electron blocking layer is located at the interface of the metal or metal-oxide top electrode and the capacitor dielectric layer to increases the effective barrier height at the interface.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 21, 2017
    Inventors: James Gerard Grote, Donna Marie Joyce, Fahima Ouchen
  • Patent number: 9812259
    Abstract: A multilayer ceramic capacitor may include: an active part including dielectric layers and internal electrodes which are alternately stacked therein; and a cover part disposed on at least one of an upper surface and a lower surface of the active part. The cover part may include an active part protective cover and an exterior cover, and the active part protective cover may be disposed adjacent to the active part.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung Ho Lee, Jong Han Kim, Min Gon Lee
  • Patent number: 9767958
    Abstract: An electrical capacitor includes a dielectric spacer. Metal electrodes are held in contact with opposite surfaces of the dielectric spacer by magnetic force.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: September 19, 2017
    Assignee: COHERENT LASERSYSTEMS GMBH & CO., LG
    Inventor: Igor Bragin
  • Patent number: 9721727
    Abstract: A multilayer ceramic capacitor has a laminate including dielectric layers laminated alternately with internal electrode layers of different polarities, wherein the dielectric layer contains ceramic grains having Ba, Ti, and X (wherein X represents at least one type of element selected from the group consisting of Mo, Ta, Nb, and W) and a variation in the concentration distribution of X above in the ceramic grain is within ±5%. The multilayer ceramic capacitor can offer excellent service life characteristics even when the thickness of the dielectric layer is 0.8 ?m or less, as well as excellent bias characteristics.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 1, 2017
    Assignee: TAIYO YUDEN CO., LTD
    Inventors: Chie Kawamura, Tetsuo Shimura, Minoru Ryu, Koichiro Morita, Yukihiro Konishi, Yoshiki Iwazaki