Distinct Physically Patents (Class 361/329)
  • Patent number: 10463863
    Abstract: A feedthrough includes a first printed circuit board, a first flexible conductive element coupled to and extending from an edge of the first printed circuit board, a second printed circuit board, and a second flexible conductive element coupled to and extending from an edge of the second printed circuit board.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: November 5, 2019
    Assignee: General Electric Company
    Inventors: Tobias Schuetz, Robert Roesner
  • Patent number: 10176925
    Abstract: Disclosed are apparatus and methodology for providing a precision laser adjustable (e.g., trimmable) thin film capacitor array. A plurality of individual capacitors are formed on a common substrate and connected together in parallel by way of fusible links. The individual capacitors are provided as laddered capacitance value capacitors such that a plurality of lower valued capacitors corresponding to the lower steps of the ladder, and lesser numbers of capacitors, including a single capacitor, for successive steps of the ladder, are provided. Precision capacitance values can be achieved by either of fusing or ablating selected of the fusible links so as to remove the selected subcomponents from the parallel connection. In-situ live-trimming of selected fusible links may be performed after placement of the capacitor array on a hosting printed circuit board.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: January 8, 2019
    Assignee: AVX Corporation
    Inventors: Kevin D. Christian, Gheorghe Korony
  • Patent number: 10008340
    Abstract: A composite electronic component includes a composite body formed by combining a multilayer ceramic capacitor (MLCC) and a tantalum capacitor. The composite electronic component has an excellent acoustic noise reduction effect, low equivalent series resistance (ESR)/equivalent series inductance (ESL), enhanced DC-bias characteristics, and a reduced chip thickness.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: June 26, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Ghyu Ahn, Byoung Hwa Lee, Sang Soo Park, Oh Choon Kwon, Hong Kyu Shin, Hyun Sub Oh, Jae Hyuk Choi
  • Patent number: 9953769
    Abstract: A composite electronic component includes an insulation sheet, a tantalum capacitor including a body part containing a sintered tantalum powder and a tantalum wire, a portion of which is embedded in the body part, and disposed on the insulation sheet, a multilayer ceramic capacitor including a ceramic body including a plurality of dielectric layers, first and second internal electrodes, and first and second external electrodes, and disposed on the insulation sheet, and a molded portion enclosing the tantalum capacitor and the multilayer ceramic capacitor. The first internal electrode includes a first lead portion led out to upper and lower surfaces and a first end surface of the ceramic body in a length direction, and the second internal electrode includes a second lead portion led out to the upper and lower surfaces and a second end surface of the ceramic body in the length direction.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Ghyu Ahn, Sang Soo Park, Byoung Hwa Lee, Kyo Kwang Lee
  • Patent number: 9847177
    Abstract: A composite electronic component includes a composite body having a multilayer ceramic capacitor and a tantalum capacitor coupled to each other, so as to have an excellent acoustic noise reduction effect, a low equivalent series resistance (ESR)/equivalent series inductance (ESL), improved direct current (DC)-bias characteristics, and a low chip thickness.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: December 19, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hong Kyu Shin, Hyun Sub Oh, Jae Hyuk Choi
  • Patent number: 9633794
    Abstract: A capacitor module of an inverter for a vehicle includes: a DC-link capacitor configured to be connected in parallel to an input of an inverter between a first high voltage input terminal and a second high voltage input terminal; and a plurality of Y-capacitors configured to be connected in parallel to the inverter. Each of the plurality Y-capacitors includes a first capacitor element connected between the first high voltage input terminal and a ground bus bar and a second capacitor element connected between the second high voltage input terminal and the ground bus bar, and the ground bus bars of the plurality of Y-capacitors are separately provided and the ground holes of the ground bus bars are disposed so as to face each other in a first direction.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: April 25, 2017
    Assignee: Hyundai Motor Company
    Inventors: Chang Han Jun, Seung Hyun Han, Jeong Yun Lee, Ho Tae Chun
  • Patent number: 9496086
    Abstract: An apparatus includes a case capable of receiving a plurality of capacitive elements, each capacitor element having at least two capacitors, and each capacitor having a capacitive value. The apparatus also includes a cover assembly with a peripheral edge secured to the case. The cover assembly includes, for each of the plurality of capacitive elements, a cover terminal that extends upwardly from the cover assembly generally at a central region of the cover assembly. Each cover terminal is connected to one of the at least two capacitors of the respective one of the plurality of capacitive elements. The cover assembly also includes, for each of the plurality of capacitive elements, a cover terminal that extends upwardly from the cover assembly at a position spaced apart from the cover terminal generally at the central region of the cover assembly.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: November 15, 2016
    Assignee: American Radionic Company, Inc.
    Inventors: Robert M. Stockman, Richard W. Stockman, Michael B. Tricano, Jonathan Charles
  • Patent number: 9412518
    Abstract: A mounting arrangement for a capacitor package is disclosed. The capacitor package is suitable for use in electric drive traction applications that are subjected to high vibration. Such a capacitor package is relatively large and requires a unique mounting arrangement in order to account for a large mass and high vibration environment. The mounting arrangement provides a clamp load plane that is near the center of mass of the capacitor package.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: August 9, 2016
    Assignee: Caterpillar Inc.
    Inventors: Todd Nakanishi, Jon Husser
  • Patent number: 9368566
    Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: June 14, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Jong-Hoon Lee, Young Kyu Song, Daeik Daniel Kim, Jung Ho Yoon, Uei-Ming Jow, Mario Francisco Velez, Jonghae Kim, Xiaonan Zhang, Ryan David Lane
  • Patent number: 9294064
    Abstract: A planar capacitor includes, in part, a first metal line forming spiral-shaped loops around one of its end point, and a second metal line forming spiral-shaped loops between the loops of the first metal line. The first and second metal lines are coplanar, formed on an insulating layer, and form the first and second plates of the planar capacitor. The planar capacitor may be used to form a filter. Such a filter includes a first metal line forming first spiral-shaped loops, a second metal line forming second spiral-shaped loops, and a third metal line—coplanar with the first and second metal lines—forming loops between the loops of the first and second metal lines. The filter further includes a first inductor coupled between the first and third metal lines, and a second inductor coupled between the second and third metal lines.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 22, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Young Kyu Song, Kyu-Pyung Hwang, Changhan Hobie Yun, Dong Wook Kim
  • Patent number: 9123477
    Abstract: Implementations and techniques for employing phase change materials in ultracapacitor devices or systems are generally disclosed.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: September 1, 2015
    Assignee: Empire Technology Development LLC
    Inventor: Ezekiel Kruglick
  • Patent number: 9025311
    Abstract: An improved high capacitance module for multi-layer ceramic capacitors is described. The module contains a flexible substrate comprising at least one first conductive trace and at least one second conductive trace. A first termination trace is in electrical connection with each first trace and a second termination trace is in electrical connection with each second trace. Each capacitor comprises interleaved conductors wherein alternate conductors are terminated to a first external termination and adjacent conductors are terminated to a second external termination. Each capacitor is mounted on the substrate with the first termination in electrical contact with the first trace and the second termination in electrical contact with the second trace. A housing with the substrate is received in the housing. A first lead tab is in electrical contact with the first termination wherein the first lead tab extends from the housing.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: May 5, 2015
    Assignee: Kemet Electronics Corporation
    Inventors: John Bultitude, John E. McConnell, Abhijit Gurav
  • Patent number: 8937801
    Abstract: There is provided an array-type multilayered ceramic electronic component including: a ceramic body; a plurality of external electrodes formed on one surface of the ceramic body and the other surface thereof opposing the one surface; and a plurality of internal electrode multilayered parts formed in the ceramic body and connected to the external electrodes, respectively, wherein when a gap between the internal electrode multilayered parts is G and internal electrode density is D, 40%?D?57%, 10 ?m?G?200 ?m, and G?(0.0577×D2)?(4.4668×D)+111.22. Therefore, delamination and cracking may be prevented.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: January 20, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hae Suk Chung, Byoung Hwa Lee, Min Cheol Park, Eun Hyuk Chae
  • Publication number: 20150002035
    Abstract: In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: David Schie, Mike Ward
  • Publication number: 20140347784
    Abstract: An apparatus includes a case capable of receiving a plurality of capacitive elements, each capacitor element having at least two capacitors, and each capacitor having a capacitive value. The apparatus also includes a cover assembly with a peripheral edge secured to the case. The cover assembly includes, for each of the plurality of capacitive elements, a cover terminal that extends upwardly from the cover assembly generally at a central region of the cover assembly. Each cover terminal is connected to one of the at least two capacitors of the respective one of the plurality of capacitive elements. The cover assembly also includes, for each of the plurality of capacitive elements, a cover terminal that extends upwardly from the cover assembly at a position spaced apart from the cover terminal generally at the central region of the cover assembly.
    Type: Application
    Filed: May 21, 2014
    Publication date: November 27, 2014
    Inventors: Robert M. Stockman, Richard W. Stockman, Michael B. Tricano, Jonathan Charles
  • Patent number: 8837113
    Abstract: A capacitor module is provided with a plurality of capacitors juxtaposedly disposed to have electrode terminals that are composed of positive electrode terminals and negative electrode terminals, respectively. Neighboring capacitors, among the plurality of capacitors, are disposed adjacent to each other to define neighboring electrode terminals, among the electrode terminals thereof, with the same polarity.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: September 16, 2014
    Assignee: Keihin Corporation
    Inventors: Seiichiro Abe, Kenichi Takebayashi
  • Patent number: 8837111
    Abstract: A capacitor forming unit according to one embodiment includes a dielectric plate with a plurality of through holes; a first conductor film formed on an upper surface of the dielectric plate; a first insulator film formed on the front end portion of the upper surface of the dielectric plate; a second conductor film formed on a lower surface of the dielectric plate; a second insulator film formed on the rear end portion of the lower surface of the dielectric plate; first electrode rods disposed in some of the through holes; and second electrode rods disposed in the remaining through holes where the first electrode rods are not disposed. The first electrodes are electrically connected to the first conductor film and electrically insulated from the second conductor film. The second electrode rods are electrically connected to the second conductor film and are electrically insulated from the first conductor film.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: September 16, 2014
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Yoshinari Take, Hidetoshi Masuda, Kenichi Ota
  • Patent number: 8830655
    Abstract: A capacitor (20A-E) formed as a roll of inner and outer electrode strips (21, 23) alternating with inner and outer dielectric strips (22, 24). Each of the dielectric strips (22, 24) is shorter than an inwardly adjacent one of the electrode strips (21, 23) at a radially outer end thereof (21 E, 23E). This exposes the radially outer end of each electrode strip on respectively different portions of an outer side surface (26, 28) of the capacitor. The exposed ends of the electrode strips may be arranged on opposite sides of the capacitor, such that stacking the capacitors interconnects them either in parallel, in series, or in combinations thereof in different embodiments.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: September 9, 2014
    Assignee: Trench Limited
    Inventors: Paolo Diamanti, Lorin Bratu, Ross McTaggart, Jorge Ribeiro, Keith Lobban
  • Patent number: 8755168
    Abstract: Provided is a package type multilayer thin film capacitor for a high capacitance, including: a capacitance block 110; a pair of clamp members 120 and 130 being installed on one side and another side of the capacitance block 110, respectively; a pair of lead members 140 and 150 being installed on the clam members 120 and 130, respectively; and a molding member 160 filling in the capacitance block 110 to partially expose each of the pair of lead members 140 and 150. The capacitance block may be configured by adhering at least two of a ceramic sintered member 111, a metal capacitance member 112, and a thin film capacitance member 113 using an insulating adhesive member and thereby disposing the at least two members in a multilayered form. Accordingly, capacitance may increase and mechanical strength may be enhanced.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: June 17, 2014
    Assignee: Samhwa Capacitor Co., Ltd.
    Inventors: Young Joo Oh, Jung Rag Yoon, Kyung Min Lee, Young Min Yoo
  • Publication number: 20140085772
    Abstract: A direct current (DC) link capacitor module includes a printed circuit board (PCB) formed by sequentially disposing a first electrode substrate, an insulation substrate, a second electrode substrate, a third electrode substrate; a plurality of DC link capacitors connected in parallel to each of the first electrode substrate and the second electrode substrate; a plurality of first Y-capacitors connected in series to each of the first electrode substrate and the third electrode substrate, and connected in parallel to the DC link capacitors; and a plurality of second Y-capacitors connected in series to each of the first electrode substrate and the third electrode substrate, and connected in parallel to the first Y-capacitors, thereby achieving a miniaturization and facilitating a fabrication by connecting the plurality of DC link capacitors using the PCB.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 27, 2014
    Applicant: SAMHWA CAPACITOR CO., LTD.
    Inventors: Young Joo OH, Jung Rag YOON, Kyung Min LEE, Young Min YOO
  • Patent number: 8670223
    Abstract: A case mold type capacitor is formed of multiple metalized film capacitors connected together in parallel and rigidly accommodated with molding resin within a case. The multiple metalized film capacitors are divided into a first block and a second block, and P-poles of each block confront each other, and N-poles thereof also confront each other. Bus-bars including a connection terminal for external connection at an end are connected to respective P-poles and N-poles of each block. The bus-bars connected to the P-poles are coupled together, and the bus-bars connected to the N-poles are coupled together. Each one of the bus-bars includes a section located on the opening side of the case with respect to the blocks. The bus-bars connected to the P-poles overlap in part, and the bus-bars connected to the N-poles also overlap in part.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 11, 2014
    Assignee: Panasonic Corporation
    Inventors: Takeshi Imamura, Yoshinari Nagata, Toshiharu Saito
  • Publication number: 20130214720
    Abstract: A hard start capacitor replacement unit has a plurality of capacitors in a container sized to fit in existing hard start capacitor space. The capacitors are 4 metallized film capacitors wound in a single cylindrical capacitive element. The container has a common terminal and capacitors value terminals for the plurality of capacitors, which may be connected singly or in combination to provide a selected capacitance. An electronic or other relay connects the selected capacitance in parallel with a motor run capacitor. The hard start capacitor replacement unit is thereby adapted to replace a wide variety of hard start capacitors.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 22, 2013
    Applicant: American Radionic Company, Inc.
    Inventor: American Radionic Company, Inc.
  • Patent number: 8416556
    Abstract: A power electronics module includes a capacitor having a trough-shaped housing and at least one capacitor winding. An electronic unit includes a base on which the capacitor is mounted. A cooling plate in thermal contact with a cooling surface of the capacitor is formed by a bus bar. The cooling plate is on the base of the electronic unit.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: April 9, 2013
    Assignees: Conti Temic Microelectronic GmbH, EPCOS AG
    Inventors: Wilhelm Grimm, Wilhelm Hübscher, Harald Vetter, Gerhard Hiemer, Edmund Schirmer, Hermann Kilian, Hermann Bäumel, George Dietrich
  • Patent number: 8395879
    Abstract: A bundled capacitor with a plurality of individual capacitors is described herein. Each bundled capacitor provides an individual capacitance value. The bundled capacitor can include a housing, a cap connected to the housing, a central common terminal, a plurality of auxiliary terminals, an interrupter, an insulating spider, an insulated collective connection, a thermal fuse, a frangible electrical connection, an insulating layer, a resin disposed around the capacitors, and an expansion chamber formed between the resin and the interrupter, enabling the cap to deform when one of the capacitors overheats in the bundled capacitor.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: March 12, 2013
    Assignee: Direct Brand, Ltd.
    Inventors: Malcolm Gorst, Ronald E. Loving
  • Publication number: 20130033156
    Abstract: An electrical condenser is disclosed for an automotive ignition system wherein the ignition system has first and second contact breaker points and first and second electrically conductive members electrically connected to the first and second contact breaker points, respectively, the first and second electrically conductive members having first and second faces, respectively, facing each other but not directly electrically connected to each other. The condenser comprises an attachment portion arranged to be interposed between the first and second faces of the electrically conductive members of the ignition system. The attachment portion has first and second oppositely facing electrically conductive faces for making electrical contact with the first and second faces, respectively, of the electrically conductive members of the ignition system.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 7, 2013
    Inventors: Kenneth Stanley TARGETT, Paul William BROWN
  • Patent number: 8336207
    Abstract: A method for supplying a plurality of capacitance values to a plurality of heating, ventilation, air-conditioning, and refrigeration (HVAC/R) components is provided. The method includes configuring a first set of terminals of a connection device to couple a first capacitor to the connection device and configuring the connection device to couple the first capacitor to at least one of the plurality of HVAC/R components. The method further includes configuring a second set of terminals of the connection device to couple a second capacitor to the connection device and configuring the connection device to selectively couple the second capacitor to at least one of the plurality of HVAC/R components.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: December 25, 2012
    Assignee: RBC Manufacturing Corporation
    Inventors: James Ryan Johnson, Francisco Javier Curiel
  • Publication number: 20120243144
    Abstract: A capacitor (20A-E) formed as a roll of inner and outer electrode strips (21, 23) alternating with inner and outer dielectric strips (22, 24). Each of the dielectric strips (22, 24) is shorter than an inwardly adjacent one of the electrode strips (21, 23) at a radially outer end thereof (21 E, 23E). This exposes the radially outer end of each electrode strip on respectively different portions of an outer side surface (26, 28) of the capacitor. The exposed ends of the electrode strips may be arranged on opposite sides of the capacitor, such that stacking the capacitors interconnects them either in parallel, in series, or in combinations thereof in different embodiments.
    Type: Application
    Filed: March 19, 2012
    Publication date: September 27, 2012
    Inventors: Paolo Diamanti, Lorin Bratu, Ross McTaggart, Jorge Ribeiro, Keith Lobban
  • Patent number: 8259431
    Abstract: The invention relates to a variable capacitor array which has excellent controllability on a capacitance value and has variable and high tunability.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: September 4, 2012
    Assignee: Kyocera Corporation
    Inventor: Hiroshi Katta
  • Patent number: 8213155
    Abstract: There is provided a multilayer chip capacitor a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged therein; and first to fourth outer electrodes, wherein the first capacitor unit includes first and second inner electrodes, and the first capacitor unit includes a plurality of capacitor elements each having a pair of the first and second inner electrodes repeatedly laminated, the second capacitor unit includes third and fourth inner electrodes, and the second capacitor unit includes at least one capacitor element having a pair of the third and fourth inner electrodes repeatedly laminated, and at least one of the capacitor elements of the first capacitor unit is different from the other capacitor elements of the first capacitor unit in a lamination number of the first and second inner electrodes or a resonant frequency.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: July 3, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byoung Hwa Lee, Sung Kwon Wi, Hae Suk Chung, Dong Seok Park, Sang Soo Park, Min Cheol Park
  • Publication number: 20120120548
    Abstract: A capacitor apparatus includes eight capacitor elements connected in parallel to an alternating-current current source. The impedance of a bus bar between the (j+1)th (j is 1 to 6) capacitor element and the (j+2)th capacitor element from a connecting terminal is (j+1) times the impedance of the bus bar between the first capacitor element and the second capacitor element from the connecting terminal. The impedance of the bus bar between the (j+1)th capacitor element and the (j+2)th capacitor element from a connecting terminal is (j+1) times the impedance of the bus bar between the first capacitor element and the second capacitor element from the connecting terminal.
    Type: Application
    Filed: June 16, 2010
    Publication date: May 17, 2012
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Yoshinobu Hasuka
  • Patent number: 8169772
    Abstract: Disclosed are apparatus and methodology for providing a precision laser adjustable (e.g., trimmable) thin film capacitor array. A plurality of individual capacitors are formed on a common substrate and connected together in parallel by way of fusible links. The individual capacitors are provided as laddered capacitance value capacitors such that a plurality of lower valued capacitors corresponding to the lower steps of the ladder, and lesser numbers of capacitors, including a single capacitor, for successive steps of the ladder, are provided. Precision capacitance values can be achieved by either of fusing or ablating selected of the fusible links so as to remove the selected subcomponents from the parallel connection. In-situ live-trimming of selected fusible links may be performed after placement of the capacitor array on a hosting printed circuit board.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: May 1, 2012
    Assignee: AVX Corporation
    Inventors: Kevin D. Christian, Gheorghe Korony
  • Patent number: 8159813
    Abstract: There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged in a laminated direction; and first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively, wherein the first capacitor unit includes first and second inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing a corresponding one of dielectric layers, the second capacitor unit includes third and fourth inner electrodes of different polarities alternately arranged in the capacitor body to oppose each other while interposing another corresponding one of the dielectric layers, the first and second capacitor units are electrically insulated from each other, and the first capacitor unit operates in a first frequency range and the second capacitor unit operates in a second frequency range lower than the first frequency range.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: April 17, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byoung Hwa Lee, Sung Kwon Wi, Hae Suk Chung, Dong Seok Park, Sang Soo Park, Min Cheol Park
  • Patent number: 8154846
    Abstract: A feedthrough capacitor assembly for attachment to a mount having an opening is disclosed. The assembly includes a feedthrough terminal adapted for insertion through said opening for coupling a signal from a first side of the mount to a second side of the mount. The assembly includes a first conductive region extending about and electrically coupled to the feedthrough terminal and a second conductive region extending about the first conductive region. A plurality of capacitors are electrically coupled between the first conductive region and the second conductive region. The plurality of capacitors are arranged about the feedthrough terminal with each capacitor having about the same capacitance as each of the other capacitors.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: April 10, 2012
    Assignee: Astec International Limited
    Inventors: Franz Fauer, Christoph Kopp
  • Patent number: 7995327
    Abstract: an exemplary film includes a base having an electrically insulating polymer which carries on one or both surfaces a sequence of electrically conductive coated areas which are separated by non-coated interstices. The film, which can include a superposition of films arranged one above another, can be shaped to form a capacitor. The capacitor can include a plurality of parallel electrodes which are insulated from each other. Each electrode can include one or more electrode layers formed by the coated areas that are separated by dielectric layers formed by sections of the base.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: August 9, 2011
    Assignee: ABB Research Ltd
    Inventors: Martin Carlen, Thomas Christen, Henning Fuhrmann
  • Publication number: 20110175630
    Abstract: The invention relates to a method for determining a functional area of an electronic textile (100;200). The electronic textile comprises a textile substrate having a first plurality of conductors (108a-b;202a-d), a second plurality of conductors (104a-c;204a-d), and a plurality of capacitors (112;212a-p), each capacitor comprising a conductor from the first plurality of conductors (108a-b;202a-d) and a conductor from the second plurality of conductors (104a-c;204a-d), separated by a dielectric (103a), the capacitors (112;212a-p) being distributed across substantially an entire surface of the electronic textile, wherein each capacitor (112;212a-p) has a capacitance of at least 10 pF.
    Type: Application
    Filed: September 10, 2009
    Publication date: July 21, 2011
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Rabin Bhattacharya
  • Publication number: 20110168782
    Abstract: A capacitance system for a radio frequency (RF) charge pump of an RF integrated circuit (IC) includes a fringe capacitor, a second capacitor, and a silicon substrate region. The fringe capacitor is made of backend masks. The second capacitor is located underneath the fringe capacitor. The silicon substrate region is located underneath the second capacitor.
    Type: Application
    Filed: January 12, 2010
    Publication date: July 14, 2011
    Applicant: NXP B.V.
    Inventors: EWALD BERGLER, ROLAND BRANDL, ROBERT SPINDLER, ROBERT ENTNER
  • Patent number: 7974072
    Abstract: A multilayer capacitor array having a plurality of multilayer capacitor devices formed in a single multilayer structure, the multilayer capacitor array including: a capacitor body formed by depositing a plurality of dielectric layers and having first and second side surfaces opposite to each other; a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer there between, and formed of a single electrode plate comprising a single lead, respectively; and a plurality of first polarity external electrodes and second polarity external electrodes, formed on the first side surface and second side surface, respectively, and connected to a correspondent polarity internal electrode via the lead, the first polarity external electrode formed on the first side surface and the second polarity external electrode formed on the second side surface, wherein the numbers of the first polarity external electro
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: July 5, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byoung Hwa Lee, Sung Kwon Wi, Hae Suk Chung, Dong Seok Park, Sang Soo Park, Min Cheol Park
  • Publication number: 20110032659
    Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 10, 2011
    Applicant: International Business Machines Corporation
    Inventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 7876547
    Abstract: Vertical parallel plate (VPP) capacitor structures that utilize different spacings between conductive plates in different levels of the capacitor stack. The non-even spacings of the conductive plates in the capacitor stack decrease the susceptibility of the capacitor stack of the VPP capacitor to ESD-promoted failures. The non-even spacings may be material specific in that, for example, the spacings between adjacent conductive plates in different levels of the capacitor stack may be chosen based upon material failure mechanisms for plates containing different materials.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: January 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ephrem G. Gebreselasie, Zhong-Xiang He, Steven H. Voldman
  • Patent number: 7848079
    Abstract: A capacitor assembly comprises a capacitor housing wherein a relatively larger main capacitor and at least one relatively smaller secondary capacitor can be enclosed and include an efficient and simple combination of electrical connections from the multiple capacitors to an external electrical connection interface. Another aspect includes a capacitor housing wherein volumetric efficiency is enhanced by the arrangement of the multi-capacitors within a given volume of a cavity of the housing. For a given size main capacitor and one or more secondary capacitors, the total volume of space occupied by those capacitors and the housing is minimized to take up minimum room in an electrical box.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: December 7, 2010
    Assignee: Musco Corporation
    Inventors: Myron K. Gordin, Gregory N. Kubbe, Kurt Charles Herr, Jr.
  • Publication number: 20100155158
    Abstract: A capacitor module in which the structure of a connecting portion is highly resistant against vibration and has a low inductance. The capacitor module includes a plurality of capacitors and a laminate made up of a first wide conductor and a second wide conductor joined in a layered form with an insulation sheet interposed between the first and second wide conductors. The laminate comprises a first flat portion including the plurality of capacitors which are supported thereon and electrically connected thereto, a second flat portion continuously extending from the first flat portion while being bent, and connecting portions formed at ends of the first flat portion and the second flat portion and electrically connected to the exterior.
    Type: Application
    Filed: March 1, 2010
    Publication date: June 24, 2010
    Applicant: Hitachi, Ltd.
    Inventors: Katsunori AZUMA, Masamitsu Inaba, Mutsuhiro Mori, Kenichiro Nakajima
  • Publication number: 20100033897
    Abstract: There is provided a multilayer chip capacitor a multilayer chip capacitor including: a capacitor body including first and second capacitor units arranged therein; and first to fourth outer electrodes, wherein the first capacitor unit includes first and second inner electrodes, and the first capacitor unit includes a plurality of capacitor elements each having a pair of the first and second inner electrodes repeatedly laminated, the second capacitor unit includes third and fourth inner electrodes, and the second capacitor unit includes at least one capacitor element having a pair of the third and fourth inner electrodes repeatedly laminated, and at least one of the capacitor elements of the first capacitor unit is different from the other capacitor elements of the first capacitor unit in a lamination number of the first and second inner electrodes or a resonant frequency.
    Type: Application
    Filed: December 19, 2008
    Publication date: February 11, 2010
    Inventors: Byoung Hwa Lee, Sung Kwon Wi, Hae Suk Chung, Dong Seok Park, Sang Soo Park, Min Cheol Park
  • Publication number: 20100020470
    Abstract: Systems, methods, and apparatuses for balancing capacitor load are provided. A system includes a plurality of capacitors, a plurality of respective positive connections and a plurality of respective negative connections that connect each of the plurality of capacitors to at least one power source, where each of the plurality of positive connections has an approximately equal length, and each of the plurality of negative connections has an approximately equal length.
    Type: Application
    Filed: July 25, 2008
    Publication date: January 28, 2010
    Applicant: General Electric Company
    Inventors: Howard Ross Edmunds, Cyrus David Harbourt, Amy Marlene Ridenour, Jeffrey Alan Melius
  • Patent number: 7619420
    Abstract: An apparatus includes a measurement device for measuring two capacitances. The apparatus also includes a display module that simultaneously displays at least two numerical values based on the measured capacitances.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: November 17, 2009
    Assignee: American Radionic Company, Inc.
    Inventor: Robert M. Stockman
  • Publication number: 20090146257
    Abstract: A capacitor includes a first capacitor structure on a substrate, the first capacitor structure including a first electrode, a first dielectric layer pattern, and a second electrode, a second capacitor structure on the first capacitor structure, the second capacitor structure including a third electrode, a second dielectric layer pattern, and a fourth electrode, at least one first contact pad on a side of the first electrode, and a wiring structure connecting the at least one first contact pad and the fourth electrode.
    Type: Application
    Filed: December 5, 2008
    Publication date: June 11, 2009
    Inventor: Kwan-Young Yun
  • Publication number: 20090128992
    Abstract: A highly linearized capacitor structure is formed by a first capacitor, that is coupled between a first terminal and a common node, combine with a second capacitor, that is coupled between a second terminal and the common node. When a bias voltage is applied, the capacitance values of the first and second capacitors combine and a capacitance variation of the first capacitor is compensated by a capacitance variation of the second capacitor to reduce and linearize overall capacitance variation in the combined capacitor structure.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 21, 2009
    Applicant: Broadcom Corporation
    Inventors: Nikolaos C. Haralabidis, Ioannis G. Kokolakis
  • Publication number: 20090128993
    Abstract: A multi-tier capacitor structure has at least one multi-tier conductive layer. At least one conductive via passes through the multi-tier conductive layer. When currents flow through the conductive via, different current paths are presented in the conductive via in response to different current frequency; in other words, different inductor is induced. Therefore, a single plate capacitor structure has function of hierarchical decoupling capacitor effect.
    Type: Application
    Filed: July 15, 2008
    Publication date: May 21, 2009
    Applicant: Industrial Technology Reaserch Institute
    Inventors: Shih-Hsien Wu, Min-Lin Lee, Shinn-Juh Lai, Shur-Fen Liu
  • Patent number: 7518890
    Abstract: A frequency converter in which the inductance is reduced by enlarging the forms of bus bars which connect a P phase, an N phase of an inverter part and a positive electrode or a negative electrode of smoothing capacitors and the form of a wiring bus bar which connects an intermediate layer of capacitors which are connected in series to enlarge areas where they overlap each other, and by making currents flow in the opposite directions to each other.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: April 14, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Hirota, Satoshi Ibori, Tomoya Kamezawa, Jiangming Mao
  • Patent number: 7518850
    Abstract: A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: April 14, 2009
    Assignee: International Business Machines Corporation
    Inventors: Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski
  • Patent number: RE41684
    Abstract: A set of integrated capacitor arrangements is presented, each of which has a circuitry-effective main capacitor and a connectable correction capacitor. Each capacitor arrangement has an electrically conductive antifuse connection and antifuse interruption between the correction capacitor and the main capacitor, which are produced after the main capacitor has been formed. The connection and interruption enable the capacitance of the capacitor arrangement to be corrected.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: September 14, 2010
    Assignee: Infineon Technologies AG
    Inventors: Armin Fischer, Franz Ungar