Abstract: A frequency converter in which the inductance is reduced by enlarging the forms of bus bars which connect a P phase, an N phase of an inverter part and a positive electrode or a negative electrode of smoothing capacitors and the form of a wiring bus bar which connects an intermediate layer of capacitors which are connected in series to enlarge areas where they overlap each other, and by making currents flow in the opposite directions to each other.

Abstract: A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.

Abstract: A multilayer capacitor has a multilayer body in which dielectric layers and internal electrode layers are alternately laminated, and terminal electrodes formed on each of two mutually opposed side faces of the multilayer body. Each internal electrode layer includes a plurality of internal electrodes arranged in an array direction along a direction perpendicular to a laminating direction of the multilayer body and parallel to the side faces. A plurality of internal electrodes included in one internal electrode layer are electrically connected to the terminal electrodes respectively. A distance between a plurality of internal electrodes included in one internal electrode layer is not less than 20 ?m nor more than 200 ?m.

Abstract: The present invention provides a capacitor device including a plurality of capacitor elements adjacent to each other along an axial direction are electrically connected to each other by fitting between a first terminal of one capacitor element and a second terminal of the other capacitor element, a intermediate plate allows the terminals fitted to each other between the capacitor elements adjacent to each other along the axial direction to penetrate through and positions these capacitor elements, an upper plate is electrically connected to the terminals of capacitor elements arranged on one end portion in the axial direction, a lower plate is electrically connected to the terminals of capacitor elements arranged on the other end portion in the axial direction, and all the capacitor elements are held in place by being sandwiched between the upper plate and the lower plate.

Abstract: An integrated capacitor assembly that offers improved performance characteristics in a convenient and space-saving package is provided. More specifically, the capacitor assembly contains a multi-anode stack of at least two electrolytic capacitors and at least one ceramic component, which are connected in parallel to common terminals within an encapsulating case. The resultant capacitor assembly is characterized by such performance characteristics as relatively high capacitance, low ESR, low piezoelectric noise, and space reduction. Reduced piezoelectric noise may be particularly advantageous for providing clear filtering in audio/video data processing and communication.

Abstract: An electrical component with a printed circuit board. The printed circuit board has an upper face and a lower face. A microprocessor is mounted to the upper face. A capacitor is mounted to the lower face. The capacitor has a first face parallel to the printed circuit board and a second face opposite to the first face. First plates and second plates are in alternating planar relationship with a dielectric therebetween and arranged in a plane perpendicular to the plane created by the circuit board. Each first plate has a first coupling tab and a power tab on opposing edges wherein the first coupling tab terminates at the first face and the power tab terminates at the second face. Each second plate of the second plates comprises a second coupling tab and a ground tab on opposing edges wherein the second coupling tab terminates at the first face and the ground tab terminates at the second face. The first coupling tab and the second coupling tab are in electrical contact with the microprocessor.

Abstract: A multilayer feedthrough capacitor array is provided with a capacitor element, and first to sixth terminal electrodes. The capacitor element has a plurality of laminated insulator layers, a first signal internal electrode and a first ground internal electrode disposed so as to face each other with the insulator layer in between, and a second signal internal electrode and a second ground internal electrode disposed so as to face each other with the insulator layer in between. The first signal internal electrode includes a first signal lead portion electrically and physically connected to the first terminal electrode, and a second signal lead portion electrically and physically connected to the second terminal electrode. The first ground internal electrode includes a first ground lead portion electrically and physically connected to the fifth terminal electrode, and a second ground lead portion electrically and physically connected to the sixth terminal electrode.

Abstract: A multilayer capacitor includes a multilayer body in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated, and a plurality of terminal electrodes formed on side faces of the multilayer body. The multilayer body has a first capacitor portion and a second capacitor portion. The first capacitor portion includes first and second internal electrodes as the internal electrodes. The second capacitor portion includes third and fourth internal electrodes as the internal electrodes. Each of the first to fourth internal electrodes is electrically connected through a lead conductor or through lead conductors to one or more corresponding terminal electrodes among the first to fourth terminal electrodes. The first and second capacitor portions have their respective capacitances different from each other.

Abstract: A capacitance type humidity sensor includes: a detection substrate including a detection portion on a first side of the detection substrate; and a circuit board including a circuit portion. The detection portion detects humidity on the basis of capacitance change of the detection portion. The circuit portion processes the capacitance change as an electric signal. The detection substrate further includes a sensor pad on a second side of the detection substrate. The sensor pad is electrically connected to the detection portion through a conductor in a through hole of the detection substrate.

Abstract: A plurality of high capacitance capacitors are coupled to supply or accept large currents. Bus bars are welded to the capacitors to provide improved thermal performance as well as self-supporting rigidity to the geometrical structure formed by the capacitors and the bus bars.

Abstract: An apparatus having a first set of contacts on a first side of the apparatus adapted to interface with a corresponding plurality of contacts on an integrated circuit package. The apparatus further includes a second set of contacts on a second side of the apparatus adapted to interface with a corresponding plurality of grid array leads, and a plurality of capacitive storage structures coupled to the first and second sets of contacts.

Abstract: A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes a first arm, a second arm, and a via. The first arm has a first end and a second end. The second arm has a third end and a fourth end. The first arm and the second arm intersect and the first, second, third and fourth ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the first and second arms.

Abstract: The present subject matter includes a capacitor stack having a first element having at least one first anode and at least one first cathode and a second element having at least one second anode and at least one second cathode. The capacitor stack is formed by the process of aligning the first element and the second element so that a first anode edge face of the first anode and a second anode edge face of the second anode form an anode connection surface for electrical connection of the first anode and the second anode. Additionally, the capacitor stack is formed by spraying metal on the anode connection surface to electrically connect the first anode and the second anode.

Abstract: The present invention is to provide a metallized film capacitor having a compact size, a large capacitance and a low inductance whereas number of parts is reduced. The metallized film capacitor comprises: a plurality of capacitor elements (1) provided with metallized contact electrodes (2) on both ends in the width direction; a bus-bar (3) to connect each of a plurality of electrodes (2) on one end; and a capacitor case (5) to house a plurality of capacitor elements (1), wherein a plurality of capacitor elements (1) are arranged in the capacitor case such that one side of electrodes (2) faces the opening surface of capacitor case (1) and each electrode (2) of one of both ends of each capacitor element (1) are positioned generally coplanarly.

Abstract: A set of integrated capacitor arrangements is presented, each of which has a circuitry-effective main capacitor and a connectable correction capacitor. Each capacitor arrangement has an electrically conductive antifuse connection and antifuse interruption between the correction capacitor and the main capacitor, which are produced after the main capacitor has been formed. The connection and interruption enable the capacitance of the capacitor arrangement to be corrected.

Abstract: A multilayered structure array has narrow pitches by making thinner coatings for insulating internal electrode layers from side electrodes and the productivity of the multilayered structure array is improved. The multilayered structure includes: a first internal electrode layer; a piezoelectric layer formed on the first internal electrode layer; a second internal electrode layer formed on the piezoelectric layer; a first coating formed on an end surface of the first internal electrode layer in a first side surface region of the multilayered structure and containing one of metal oxide, metal nitride, metal fluoride and metal sulfide in at least one part thereof; and a second coating formed on an end surface of the second internal electrode layer in a second side surface region of the multilayered structure and containing one of metal oxide, metal nitride, metal fluoride and metal sulfide in at least one part thereof.

Abstract: A multilayer ceramic condenser comprises a multilayer body constituted by a plurality of dielectric layers laminated together, first and second terminal electrodes respectively positioned on opposite side faces of the multilayer body, and a plurality of inner electrode groups provided within the multilayer body in a laminating direction of the multilayer body. Each inner electrode group includes a first inner electrode connected to the first terminal electrode, a second inner electrode connected to the second terminal electrode, and a third inner electrode connected to none of the first and second terminal electrodes. The first, second, and third inner electrodes are arranged so as to hold the dielectric layer therebetween such that a plurality of capacitors connected in series are formed between the first and second inner electrodes.

Abstract: A technique of increasing the corona inception voltage (CIV), and thereby increasing the operating voltage, of film/foil capacitors is described. Intentional venting of the capacitor encapsulation improves the corona inception voltage by allowing internal voids to equilibrate with the ambient environment.

Abstract: Upper, inner and lower sections (182, 180 and 184) of a PCB (100) are formed with each section having a substrate (140, 150 and 160) having patterned layers of metallization (105 and 110, 115 and 120, and 125 and 130), respectively. Some of the patterned layers of metallization (110, 115, 120, and 125) have thicker portions (171, 173) and part (188) of portion (186), and thinner portions (172, 174, 187, 190, 191, 192 and 193). The resultant thinner portion (175 and 194) in the prepreg layers (145 and 155) with the respective thicker portions of metallization provide decoupling capacitors, while the resultant thicker portions (196 and 198), for example, provide a lower capacitance for improved trace impedance for the signal traces (191 and 192).

Abstract: A capacitor including a first and second component capacitor structure disposed on a substrate. A component capacitor structure includes an upright arm, a transverse arm, and a via. The upright arm has a top end and a bottom end that extend at substantially right angles to a central axis of the upright arm. The transverse arm has a left and right end that extend at substantially right angles to a central axis of the transverse arm. The upright arm and the transverse arm intersect to form a cross-like pattern and the top, bottom, left and right ends all extend in the same rotary direction. The via is electrically coupled to an area of intersection of the upright and transverse arms.

Abstract: A capacitor assembly is formed from one or more capacitive elements placed between a pair of opposing brackets. Each bracket has at least one L-shaped section and an arcuate section. Each L-shaped section has a capacitor seating surface and an assembly connecting surface that is substantially perpendicular to the capacitor seating surface. The arcuate section is adjacent to the capacitor seating surface. The opposing ends of each capacitive element is in electrically contact with the capacitor seating surfaces on the opposing brackets. When secured to a bus bar by fasteners located in the regions formed by the arcuate sections of the opposing brackets the assembly connection surfaces serve as electrical and thermal conducting regions between the capacitor assembly and the bus bars. Alternatively a capacitor assembly may be secured to bus bars by fastening to the capacitor seating surfaces.

Abstract: An integrated circuit substrate having embdedded passive components provides a reduced cost and compact package for a die and one or more passive components. An insulating layer of the substrate is embossed or laser-ablated to generate apertures for insertion of a paste forming the body of the passive component. A resistive paste is used to form resistors and a dielectric paste is used for forming capacitors. A capacitor plate may be deposited at a bottom of the aperture by using a doped substrate material and activating only the bottom wall of the aperture, enabling plating of the bottom wall without depositing conductive material on the side walls of the aperture. Vias may be formed to the bottom plate by using a disjoint structure and conductive paste technology. Connection to the passive components may be made by conductive paste-filled channels forming conductive patterns on the substrate.

Abstract: In a differential capacitor1, first and second capacitors 1003 and 1004 are formed in substantially symmetrical positions from each other with respect to a vertical plane B-B?, on a semiconductor substrate 1020. The differential capacitor 1 further includes a shield plate 1022 interposed between the semiconductor substrate 1020 and the lower electrodes 1016 and 1018. When each of the lower electrodes 1016 and 1018 is projected onto the shield plate 1022 along the vertical direction, each projected lower electrode 1016 or 1018 has a partial overlap with the shield plate 1022.

Abstract: An electronic component includes: an element having a pair of terminal electrodes; and a pair of metal terminals formed of metal materials respectively and connected to the pair of terminal electrodes respectively, in which: a portion of the metal terminal that extends from a base-end side of the metal terminal connectable to an external circuit to face the terminal electrode of the element is an electrode facing portion; and a tip side portion of the metal terminal in the electrode facing portion is connected to the terminal electrode, and a gap exists between a base-end side portion of the metal terminal in the electrode facing portion and the terminal electrode. Therefore, the electronic component is capable of fully absorbing a stress and realizes reduction in production cost.

Abstract: An accumulating element module includes a plurality of accumulating elements, each having a positive pole terminal and a negative pole terminal at one end. The accumulating elements are connected together at their other ends by an insulating connecting member made of a synthetic rubber. The insulating connecting member includes a plurality of caps and connectors. A deformation-resistant, band-shaped, temperature sensing member having a plurality of excessively raised temperature detectors is inserted through the caps.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate, an insulation region which covers the capacitor and has a first hole and a second hole, the first hole being provided apart from the capacitor and extending in a vertical direction with respect to a main surface of the semiconductor substrate, the second hole reaching an electrode of the capacitor, extending in the vertical direction with respect to the main surface of the semiconductor substrate and being shallower than the first hole, a tungsten plug provided in the first hole, a first oxygen barrier film provided between the tungsten plug and a side wall of the first hole, and a conductive plug provided in the second hole and connected to the electrode of the capacitor.

Abstract: A capacitor is formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

Abstract: Disclosed is a capacitor for effectively shielding noise generated from a magnetron. According to an embodiment of the present invention, a case of the capacitor is combined with a ground plate in order that electrode insulation pipes integrally formed in the case extend through extending pipes mounted in the ground plate. Electrodes respectively extend through the electrode insulation pipes. A fixing cover is inserted through an upper opening of the case into the case to be disposed over the electrode insulation pipes, of which a fixing pipe extends through the case so as to come in contact with a screwed hole formed in the ground plate. The extending pipes respectively prevent unnecessary microwave noise generated from the magnetron. A length of the extending pipe is preferably in a range of 5 to 15 mm. Furthermore, the extending pipe and the electrode are made such that a sum of radiuses of the extending pipe and the electrode is less than 5 mm.

Abstract: An integrated circuit capacitor (60) uses multiple electrically conductive stacks (63-68, 70) to optimize capacitance density. A second stack (70) is a first nearest neighbor to a first stack (66). A third stack (65) is a second nearest neighbor to the first stack. Each of the three stacks defines vertices of an isosceles triangle (20) formed in a plane substantially perpendicular to the three stacks. The isosceles triangle does not have a ninety degree angle. The isosceles triangle may also be implemented as an equilateral triangle.

Abstract: A plastic package for use in semiconductor devices, which has a plurality of metallic terminals exposed on a package surface and a metallic bump attached to each of said terminals. The bumps are made of reflowable metal and have approximately uniform height. An adherent layer of polymer material covers the package surface and surrounds each of the bumps to form a solid meniscus. The layer has a thickness between a quarter and one half of the bump height. An analogous methodology applies to plastic assembly boards.

Abstract: The present specification discloses highly efficient capacitor structures. One embodiment of the present invention is referred to herein as a vertical parallel plate (VPP) structure. In accordance with this embodiment, a capacitor structure having a plurality of vertical plates. The vertical plates are substantially parallel to each other, and each vertical plate has multiple conducting strips. These conducting strips are substantially parallel to each other and are connected to each other by one or more vias. The vertical plates are alternately connected to each other, creating a first portion of the vertical plates and a second portion of the vertical plates, such that the first portion of the vertical plates forms a first terminal of the capacitor structure, and the second portion of the vertical plates forms a second terminal of the capacitor structure. Either slotted vias or individual vias can be used to connect the conducting strips.

Abstract: A mobile telephone device fitted with a transmitter and a receiver each having a high-frequency component with an integrated decoupling capacitor. The high-frequency component includes a substrate with the decoupling capacitor on one surface thereof, first and second current supply terminals for the capacitor on the same surface of the substrate as the capacitor, one capacitor electrode connected to a high frequency circuit and a DC voltage source, also on the one surface of the substrate, and the other capacitor electrode connected to ground.

Abstract: Capacitors comprising an inert porous shaped body onto which a first electrically conductive layer, a second layer of barium titanate and a further electrically conductive layer have been applied.

Abstract: A capacitive pressure sensor includes a first substrate (1), a first flat electrode (1a) formed on the first substrate (1), a pressure-sensing frame (4) surrounding the first flat electrode (1a) provided on the first substrate (1), second substrates (2, 3) connected to the pressure-sensing frame (4) opposedly to the first substrate (1) and forming a capacitance chamber (7) together with the first substrate (1) and the pressure-sensing frame (4), a stage (5) provided on the second substrates (2, 3) in the capacitance chamber (7), separated from the pressure-sensing frame (4), and opposed to and separated from the first flat electrode (1a), and a second flat electrode (2a) provided on the stage (5) and opposed to the first flat electrode (1a), wherein the pressure-sensing frame (4) deforms elastically according to a pressure applied to the first and second substrates (1, 2, 3).

Abstract: A multichannel parallel IC amplifier includes a plurality of amplifier circuits formed on an IC substrate. Each amplifier circuit is coupled to respective inputs via a pair of capacitors. The capacitors are configured so as to substantially equalize like sense and unlike sense coupling between adjacent channels, leading to cancellation of crosstalk signals.

Abstract: A flip chip-ball grid array package and a stiffening ring having first and second faces, and grooves formed in at least a one of the first and second faces of the stiffening ring. Providing grooves in at least one of the faces of the stiffening ring imparts of degree of flexibility to the stiffening ring to overcome and accommodate stresses induced in the manufacturing process associated with adhesive curing, solder reflow, chip underfilling and cavity filling, and differences in the coefficient of thermal expansion of the various materials used to construct the assembly. Furthermore, forming grooves in at least one of the faces of the stiffening ring provides increased surface area and therefore improves the heat transfer property of the stiffening ring. At the same time, the stiffening ring provides a sufficient degree of rigidity to the first substrate and to the microelectronic assembly in general to facilitate handling of the microelectronic assembly without damaging the chip or its solder connections.

Abstract: A multi-layer ceramic capacitor (MLC) device for low inductance decoupling applications is provided in which a first terminal is formed around substantially the entire periphery of the device body and a second opposing polarity terminal is formed by a through-via located generally in the middle of the device body. In an alternative embodiment, a plurality of surface mount MLC devices are mounted to a circuit board in a diamond arrangement so as to allow contacts of one polarity to be electrically connected to terminals of similar polarity which are located substantially around the entire periphery of each device body. Contacts of opposing polarity may be electrically connected to through-via terminals located generally in the middle of each device body. In a third embodiment, a single surface mount MLC device is provided in which all electrical connections between the circuit board and the device are made by through-via terminals which align with respective contacts on the circuit board.

Abstract: A capacitive electrical energy storage structure is fabricated as a thin-film device comprising electrodes on opposite sides of a dielectric layer. In one approach, a high surface area metallic sponge can be incorporated into the structure. The energy storage structure can comprise either single or multiple layers of capacitors connected in series, parallel, or a combination of such arrangements. The multi-layer capacitor structure can be either applied directly to supporting structures of portable or transportable devices or can be fabricated as a film which is applied as a laminate to such structures. Further, a conformal energy storage structure can be produced which is shaped to fit in voids within devices, which voids would otherwise be little used or unused.

Abstract: A multilayer electronic device comprised of a capacitor body in which a plurality of internal electrodes are separately arranged in a plurality of blocks via ceramic layers. At least one lead is led out from each internal electrode. The terminal electrodes connected to each lead is arranged at the side faces of the capacitor body. The polarities of the voltages supplied to the nearby terminal electrodes in the same side face differ.

Abstract: A long-lived, lightweight, and quickly and precisely charged storage capacitor power supply capable of stably supplying electric power to a load. The power supply has a capacitor block consisting of capacitors connected in series, in parallel or in any combination of series and parallel. The power supply further includes a charging circuit for charging the block, a charging power supply connected with the block via the charging circuit, and a charge-limiting circuit. This charge-limiting circuit detects the voltage across the terminals of the block and limits charging of the block if the voltage reaches a given value. One embodiment of the invention further includes a charge-limiting circuit, a full charge-detecting circuit, and a residual electricity-detecting circuit connected in parallel with the block. The charge-limiting circuit senses that the voltage across the terminals of the block exceeds the given value and causes the charging current to bypass the block.

Abstract: A fingered capacitor in an integrated circuit. A first capacitor element is formed in a first layer of an integrated circuit (IC) die. The first capacitor element includes a positive plate and a negative plate. Each of the positive and negative plates of the first capacitor element has a plurality of fingers interdigitated with the fingers of the other of the positive and negative plates of the first capacitor element. The fingers are separated by a dielectric. The interdigitated fingers cooperate to generate fringe capacitance between neighboring fingers. A plurality of capacitor elements having interdigitated fingers can be provided in adjacent layers of the IC die.

Abstract: A substantial comb-type lower electrode 11 is formed on a substrate 14, then a dielectric layer 13 is formed on the lower electrode 11, and then a substantial comb-type upper electrode 12 is formed on the dielectric layer 13. Respective element electrodes 16 (15) of one of the lower electrode 11 and the upper electrode 12 are arranged in blank areas between respective element electrodes 15 (16) of the other of the lower electrode 11 and the upper electrode 12.

Abstract: A multi-capacitor device having a plurality of capacitors in a single circuit package is formed of a plurality of layers of dielectric material, preferably the same type of material that is commonly used to fabricate circuit boards. The plurality of layers are disposed in a vertically stacked relationship. Each capacitor is formed of first and second pluralities of planar electrodes formed on alternating layers of the stack. The first plurality of electrodes is disposed in a first vertically stacked array, and the second plurality of electrodes is disposed in a second vertically stacked array. Each vertical electrode array is provided with a via hole extending through all of its layers to connect all of the respective electrode array in parallel. At the upper surface of the assembly, each via hole is connected to a solder pad and disposed to be soldered to a connection point on a printed circuit board or the like.

Abstract: In a power capacitor with a plurality of round, wound elements accommodated in a common housing at least one wound element group consisting of three round, wound elements is accommodated in the housing, with the wound elements of the group being arranged in star-form alongside one another, with their axes parallel to one another. The housing has in cross-section in general the shape of a triangle having rounded corners, with a radius of curvature which corresponds at least substantially to the radius of the round, wound elements.

Abstract: An obstacle is opposed to a lower electrode of a metal-insulator-metal capacitor so as to form a gap therebetween, thereafter, insulating material is deposited so as to fill the gap and form a dielectric layer of the metal-insulator-metal capacitor; even if the deposition does not achieve a conformal step coverage, the insulating material in the gap surely isolates the lower electrode from the upper electrode, and the lower electrode is never short-circuited with the upper electrode.

Abstract: The invention relates to an apparatus for a crater-style sampling capacitor. The apparatus includes a dielectric having a smooth crater shaped input electrode on a first surface and output and guard electrodes on a second surface. A sampling capacitor is defined by the input and output electrodes, and a guard capacitor is defined by the input and guard electrodes. The edge of input electrode is positioned below the first surface to increase surface flash over voltage, further, the input electrode is curved to eliminate corona discharge at edges of the input electrode and to reduce self-heating to negligible levels. The apparatus is suitable for high-voltage radio-frequency applications, such as a mass spectrometer, or other high-voltage applications that require an accurate sampling capacitor for amplitude control and accurate sampling of radio-frequency waveforms.

Abstract: A laser trimmable electronic device (1) has a housing (2) and a partially enclosed component (3) at least partially enclosed inside the housing (2) and electrically coupled to external connector terminals (4,5). The device (1) has a laser trimmable component (6) electrically coupled the external connector terminals (4,5), wherein at least part of the trimmable component (6) is mounted to an outer surface (7) of the housing (2).

Abstract: In a laminated capacitor, internal electrodes formed within a naked laminated body oppose a trimming electrode formed on a surface of the naked laminated body so as to obtain an electrostatic capacity, and the internal electrodes differ from one another in area opposed to the trimming electrode. By removing the trimming electrode from a portion where it is opposed to more of the internal electrodes toward another portion where it is opposed to less of the internal electrodes, the rate of decrease in electrostatic capacity with respect to the area of the trimming electrode is large at an initial stage of the trimming process and it gradually reduces in accordance with the progress thereof. Further, when the electrostatic capacity becomes to small through too much trimming, an adjusting layer between the trimming electrode and the internal electrode is deoxidized in a part thereof so that the portion of the adjusting layer is turned conductive to increase the electrostatic capacity thereof.

Abstract: A capacitive filter feedthrough assembly and method of making same are disclosed for shielding an implantable medical device such as pacemaker or defibrillator from electromagnetic interference or noise. A ferrule is adapted for mounting onto a conductive device housing by welding, soldering, brazing or gluing, and supports a terminal pin for feedthrough passage to a housing interior. A capacitive filter is mounted at the inboard side of a device housing, with capacitive filter electrode plate sets coupled respectively to the housing and the terminal pin by an electrically conductive combination of adhesive, brazing and soldering. In one embodiment of the invention, multiple capacitive filters are provided in an array within a common base structure, where each capacitive filter is associated with a respective terminal pin.

Abstract: A capacitor array layout technique for improving capacitor array matching. A capacitor array is laid out in a geometrical configuration wherein the geometrical configuration has a centerpoint. The geometrical configuration is divided into a plurality of first sections wherein each of the plurality of first sections have a corresponding second section diagonally located from and at an approximately equal distance from the centerpoint as said first section. Each of the of second sections house a capacitor set of a predetermined value wherein each of the plurality of first sections house a capacitor set of an equal value as the corresponding second section.