Shared Electrode Patents (Class 361/330)
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Patent number: 10811189Abstract: A rear bus bar includes a rear electrode connecting part connected to an upper end electrode of a capacitor element, and a rear overlapping part is led out upward from a rear electrode connecting part at a position overlapping with the upper end electrode. A front bus bar includes a front electrode connecting part connected to a lower end electrode of the capacitor element, a first relay part, and a second relay part extending along the upper end electrode, and a front overlapping part is led out upward from the second relay part. An insulation module includes a first insulating part interposed between the front overlapping part and the rear overlapping part, and a second insulating part interposed between the upper end electrode and the second relay part.Type: GrantFiled: August 1, 2018Date of Patent: October 20, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Takeshi Imamura, Toshihisa Miura, Eriko Kanatani
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Patent number: 9722622Abstract: The disclosure provides a capacitor array. The capacitor array includes one or more first metal plates vertically stacked parallel to each other. A second metal plate is horizontally stacked to couple one end of each first metal plate of the one or more first metal plates. One or more third metal plates are vertically stacked parallel to the one or more first metal plates. Each third metal plate of the one or more third metal plates is stacked between two first metal plates.Type: GrantFiled: April 22, 2016Date of Patent: August 1, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gehesh Edakkuttathil Muhammed, Naveen KV, Arun Mohan, Shagun Dusad
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Patent number: 9155199Abstract: The present invention relates to a passive device embedded in a substrate, which includes a laminate formed by alternately laminating a plurality of internal electrodes and dielectric layers; a first external electrode covering one side surface of the laminate and having a first upper cover region, which covers a part of an upper portion of the laminate, and a first lower cover region, which covers a part of a lower portion of the laminate and is smaller than the first upper cover region; and a second external electrode covering the other side surface of the laminate and having a second lower cover region, which covers a part of the lower portion of the laminate, and a second upper cover region, which covers a part of the upper portion of the laminate and is smaller than the second lower cover region, and the substrate.Type: GrantFiled: September 30, 2013Date of Patent: October 6, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yee Na Shin, Yul Kyo Chung, Seung Eun Lee
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Patent number: 9025311Abstract: An improved high capacitance module for multi-layer ceramic capacitors is described. The module contains a flexible substrate comprising at least one first conductive trace and at least one second conductive trace. A first termination trace is in electrical connection with each first trace and a second termination trace is in electrical connection with each second trace. Each capacitor comprises interleaved conductors wherein alternate conductors are terminated to a first external termination and adjacent conductors are terminated to a second external termination. Each capacitor is mounted on the substrate with the first termination in electrical contact with the first trace and the second termination in electrical contact with the second trace. A housing with the substrate is received in the housing. A first lead tab is in electrical contact with the first termination wherein the first lead tab extends from the housing.Type: GrantFiled: April 23, 2013Date of Patent: May 5, 2015Assignee: Kemet Electronics CorporationInventors: John Bultitude, John E. McConnell, Abhijit Gurav
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Patent number: 8898894Abstract: A welding system component includes a circuit board for the welding system component. An interface has a main riser portion with a fastener passageway formed therethrough. The interface has an extension portion with a terminal passageway formed therethrough. The extension portion is electrically connected to the circuit board with a terminal disposed in the terminal passageway. The extension portion is spaced away from a surface of the circuit board. A capacitor is electrically connected to the main riser portion with a fastener disposed in the fastener passageway.Type: GrantFiled: March 7, 2013Date of Patent: December 2, 2014Assignee: Lincoln Global, Inc.Inventors: George Koprivnak, Robert Dodge, Jeremie Buday, David Perrin
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Patent number: 8873219Abstract: A method of forming a stacked electronic component, and an electronic component formed by the method wherein the method includes: providing a multiplicity of electronic components wherein each electronic component comprises a first external termination and a second external termination; providing a first lead frame plate and a second lead frame plate wherein the first lead frame plate and the second lead frame plate comprises barbs and leads; providing a molded case comprising a cavity and a bottom; and forming a sandwich of electronic components in an array between the first lead frame plate and the second lead frame plate with the barbs protruding towards the electronic components and the leads extending through the bottom.Type: GrantFiled: June 26, 2012Date of Patent: October 28, 2014Assignee: Kemet Electronics CorporationInventors: Maurice Perea, Allen Hill, Reggie Phillips
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Patent number: 8836138Abstract: A wiring substrate includes: a substrate body made of an inorganic material; a first electrode portion, having a flat-plate shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a flat-plate shape, which penetrates through the substrate body in the thickness direction and faces the first electrode portion at a prescribed interval; and a first signal electrode, which is provided between the first electrode portion and the second electrode portion and penetrates through the substrate body in the thickness direction, wherein one of the first electrode portion and the second electrode portion is a ground electrode and the other is a power electrode.Type: GrantFiled: August 23, 2012Date of Patent: September 16, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventor: Tomoharu Fujii
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Patent number: 8837111Abstract: A capacitor forming unit according to one embodiment includes a dielectric plate with a plurality of through holes; a first conductor film formed on an upper surface of the dielectric plate; a first insulator film formed on the front end portion of the upper surface of the dielectric plate; a second conductor film formed on a lower surface of the dielectric plate; a second insulator film formed on the rear end portion of the lower surface of the dielectric plate; first electrode rods disposed in some of the through holes; and second electrode rods disposed in the remaining through holes where the first electrode rods are not disposed. The first electrodes are electrically connected to the first conductor film and electrically insulated from the second conductor film. The second electrode rods are electrically connected to the second conductor film and are electrically insulated from the first conductor film.Type: GrantFiled: March 16, 2012Date of Patent: September 16, 2014Assignee: Taiyo Yuden Co., Ltd.Inventors: Yoshinari Take, Hidetoshi Masuda, Kenichi Ota
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Patent number: 8830655Abstract: A capacitor (20A-E) formed as a roll of inner and outer electrode strips (21, 23) alternating with inner and outer dielectric strips (22, 24). Each of the dielectric strips (22, 24) is shorter than an inwardly adjacent one of the electrode strips (21, 23) at a radially outer end thereof (21 E, 23E). This exposes the radially outer end of each electrode strip on respectively different portions of an outer side surface (26, 28) of the capacitor. The exposed ends of the electrode strips may be arranged on opposite sides of the capacitor, such that stacking the capacitors interconnects them either in parallel, in series, or in combinations thereof in different embodiments.Type: GrantFiled: March 19, 2012Date of Patent: September 9, 2014Assignee: Trench LimitedInventors: Paolo Diamanti, Lorin Bratu, Ross McTaggart, Jorge Ribeiro, Keith Lobban
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Patent number: 8760847Abstract: A low-inductance capacitor assembly (12) is provided. The capacitor assembly (12) includes a positive terminal plate (16), a negative terminal plate (18) and an array (20) of capacitors (22) disposed between and electrically coupled to the positive terminal plate (16) and the negative terminal plate (18). A passage (30) extends through the positive terminal plate (16), the negative terminal plate (18) and through a void (35) formed within the array (20) of capacitors (22). The passage (30) may allow routing of a conductor (14) through the capacitor assembly (12).Type: GrantFiled: November 30, 2010Date of Patent: June 24, 2014Assignee: Pratt & Whitney Canada Corp.Inventors: Kevin Allan Dooley, Joshua Bell
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Patent number: 8760848Abstract: A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.Type: GrantFiled: December 9, 2011Date of Patent: June 24, 2014Assignee: Kemet Electronics CorporationInventors: John D. Prymak, Peter Par Blais, George Haddox, Michael Prevallet, Jim Piller, Chris Stolarski, Chris Wayne
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Patent number: 8760844Abstract: A structural capacitor includes a first carbon fiber material layer, a second carbon fiber material layer, and an interlayer dielectric including a diamond-like-carbon material layer.Type: GrantFiled: August 10, 2011Date of Patent: June 24, 2014Assignee: Mesoscribe Technologies, Inc.Inventors: William G. Baron, Jeffrey A. Brogan, Sandra Fries-Carr, Richard J. Gambino, Christopher Gouldstone, Brian Keyes, Sanjay Sampath, Huey-Daw Wu, Richard L. C. Wu
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Patent number: 8693162Abstract: A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.Type: GrantFiled: May 9, 2012Date of Patent: April 8, 2014Assignee: BlackBerry LimitedInventors: Mircea Capanu, Andrew Cervin-Lawry, Marina Zelner
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Patent number: 8488299Abstract: The disclosure provides a capacitor structure. A first dielectric layer is disposed over the first electrode layer. A second electrode layer is disposed over the first dielectric layer. At least one of the first electrode layer and the second electrode layer has a peak-valley like structure to create at least two different gap distances therebetween, thereby providing parallel combinations of at least two different capacitances.Type: GrantFiled: July 22, 2010Date of Patent: July 16, 2013Assignee: Industrial Technology Research InstituteInventors: Shih-Hsien Wu, Min-Lin Lee, Shinn-Juh Lai, Shur-Fen Liu, Meng-Hua Chen, Chin-Hsien Hung
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Patent number: 8355240Abstract: A multilayer capacitor operable to allow adjustment of its equivalent series resistance substantially independent of its equivalent series inductance is disclosed. The multilayer capacitor can be used in decoupling circuits such as power supply decoupling circuits. The equivalent series resistance of the multilayer capacitor can be increased while suppressing an increase in the equivalent series inductance resulting in improved noise grounding.Type: GrantFiled: July 24, 2009Date of Patent: January 15, 2013Assignee: KYOCERA CorporationInventor: Hisashi Satou
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Publication number: 20130003334Abstract: A chip component is provided with a block including a dielectric, input and output terminals, which are the first and second terminals that are provided on the surface of the block, an adjustment terminal that is a third terminal that includes an internal electrode extended into the block and that is provided on the surface of the block, and at least two inter-terminal circuits that are provided in the block and that are connected between at least two sets of two terminals of the first, second, and third terminals.Type: ApplicationFiled: June 5, 2012Publication date: January 3, 2013Applicant: Sony Mobile Communications Japan, Inc.Inventor: Kotaro Fujimori
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Patent number: 8339767Abstract: A power capacitor is described herein. The power capacitor includes a housing and at least one capacitor winding. The power capacitor also includes at least one mechanical spring element between the housing and the at least one capacitor winding.Type: GrantFiled: April 13, 2006Date of Patent: December 25, 2012Assignee: EPCOS AGInventors: Wilhelm Grimm, Wilhelm Hübscher, Harald Vetter
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Publication number: 20120319800Abstract: An electronic component includes a capacitor having a desired capacitance value and a laminate including a plurality of laminated insulating material layers. Land electrodes are provided on a bottom surface of the laminate. Internal conductors face the land electrodes, respectively, across the insulating material layer within the laminate, have areas larger than those of the land electrodes, respectively, and contain the land electrodes, respectively, when seen in a planar view from a z-axis direction. A capacitor conductor is provided on the positive direction side of the capacitor conductors in the z-axis direction and faces the capacitor conductors.Type: ApplicationFiled: August 23, 2012Publication date: December 20, 2012Applicant: Murata Manufacturing Co., Ltd.Inventors: Hiroyuki SASAKI, Ikuo TAMARU
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Patent number: 8274779Abstract: Provided are an embedded capacitor, an embedded capacitor sheet using the embedded capacitor, and a method of manufacturing the same that may increase a surface area to thereby increase a capacity for each unit area and may provide an embedded capacitor in a sheet to thereby readily lay the embedded capacitor on an embedded printed circuit board. The embedded capacitor may include: a common electrode member 11 including a plurality of grooves 11a; a sealing dielectric layer 12 being formed by sealing a nano dielectric powder with a high dielectric constant in the plurality of grooves 11a formed in the common electrode member 11; a buffer dielectric layer 13 sealing and smoothing an uneven portion of the sealing dielectric layer 12 by applying a paste or a slurry including epoxy of 20 Vol % through 80 Vol % and dielectric powder of 20 Vol % through 80 Vol % with respect to the sealing dielectric layer 12; and an individual electrode member 14 being formed on the buffer dielectric layer 13.Type: GrantFiled: May 18, 2009Date of Patent: September 25, 2012Assignee: Samhwa Capacitor Co., Ltd.Inventors: Jung Rag Yoon, Kyung Min Lee, Jeong Woo Han
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Patent number: 8254607Abstract: A hearing aid is provided. The hearing aid has a one- or multi-part carrying hook. The one- or multi-part carrying hook has a tip for connection to a sound tube, the tip being connected integrally to a damper extending across the internal cross-section of the tip, the damper preferably being designed as a membrane.Type: GrantFiled: February 5, 2009Date of Patent: August 28, 2012Assignee: Siemens Medical Instruments Pte. Ltd.Inventors: Hartmut Ritter, Tom Weidner
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Patent number: 8199458Abstract: Provided is a surface mounting type high voltage ceramic capacitor with an array structure that may form a plurality of capacitors in an array structure to thereby simultaneously mount the plurality of capacitors on a printed circuit board, and thus may reduce a work procedure and enhance a work productivity. The surface mounting type high voltage ceramic capacitor with an array structure, may include: a ceramic member 11; a common electrode member 12 being formed on one surface of the ceramic member 11; a plurality of individual electrode members 13 being arranged on another surface of the ceramic member 11; a common lead terminal 14 being connected to the common electrode member 12; a plurality of individual lead terminals 15 being connected to the plurality of individual electrode members 13, respectively, to face the common lead terminal 14; and a molding member 16 sealing the ceramic member 11, the common electrode member 12, and the plurality of individual electrode members 13.Type: GrantFiled: April 8, 2009Date of Patent: June 12, 2012Inventor: Young Joo Oh
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Patent number: 8194387Abstract: A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.Type: GrantFiled: March 20, 2009Date of Patent: June 5, 2012Assignee: Paratek Microwave, Inc.Inventors: Mircea Capanu, Andrew Cervin-Lawry, Marina Zelner
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Publication number: 20120134069Abstract: A low-inductance capacitor assembly (12) is provided. The capacitor assembly (12) includes a positive terminal plate (16), a negative terminal plate (18) and an array (20) of capacitors (22) disposed between and electrically coupled to the positive terminal plate (16) and the negative terminal plate (18). A passage (30) extends through the positive terminal plate (16), the negative terminal plate (18) and through a void (35) formed within the array (20) of capacitors (22). The passage (30) may allow routing of a conductor (14) through the capacitor assembly (12).Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: PRATT & WHITNEY CANADA CORP.Inventors: Kevin Allan Dooley, Joshua Bell
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Publication number: 20120106026Abstract: A electrical storage device has: a cell module including a plurality of cells arranged juxtaposed and each having a pair of current collector terminals protruding from electrodes, the current collector terminals of adjacent ones of the cells being connected to each other; and an electronic circuit board disposed near the cell module and electrically connected to the current collector terminals of each of the cells via a plurality of connecting wires, for controlling charging and discharging of each of the cells. A cable having flexibility or a flexible wire is used as each of the connecting wires. One end of each of the connecting wires has a connecting terminal portion for clamping the current collector terminals of the adjacent ones of the cells to each other.Type: ApplicationFiled: March 1, 2011Publication date: May 3, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Toshihiko HIGASHINO, Fumito UEMURA, Nobuhiro KIHARA, Yuichi MURAMOTO, Takayuki UBUKATA
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Patent number: 8145919Abstract: A power supply module removably disposed within an automated data storage and retrieval system. An automated data storage and retrieval system which includes one or more power supply modules removably disposed therein. An accessor movably disposed with an automated data storage and retrieval system comprising a gripper mechanism which can be releasably attached to a power supply module. A method to supply power to an automated data storage and retrieval system. A method to monitor the operation of a power supply module removably disposed within an automated data storage and retrieval system.Type: GrantFiled: August 21, 2008Date of Patent: March 27, 2012Assignee: International Business Machines CorporationInventors: Robert G. Emberty, Craig Anthony Klein
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Patent number: 8125766Abstract: A capacitor assembly with a substrate having a first face and a second face. A multiplicity of capacitors are mounted on the first face wherein each capacitor has a first lead and a second lead of opposite polarity to the first lead. A bridge is in electrical contact with multiple first leads. A tree is in electrical contact with the bridge wherein the tree passes through a via of the substrate and is in electrical contact with a first trace of the second face. A second trace is on the second face wherein the second lead is in electrical contact with the second trace.Type: GrantFiled: June 13, 2008Date of Patent: February 28, 2012Assignee: Kemet Electronics CorporationInventors: John D. Prymak, Peter Blais, George Haddox, Michael Prevallet, Jim Piller, Chris Stolarski, Chris Wayne
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Patent number: 8116064Abstract: An element body has a major capacitance forming portion to form a first capacitance, and a minor capacitance forming portion to form a plurality of second capacitances smaller than the first capacitance. The major capacitance forming portion includes a first internal electrode connected to a first terminal electrode, and a second internal electrode opposed to the first internal electrode and connected to a second terminal electrode.Type: GrantFiled: April 24, 2009Date of Patent: February 14, 2012Assignee: TDK CorporationInventors: Masaaki Togashi, Hiroshi Okuyama, Yutaro Kotani
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Patent number: 8064188Abstract: At least an embodiment of the present technology provides a capacitor, comprising a substrate, a first solid electrode disposed on the substrate, a second electrode broken into subsections, the subsections connected by a bus line and separated from the first electric by a dielectric medium. The second electrode broken into subsections may have a lower resistance than the first solid electrode and by changing the width and length of the sides of the subsections, the resistance of the first electrode is modifiable.Type: GrantFiled: November 20, 2006Date of Patent: November 22, 2011Assignee: Paratek Microwave, Inc.Inventors: James Oakes, James Martin
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Patent number: 8050045Abstract: The invention relates to a surface mount type electronic component mounted on a printed circuit board or hybrid IC (HIC) and a method of manufacturing the same and provides an electronic component which can be formed with a small size and a low height at a low cost and a method of manufacturing the same. A common mode choke coil as the electronic component has an overall shape in the form of rectangular parallelepiped that is provided by forming an insulation layer, a coil layer (not shown) formed with a coil conductor, and external electrodes electrically connected to the coil conductor in the order listed on a silicon substrate using thin film forming techniques. The external electrodes are formed to spread on a top surface (mounting surface) of the insulation layer.Type: GrantFiled: August 7, 2006Date of Patent: November 1, 2011Assignee: TDK CorporationInventors: Nobuyuki Okuzawa, Makoto Yoshida
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Patent number: 8018712Abstract: A bus-bar for assembling a capacitor device is disclosed, which is capable of improving the environment of a soldering operation for the bus-bar being soldered to a capacitor device, reducing the inferior rate of the capacitor device while improving the quality of the capacitor device, and reducing the weight of the capacitor module, in soldering the bus-bar to capacitor devices. The lead frame attached to polar plates by soldering is formed thinner than the other parts of the bus-bar, and opening parts having an oval or polygonal shape are formed on a surface of the bus-bar so that two adjoining capacitor devices can be exposed. The lead frame is formed in the opening in order for soldering with the polar plates of the capacitor device.Type: GrantFiled: September 26, 2008Date of Patent: September 13, 2011Assignee: Nuintek Co., Ltd.Inventors: Chang Hoon Yang, Dae Jin Park, Yong Won Jun
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Patent number: 8004063Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.Type: GrantFiled: November 16, 2006Date of Patent: August 23, 2011Assignee: Vishay Intertechnology, Inc.Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
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Publication number: 20110149472Abstract: There is provided a method of connecting busbars for a capacitor and a product manufactured by the same method, whereby the inductance of the capacitor is decreased and thus the amount of heat generated in the capacitor is decreased to improve the temperature characteristics and electrical characteristics of the capacitor and the reliability of the quality of the capacitor, to consistently improve the insulation between the busbars having different polarity, and to maintain the insulation between the busbars in severe environments. The method of connecting busbars for a capacitor is characterized by coating at least parts of an N-pole busbar and a P-pole busbar, each of which has different polarity, with an insulating material; exposing parts of the N-pole and P-pole busbars outside an outer case so as to form a terminal to be connected to an other component; and connecting the N-pole busbar to the P-pole busbar in a manner that at least parts of the N-pole and P-pole is busbars overlap each other.Type: ApplicationFiled: December 21, 2009Publication date: June 23, 2011Applicant: NUINTEK CO., LTD.Inventors: Chang-Hoon YANG, Dae-Jin Park, Yong-Won Jun
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Patent number: 7932471Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.Type: GrantFiled: August 4, 2006Date of Patent: April 26, 2011Assignee: NGK Spark Plug Co., Ltd.Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Kazuhiro Hayashi, Jun Otsuka, Manabu Sato
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Publication number: 20110069425Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.Type: ApplicationFiled: September 24, 2009Publication date: March 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis L. Hsu, Xu Ouyang, Chih-Chao Yang
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Publication number: 20110032659Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.Type: ApplicationFiled: August 5, 2009Publication date: February 10, 2011Applicant: International Business Machines CorporationInventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
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Publication number: 20100207710Abstract: An electrical circuit arrangement provides a substrate and at least two conductive surfaces. The substrate comprises at least one layer disposed between the conductive surfaces. The conductive surfaces form a capacitor and overlap in part and form an overlapping area. In the event of a displacement of the conductive surfaces relative to one another, the resulting overlapping area is largely constant up to a threshold value of the displacement.Type: ApplicationFiled: October 9, 2008Publication date: August 19, 2010Applicant: Rohde & Schwarz GmbH & Co. KGInventor: Robert Ziegler
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Patent number: 7763925Abstract: A semiconductor device incorporating a capacitor and a method of fabricating the same include a first inter-layer dielectric film formed on a semiconductor substrate, a first electrode pattern formed on the first inter-layer dielectric film, and a capacitor region self-aligned to the first electrode pattern and in which the first inter-layer dielectric film is etched. An MIM capacitor is conformably formed on the sidewall of the first electrode pattern in the capacitor region. In the capacitor region, a first hollow region is formed enclosed by the MIM capacitor and a second electrode pattern fills the first hollow region. The second electrode pattern has a sidewall opposite to the sidewall of the first electrode pattern. The MIM capacitor is conformably formed in the capacitor region that is deepened more than a thickness of an interconnection layer, so that it has a capacitor area wider than an area contacting with the interconnection layer.Type: GrantFiled: May 29, 2007Date of Patent: July 27, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Jun-Pyo Hong
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Publication number: 20100061036Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.Type: ApplicationFiled: November 10, 2009Publication date: March 11, 2010Inventors: Edward B. Harris, Canzhong He, Che Choi Leung, Bruce W. McNeill
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Patent number: 7623338Abstract: In a device including multiple metal-insulator-metal (MIM) capacitors and a method of fabricating the same, the multiple MIM capacitors comprise a lower interconnect in a substrate; a first dielectric layer on the lower interconnect; a first intermediate electrode pattern on the first dielectric layer overlapping with the lower interconnect; a second intermediate electrode pattern on the first dielectric layer and spaced apart from the first intermediate electrode pattern in a same plane of the device as the first intermediate electrode pattern; a second dielectric pattern on the second intermediate electrode pattern; and an upper electrode pattern on the second dielectric pattern.Type: GrantFiled: January 30, 2006Date of Patent: November 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Seok-jun Won
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Patent number: 7602600Abstract: A tantalum capacitor includes: sintered bodies which are disposed at intervals and respectively have first surfaces forming the same surface; and electrode rods which respectively extend into the tantalum sintered bodies and project from the first surfaces of the tantalum sintered bodies. The tantalum capacitor further includes: layers composed of an oxide film layer, a functional polymer layer or a manganese layer, and a carbon layer which are sequentially laminated on surfaces of each of the tantalum sintered bodies excluding the first surface; a conductive layer which covers outside surfaces of the tantalum sintered bodies excluding the first surfaces; and an electrode plate having openings respectively formed at positions corresponding to the first surfaces of the tantalum sintered bodies so that the electrode rods are exposed through the openings. The electrode plate is connected to the conductive layer and spreads across the first surfaces of the tantalum sintered bodies.Type: GrantFiled: November 25, 2008Date of Patent: October 13, 2009Assignee: Fujitsu LimitedInventor: Masayuki Itoh
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Patent number: 7602599Abstract: A method of making a metal-metal capacitor is disclosed, in which a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, and a third metal layer are formed in the order over a substrate; an upper capacitor is defined by etching using a first mask, wherein the stop of the etching can be controlled; a lower capacitor is defined by etching using a second mask; and an anti-reflective third mask is formed to cover the surface, and the capacitor border and metal interconnect conductive wire are defined, so as to make a metal-metal capacitor with a stable structure in a wide process window.Type: GrantFiled: July 9, 2008Date of Patent: October 13, 2009Assignee: United Microelectronics Corp.Inventor: Chien-En Hsu
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Patent number: 7599167Abstract: Circuit modules, systems and devices for controlling voltages across capacitors.Type: GrantFiled: March 16, 2006Date of Patent: October 6, 2009Assignee: Cooper Technologies CompanyInventor: Frank Anthony Doljack
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Patent number: 7599168Abstract: Provided are active balancing modules that control voltage imbalances between capacitors stacked in a series arrangement and methods for their manufacture. These modules are simple and inexpensive to manufacture, and versatile. They may be used alone or they may be combined together to form a multi-module active balancing circuitry for a plurality of capacitors stacked in a series arrangement. The modules may further be aligned in either a side-by-side topology or an overlapping topology.Type: GrantFiled: February 6, 2008Date of Patent: October 6, 2009Assignee: Cooper Technologies CompanyInventors: Frank Anthony Doljack, Neal Schultz, Hundi P. Kamath, Jim Strain
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Patent number: 7594318Abstract: A multilayer substrate assembly (80) includes at least one embedded component (52) within a plurality of stacked pre-processed substrates. Each pre-processed substrate can have a core dielectric (14), patterned conductive surfaces (12 and 16) on opposing sides of the core dielectric, and at least one hole (18) in each of at least two adjacently stacked pre-processed substrates such that at least two holes are substantially aligned on top of each other forming a single hole (19). The assembly further includes a processed adhesive layer (48) between top and bottom surfaces of respective pre-processed substrates. The embedded component is placed in the single hole and forms a gap (67 & 66) between the embedded component and a peripheral wall of the single hole. When the assembly is biased, the processed adhesive layer fills the gap to form the assembly having the embedded component cross-secting the plurality of pre-processed substrates.Type: GrantFiled: September 12, 2007Date of Patent: September 29, 2009Assignee: Motorola, Inc.Inventors: James A. Zollo, John K. Arledge, Nitin B. Desai
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Patent number: 7554789Abstract: A capacitor array comprising a plurality of unit capacitors, each having first and second electrode plates. The first electrode plates are commonly connected via first routings. The second electrode plates are grouped and connected to a plurality of nodes via second routings. The second routings connected to one node and another do not overlap in the capacitor array. The second electrode plates connected to the same node conglomerate as a group and no second electrode plate connected to another node is located in the group.Type: GrantFiled: June 29, 2006Date of Patent: June 30, 2009Assignee: Mediatek Inc.Inventor: Hung-I Chen
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Patent number: 7511940Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.Type: GrantFiled: August 15, 2007Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Natalie B. Feilchenfeld, Michael L. Gautsch, Zhong-Xiang He, Matthew D. Moon, Vidhya Ramachandran, Barbara Waterhouse
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Patent number: 7502218Abstract: A multi-terminal capacitor includes a first capacitor plate, a second capacitor plate in parallel with the first capacitor plate, and a third capacitor plate in parallel with the first and second capacitor plates. The first, second and third capacitor plates are separated from each other by dielectric material, such that the first, second and third capacitor plates function as a first, second and third terminals, respectively, for capacitors formed therebetween.Type: GrantFiled: November 9, 2005Date of Patent: March 10, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shun Cheng Yang
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Patent number: 7492569Abstract: A capacitor cell for reducing noise in a high drive cell includes a plurality of vias for supplying power to an interconnection layer positioned over the capacitor cell from an upper interconnection layer, so that the resistance of the power supply path is reduced.Type: GrantFiled: June 30, 2006Date of Patent: February 17, 2009Assignee: NEC Electronics CorporationInventors: Taro Sakurabayashi, Toshikazu Kato
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Patent number: 7483258Abstract: A metal-insulator-metal capacitor formed in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.Type: GrantFiled: December 13, 2005Date of Patent: January 27, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Hong Chen, Minghsing Tsai
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Patent number: RE44998Abstract: At least an embodiment of the present technology provides a capacitor, comprising a substrate, a first solid electrode disposed on the substrate, a second electrode broken into subsections, the subsections connected by a bus line and separated from the first electric by a dielectric medium. The second electrode broken into subsections may have a lower resistance than the first solid electrode and by changing the width and length of the sides of the subsections, the resistance of the first electrode is modifiable.Type: GrantFiled: March 9, 2012Date of Patent: July 8, 2014Assignee: BlackBerry LimitedInventors: James Oakes, James Martin