Impedance Insertion Patents (Class 361/58)
  • Patent number: 4967302
    Abstract: A single-channel shunt-diode safety barrier for energizing a 2-wire transmitter, particularly for use in process control, incorporates within the barrier a floating d.c. power supply or its equivalent to enable the barrier to deliver into an earthed load a direct current substantially equal to that which it draws from the transmitter. The floating d.c. power supply is preferably derived from an external d.c. power source via a transformer or diode-pump circuit within the barrier itself. The barrier is enabled to pass superimposed digital or frequency signals in both directions to and from the transmitter.
    Type: Grant
    Filed: May 31, 1988
    Date of Patent: October 30, 1990
    Assignee: Measurement Technology Limited
    Inventors: Ian C. Hutcheon, David J. Epton
  • Patent number: 4958254
    Abstract: A five pin protector module for telephone circuits comprises two input pins, two output pins and a grounding pin, all on an insulative base. The electrical current path between each input pin and its respective output pin comprises an electrically conductive arm, a current responsive assembly and an electrically conductive helical spring. The module contains a bidirectional voltage sensitive switch which prevents input voltage surges from reaching the output but, instead, conducts them to a grounding member to which the grounding pin is attached.
    Type: Grant
    Filed: March 31, 1989
    Date of Patent: September 18, 1990
    Assignee: GTE Products Corp.
    Inventors: Dan Kidd, John J. Napiorkowski, Bruce D. Atkinson
  • Patent number: 4949212
    Abstract: A circuit configuration for protecting an integrated circuit from damage by a voltage present at an output exceeding the supply voltage range of the integrated circuit includes a given number of parasitic circuit structures of the integrated circuit. Additional circuit structures combined with the parasitic circuit structures form a protective circuit. The circuit structures are activated by the voltage at the output to become operative for protection.
    Type: Grant
    Filed: February 15, 1989
    Date of Patent: August 14, 1990
    Assignee: Siemens Aktiengesellschaft
    Inventors: Michael Lenz, Frank-Lothar Schwertlein, Wolfgang Horchler
  • Patent number: 4945358
    Abstract: A short circuit protection arrangement (2) for a driver circuit (9, 16) including a diode (24) for sensing the presence of a short circuit condition at the driver circuit output; and an arrangement (18, 20, 22, 24) for sensing the discontinuance of the short circuit condition by establishing an inductive current at the output upon the occurrence of the short circuit condition and sensing the increase in voltage at the output due to the inductive current upon discontinuance of the short circuit condition. Such a protection arrangement may be used for each of a plurality of driver circuits (40, 50, 60, 70, 80) utilizing a common inductance (36, 38).
    Type: Grant
    Filed: May 30, 1989
    Date of Patent: July 31, 1990
    Assignee: Motorola, Inc.
    Inventor: Stanley Wrzesinski
  • Patent number: 4943887
    Abstract: An asymmetrical overvoltage protection circuit includes a series connection of varistors with a capacitance in parallel with only one of the varistors. The asymmetry may also involve a parallel connection of an inductance with the other of the varistors.
    Type: Grant
    Filed: May 20, 1988
    Date of Patent: July 24, 1990
    Assignee: Smit Transformation B.V.
    Inventor: Ajit K. Bose
  • Patent number: 4939616
    Abstract: The described embodiments of the present invention provide an input protection device with a low trigger threshold. The structure is a silicon controlled rectifier (SCR) type of device wherein the triggering mechanism is avalanche conduction at the interface between the N-well surrounding a portion of the protection device and the P-type substrate. The embodiments provide a lowered threshold voltage by providing a highly doped region of the same conductivity type as the well at the interface between the well and the substrate. This highly doped region is connected to a resistor which is then connected to the protected node. The resistor and heavily doped region at the intersection between the N-well and substrate provides an additional source of current for avalanching at a lower voltage. Thus the trigger voltage of the protection system is substantially lowered.
    Type: Grant
    Filed: November 13, 1989
    Date of Patent: July 3, 1990
    Assignee: Texas Instruments Incorporated
    Inventor: Robert N. Rountree
  • Patent number: 4937471
    Abstract: A bidirectional input-output cell characterized in a logic means has MOS transistors of which semiconductor region approaches through whole side of outer drain region in the opposite position of channel and is the opposite type conductivity of said drain region conductivity. The bidirectional input-output cell can prevent the breakdown of semiconductor device come out the surge current of electrostatic discharge voltage in said semiconductor region.
    Type: Grant
    Filed: November 29, 1988
    Date of Patent: June 26, 1990
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Haksong Park, Kwanyong Sung, Heonjoon Kim, Chaimin Lee
  • Patent number: 4937696
    Abstract: A protection circuit for a semiconductor device is disclosed. This circuit is connected in series with a power semiconductor device to be protected, and is comprised of a circuit breaker and current-limiting device. The current-limiting device limits the overcurrent, thereby providing a time allowance until the circuit breaker begins operate.
    Type: Grant
    Filed: May 11, 1989
    Date of Patent: June 26, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Yoshino, Noburu Fukushima, Masakatsu Haga, Masachika Iida, Sadaaki Mori
  • Patent number: 4930035
    Abstract: A radio frequency limiter having a radio frequency power divider having an input and a plurality of outputs; at least one diode connected in shunt with each one of the outputs of the power divider; and, a power combiner having an output and a plurality of inputs, each one of such inputs being connected to a corresponding one of the outputs of the power divider. With such arrangement, the insertion loss of such limiter is reduced compared to a limiter having a like number of diodes connected in shunt at a common point of a single transmission line. Therefore, the reduced insertion loss means that the impedance matching circuit required will not limit the maximum operating frequency to the degree an impedance matching circuit of similar complexity will limit the maximum operating frequency required for a limiter having the same number of diodes but using a single transmission line.
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: May 29, 1990
    Assignee: Raytheon Company
    Inventors: Luis M. Viana, Robert A. Cuozzo, Michael L. Miceli, Kent A. Whitney
  • Patent number: 4930037
    Abstract: A static electricity protection system for use with a voltage sensitive MOS component having a gate input including a layer of oxide. A transmission gate having a source and a drain as an input and output, respectively, is connected to the MOS component gate input for protecting it from sudden electrical voltage surge discharges. The transmission gate source and drain include a layer of oxide substantially thicker than the oxide layer of the MOS component gate input.
    Type: Grant
    Filed: February 16, 1989
    Date of Patent: May 29, 1990
    Assignee: Advaced Micro Devices, Inc.
    Inventor: Ann K. Woo
  • Patent number: 4930036
    Abstract: A terminal of an integrated circuit is protected from electrostatic discharge voltages at the terminal by a protection circuit which includes a bidirectionally conductive transistor as a discharge current shunting device. A bidirectionally conductive controlled path is provided between the terminal and one of two voltage supply terminals. The transistor has a biassing resistor connected between the terminal and its control electrode. A normally reverse biassed diode is connected between the control electrode on another of the voltage supply terminals. For an n-channel FET or an npn bipolar transistor, when a positive electrostatic discharge is applied to the terminal, a current flowing through the biassing resistor turns on the transistor to provide a discharge path from the terminal to the voltage supply terminal.
    Type: Grant
    Filed: July 13, 1989
    Date of Patent: May 29, 1990
    Assignee: Northern Telecom Limited
    Inventor: John E. Sitch
  • Patent number: 4928199
    Abstract: A circuit protection device for protecting electrical circuits against voltage transients comprises a chip package which includes a threshold switch device formed from an amorphous composition.
    Type: Grant
    Filed: September 11, 1989
    Date of Patent: May 22, 1990
    Assignee: Raychem Limited
    Inventors: Stephen H. Diaz, Gabe Cherian, Stephen Morris, John R. Vinson, David Crofts, Anthony J. Moore
  • Patent number: 4924340
    Abstract: A circuit protection device for protecting an electrical circuit from a voltage transient, e.g. a voltage transient caused by an electrostatic discharge, lightning or a nuclear electromagnetic pulse, comprises a threshold switching element formed from an amorphous composition comprising arsenic, sulphur, and optionally germanium, and a pair of electrodes in contact with the composition. The devices generally exhibit a good balance of physical properties including switching speed, energy required to latch them in their low resistance state, high resistance state (off) resistance, threshold voltage and capacitance, which enables them to be used successfully to protect electrical circuits from such transients.
    Type: Grant
    Filed: August 31, 1988
    Date of Patent: May 8, 1990
    Assignee: Raychem Limited
    Inventor: Martin Sweet
  • Patent number: 4924342
    Abstract: A polyphase AC current limiting circuit, which incorporates improvements in control methods and circuitry that operate to avoid high rates of current change which occur upon initiation of a branch load fault and when the branch load fault is suddenly cleared. This "soft" start and "soft" load-off characteristic, reduces the voltage transients imposed on the AC power source and bus to relative insignificance compared with the voltage transients imposed by prior art current limiting circuits. The invention AC current limiting circuit comprises a high impedance circuit connected in parallel with a low impedance circuit, a load-off circuit connected in shunt with the device output power lines, and a control means for controlling the switching devices.
    Type: Grant
    Filed: August 3, 1988
    Date of Patent: May 8, 1990
    Assignee: Teledyne Inet
    Inventor: Robert H. Lee
  • Patent number: 4924339
    Abstract: A bipolar transistor for clamping an excess input potential is provided near an input pad. A signal from the input pad is supplied through a wire to the gate of a MOS transistor in the input stage. A diode is provided near the gate of the MOS transistor. The diode absorbs a potential oscillation generated in the wire near the gate of the transistor, which is due to action of an inductance involved in the wire.
    Type: Grant
    Filed: December 28, 1988
    Date of Patent: May 8, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Atsumi, Toru Yoshida, Yasuo Kawahara, Fuminari Tanaka
  • Patent number: 4922367
    Abstract: A CMOS circuit including a variable conductor means interposed between a power supply and the CMOS circuit. The CMOS circuit comprises a P channel MOS FET and an N channel MOS FET laterally formed on the surface of a semiconductor substrate, inherently producing a parasitic thyristor which can be latched-up with destructive consequences under certain circumstances. The variable conductor means, interposed between the power supply and CMOS circuit, preferably includes a superconductor arranged to sharply switch to a normal conductor mode when the current level exceeds a critical current level, established to be less than the latch-up holding current of the parasitic thyristor, thereby to prevent latch-up.
    Type: Grant
    Filed: March 9, 1988
    Date of Patent: May 1, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hideto Hidaka
  • Patent number: 4922365
    Abstract: Disclosed is an overvoltage suppressing circuit for a semiconductor device connected between the poles of a DC power source and adapted to effect a switching operation. The circuit comprises: a serial circuit connected in parallel with a semiconductor device and including an overvoltage suppressing capacitor, an oscillation suppressing diode, and an impedance regulator connected in series each other, the impedance regulator being operable to change into a state of high impedance for suppressing a reverse current flowing into the oscillation suppressing diode when the oscillation suppressing diode is turned off; and a discharging device connected between a DC power source and the overvoltage suppressing capacitor for discharging to the DC power source a charge accumulated in the overvoltage suppressing capacitor when the oscillation suppressing diode is off.
    Type: Grant
    Filed: April 13, 1989
    Date of Patent: May 1, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Haruyoshi Mori
  • Patent number: 4910626
    Abstract: A current limiter comprising a cryostat provided with a first insulating feedthrough for an inlet conductor and a second insulating feedthrough for an outlet conductor, and a conductor running from one feedthrough to the other inside the tank, said conductor being constituted at least in part by a superconducting material, the cryostat being filled with a fluid at a temperature which is low enough to maintain said material in the superconducting state, said portion made of superconducting material including at least one portion comprising superconducting wires (7, 8) wound in opposite direction windings on two coaxial insulating formers (14, 15). Respective the ends of each of the superconducting wires (7, 8) are connected firstly to the inlet conductor and secondly to the outlet conductor via identical elementary current feeds (21A, 22A).
    Type: Grant
    Filed: March 30, 1989
    Date of Patent: March 20, 1990
    Assignee: Societe Anonyme dite : Alsthom
    Inventors: Michel Collet, Van Doan Pham, Alain Fevrier
  • Patent number: 4907020
    Abstract: A driving circuit for an ink jet recording head that includes electrothermal converting elements for causing liquid emission by thermal energy. Electric energy is supplied to the electrothermal converting elements for actuation. Resistor elements are respectively and electrically connected parallel to the electrothermal converting elements for the purpose of reducing the influence of the capacitative component of the electrothermal converting elements to a negligible level, thereby suppressing electric current through the ink.
    Type: Grant
    Filed: March 21, 1988
    Date of Patent: March 6, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventor: Atsushi Shiozaki
  • Patent number: 4907118
    Abstract: An inexpensive, compact, portable, visual indicator electrical plug-type surge protector which comprises an electrical plug body composed of a molded transparent polymer, the plug body having an extended male grounding prong and a pair of male electrical prongs on one face and a female receiving grounding inlet and a pair of female receiving inlets on the opposite face. The plug body contains in a visually indicating position, generally slightly below the surface of the plug body, a metal oxide varistor electrically connected to the electrical outlet plug so as to prevent electrical surges from passing through the surge protector from the electrical source into which the electrical plug-type surge protector is plugged and to be activated and to change color on the occurrence of an electrical surge so that the user of the surge protector will know when the electrical surge has been received and thereby be able to replace the surge protector with a new surge protector.
    Type: Grant
    Filed: March 9, 1989
    Date of Patent: March 6, 1990
    Assignee: Curtis Manufacturing Company, Inc.
    Inventor: Edward L. Hames
  • Patent number: 4897756
    Abstract: An add on ground fault detection system including a module readily connected to the distribution line and to the associated circuit breaker, and including circuit means for sensing a metering signal while providing a low resistance burden to summing transformers, and providing a relay tripping signal if the metering signal is above a selected level.
    Type: Grant
    Filed: February 22, 1989
    Date of Patent: January 30, 1990
    Assignee: Square D Company
    Inventor: Henry J. Zylstra
  • Patent number: 4890182
    Abstract: A circuit protection device for protecting an electrical circuit from a voltage transient, e.g. a voltage transient caused by an electrostatic discharge, lightning or a nuclear electromagnetic pulse, comprises a threshold switching element formed from an amorphous composition comprising germanium, selenium and optionally antimony, and a pair of electrodes in contact with the composition. The devices generally exhibit a good balance of physical properties including switching speed, energy required to latch them in their low resistance state, high resistance state (off) resistance, threshold voltage and capacitance, which enables them to be used successfully to protect electrical circuits from such transients.
    Type: Grant
    Filed: August 31, 1988
    Date of Patent: December 26, 1989
    Assignee: Raychem Limited
    Inventor: Martin Sweet
  • Patent number: 4890186
    Abstract: In the past, a power fuse need be replaced after the current limiting operation and cannot be repeatedly used. To solve this problem, there has been proposed a permanent fuse or the like which uses an alkaline metal having a low melting point such as Hg, K, Na, etc.These are harmful to human body, and since they are completely vaporized, an insulated layer of a vessel cannot be removed, thus giving rise to a difficulty toward higher voltage.The present invention makes best use of characteristic of carbon which sublimates. A plurality of boundary layers of carbon lumps are disposed in series or in series and parallel, and electrode potential drops at the time of large current and potential drops of arc column under high atmosphere presssure which produces for a short period of time are utilized to effect current limiting.
    Type: Grant
    Filed: February 14, 1989
    Date of Patent: December 26, 1989
    Assignee: Kabushiki Kaisha Yaskawa Denki Seisakusho
    Inventors: Chiaki Matsubara, Hirokuni Ishikawa, Masao Ojima
  • Patent number: 4890181
    Abstract: A short-circuit protective device for a motor-driven and generator-driven electrical machine fed by a pulse-controlled a.c. converter has reverse-parallel circuitry that is switching dependent on a monitoring device. The monitoring device detects short circuits and is provided in a d.c. current supply line. Using the reverse-parallel circuitry and the monitor, an intermediate circuit capacitor of the pulse-controlled a.c. converter feeding the machine is isolated from the short circuit location.
    Type: Grant
    Filed: March 8, 1989
    Date of Patent: December 26, 1989
    Assignee: Siemens Aktiengesellschaft
    Inventors: Georg Nerowski, Bernhard Piepenbreier, Hans-Juergen Toelle
  • Patent number: 4884163
    Abstract: Conductive polymer compositions, particularly PTC compositions, which contain alumina trihydrate, or another arc-controlling agent, and a lubricant or coupling agent. Advantages which can result from use of the lubricant or coupling agent include improved PTC behavior and improved adhesion to metal conductors, in particular metal foils and solid metal wires.
    Type: Grant
    Filed: April 5, 1988
    Date of Patent: November 28, 1989
    Assignee: Raychem Corporation
    Inventors: Marguerite E. Deep, Nelson H. Thein
  • Patent number: 4879622
    Abstract: The circuit monitors the superconducting state of a superconducting magnet winding. The winding is subdivided into two serially connected sub-windings with an intermediate tap point. The end of the sub-windings are connected via an electrically conducting parallel branch. This parallel branch consists of two serially connected sub-branches, each containing at least one ohmic resistor. There is a junction between the sub-branches. This junction and the tap point of the magnet winding are the diagonal points of a bridge circuit, to which is connected an electronic device for evaluating and processing the voltage signal to be measured. To account for the ohmic resistances associated with the sub-windings of the superconducting magnet winding and thereby increasing the sensitivity of the circuit, each sub-branch of parallel branch contains at least one capacitor.
    Type: Grant
    Filed: May 20, 1987
    Date of Patent: November 7, 1989
    Assignee: Siemens Aktiengesellschaft
    Inventor: Lutz Intichar
  • Patent number: 4876621
    Abstract: A line protector for a communications circuit. The line protector has an overvoltage arrestor such as a three electrode gas tube, two of whose electrodes are connected to the line input terminals of the protector by associated conductive elements projecting from the protector base. The third electrode is connected to the ground terminal. The line protector also has two positive temperature coefficient resistors (PTCRs) which protect against marginal overcurrents. Conductive elements connected to the line protector's equipment terminals also project from the base in the same direction as the line input terminal conductive elements project. Each PTCR is in contact with an associated one of the two line input terminal conductive elements and an associated one of the two equipment terminal conductive elements.
    Type: Grant
    Filed: December 8, 1988
    Date of Patent: October 24, 1989
    Assignee: Reliance Comm/Tec Corporation
    Inventors: Wayne Rust, Alexander G. Gilberts
  • Patent number: 4873604
    Abstract: A shunt device and a method are described for protecting electrical equipment when a fuse blows. The shunt device establishes a by-pass across the fuse for permitting a limited amount of current to begin to flow at a lower voltage than the fuse blowing voltage and before the fuse blows, thereby serving as a transitory relief valve for a portion of the current while minimizing or even substantially eliminating the inductive spike when the fuse blows. The shunt device is made of at least one pyrolyzed polyacrylonitrile (PPP) fiber having a selected switching voltage so that the PPP fiber switches to a low resistance state while the fuse is blowing. When the fuse and PPP characteristics are properly matched, the rate of change of the current with time is lowered, thus selectively decreasing the size of the voltage transients which occur after the fuse blows.
    Type: Grant
    Filed: July 1, 1985
    Date of Patent: October 10, 1989
    Assignee: Hoechst Celanese Corp.
    Inventors: Harris A. Goldberg, Clyde C. Williams
  • Patent number: 4870534
    Abstract: A surge suppressor for repeatedly protecting a load against surges occurring on A-C power mains from lightning surges or the like comprises a first series circuit having a first inductance and a first alternating voltage limiter, including at least a first capacitance and a bidirectionally conductive rectifier circuit, coupled between first and second input terminals. The first inductance conducts substantially all of the current supplied from the A-C power mains. A second series circuit comprising a second inductance and second alternating voltage limiter, including at least a second capacitance and a second bidirectionally conductive rectifier circuit, is coupled across the first alternating voltage limiter and is coupled to first and second output terminals.
    Type: Grant
    Filed: September 2, 1988
    Date of Patent: September 26, 1989
    Inventor: Jack R. Harford
  • Patent number: 4868903
    Abstract: A circuit for supplying safe logic zero and logic one signals to hardwired inputs of CMOS ICs comprises, at most, three field effect transistors, none of which have gates connected to either drain voltage V.sub.dd or source voltage V.sub.ss. The circuit has no external inputs and has two outputs, logic zero and logic one. The circuit has only one stable operating point and moves to this operating point from any initial condition. The circuit is safe and can enhance the reliability of ICs as it provides the same noise protection from voltages V.sub.ss and V.sub.dd for nodes connected to its output that an inverter provides for nodes connected to its output.
    Type: Grant
    Filed: April 15, 1988
    Date of Patent: September 19, 1989
    Assignee: General Electric Company
    Inventor: Peter F. Corbett
  • Patent number: 4868703
    Abstract: A solid state switching device allows independent control of the latching and holding currents, and has particular application to telephone systems. The holding current may be set at a high level so as to return the switching device to the off-state without a large reduction in the current to the circuit embodying the switching device, whereas the latching current may be set at a low level to reduce the heat dissipation in the device just prior to the transition from the latching state to the holding state. The device, which may be implemented in either linear technology or with discrete components, is a thyristor structure defined by npn and pnp bipolar transistor devices each having its base connected to the collector of the other. Each transistor device has a resistance between its base and emitter, and in the case of at least one of the transistor devices that resistance varies with the voltage on the collector of the associated transistor device.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: September 19, 1989
    Assignee: Northern Telecom Limited
    Inventor: Jerzy Borkowicz
  • Patent number: 4864454
    Abstract: Differentially-connected pairs of JFETs on an IC chip are protected from ESD events by connecting respective discharge control resistors to the drains of the JFETs in such a manner as to be in series with any flow of current through either JFET.
    Type: Grant
    Filed: April 21, 1988
    Date of Patent: September 5, 1989
    Assignee: Analog Devices, Incorporated
    Inventor: Edward L. Wolfe
  • Patent number: 4862310
    Abstract: A battery protection device for preventing battery charging comprises a diode formed with a p+ region (36) within an N-type region (34). The diode is completely surrounded by a P-well (32) to prevent minority carrier injection from the N-type region (34) to the N-type substrate (30). The N-type region (34) is connected to the P-well (32) and to the substrate (30) through an electrical connection (43). By preventing minority carrier injection into the substrate (30), leakage through a parasitic transistor is prevented.
    Type: Grant
    Filed: April 29, 1988
    Date of Patent: August 29, 1989
    Assignee: Dallas Semiconductor Corporation
    Inventor: Thomas E. Harrington, III
  • Patent number: 4860148
    Abstract: A semiconductor integrated circuit device is provided with an input and/or an output terminal and at least one semiconductor device. The circuit has a resistor provided between the input terminal and/or the output terminal and one of the at least one semiconductor devices and an electronic switch connected in parallel with the resistor. The electronic switch is on-off controlled so as to exhibit a relatively low impedance when the semiconductor device is in operation and a relatively high impedance when the semiconductor device is not in operation. Thus, the semiconductor integrated circuit device is operable at a higher speed with an improved reliability and/or with controllable response characteristics, as compared with the conventional device.
    Type: Grant
    Filed: April 13, 1987
    Date of Patent: August 22, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Ikuro Masuda, Hideaki Uchida
  • Patent number: 4855649
    Abstract: Disclosed is a novel switching circuit directed to use for limiting surge into lamp, comprising a diode circuit wherein two sets of diodes are connected in reverse-parallel; a resistive element connected in series with a lamp to limit the switch-on surge thereinto; a bidirectionally conductive element having a main current path connected in seried with an ac source through said resistive element, diode circuit and lamp; and a timing circuit having a time constant, said timing circuit triggering said bidirectionally conductive element with the voltage across said diode circuit to short-circuit said resistive element after a lapse of said time constant from switch-on.
    Type: Grant
    Filed: January 27, 1988
    Date of Patent: August 8, 1989
    Assignee: Ken Hayashibara
    Inventor: Kazumi Masaki
  • Patent number: 4853821
    Abstract: Safety appparatus for sensing an electrically powered device connected to an AC power source to prevent the start-up of the device upon power restoration when the power device is in its "ON" operative condition includes a current sensing circuit that is responsive to reconnection of such a load to prevent the establishment of an electrical circuit path through the device. Included are circuits for sensing the presence of the AC power and for the generation of the sensing current are also presented.
    Type: Grant
    Filed: November 29, 1988
    Date of Patent: August 1, 1989
    Inventor: Dennis E. Lewis
  • Patent number: 4853823
    Abstract: An electrical receptacle is disclosed which deactivates the front of an electrical receptacle when an electrical plug is not present. The receptacle includes a semiconductor switch mounted between the hot contacts of the receptacle, and the hot conductor of an electrical power cable. The receptacle also includes a momentary contact switch located between the contacts of the ground receptacle portion, activated by the ground pin of an electrical plug upon engagement, and deactivated upon retraction of the electrical plug. The momentary contact switch, when activated, also activates the semiconductor switch which in turn, activates the receptacle front.
    Type: Grant
    Filed: March 21, 1988
    Date of Patent: August 1, 1989
    Assignee: AMP Incorporated
    Inventors: Joe R. Arechavaleta, William D. Berg, Frank P. Dola
  • Patent number: 4843515
    Abstract: Disclosed is improved apparatus for applying a test electrical surge from a surge generator to equipment under test. The apparatus includes a coupler/filter that comprises an inductor in each leg of the input power line. In order to dissipate the energy stored in the inductors as the result of a unidirectional test surge, and thereby prevent damage from undershoot to the equipment under test, the apparatus includes high voltage rectifiers across the inductors.
    Type: Grant
    Filed: August 18, 1987
    Date of Patent: June 27, 1989
    Assignee: KeyTek Instrument Corp.
    Inventor: Peter L. Richman
  • Patent number: 4843513
    Abstract: A method by which a turbine generator (1, 2, 3) can be protected against sub-synchronous frequencies occurring in an electric network which is connected to the turbine generator and which incorporates capacitors. The method is based on de-equalizing the subsynchronous natural frequencies of the three phases, so as to weaken the coherence of the frequencies. This is achieved by incorporating in each of two of the phases a respective inductance L of mutually different size and by changing the capacitance equivalently with a series capacitance C such as to fulfill the condition 1/LC=.omega..sub.o.sup.2, where .omega..sub.o is the network frequency.
    Type: Grant
    Filed: March 28, 1988
    Date of Patent: June 27, 1989
    Assignee: Asea Brown Boveri AB
    Inventor: Abdel-Aty O. M. Edris
  • Patent number: 4837458
    Abstract: A flip-flop circuit which requires only a small drive power and which operates with small power consumption, and in which the on-off transition occurs reliably. The flip-flop circuit comprises MOS field effect transistors (abbreviated as MOSFET's) and resistors. A first MOSFET and a second MOSFET, to which control signals are applied, are commonly-connected at their sources to be connected at the sources to a voltage source supplying a power supply voltage sufficiently higher than a threshold voltage of a third MOSFET and a fourth MOSFET interconnected to each other. The interconnected third and fourth MOSFET's are connected at their gates to the drains of the first and second MOSFET's, respectively, and to the drains of the fourth and third MOSFET's through resistors, respectively. The third and fourth MOSFET's are common-connected at their sources. An output terminal is led out from the drains of the first and third MOSFET's.
    Type: Grant
    Filed: August 19, 1987
    Date of Patent: June 6, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Sigeyuki Kawahata, Yoshitaka Sugawara
  • Patent number: 4835653
    Abstract: An electrostatic discharge protection circuit includes a P.sup.- doped channel and an N.sup.- doped channel that form a serial path between a signal pad and a transistor. Holes are depleted from the P.sup.- doped channel in response to a negative electrostatic discharge on the input signal pad; and electrons are depleted from the N.sup.- doped channel in response to a positive electrostatic discharge on the input signal pad. When either depletion occurs, the path from the signal pad to its transistor is open circuited; and so the transistor is protected. Conversely, when no electrostatic charge exists on the signal pad, the path through the P.sup.- doped channel and the N.sup.- doped channel is highly conductive; and so signals pass between the pad and the transistor very quickly.
    Type: Grant
    Filed: January 19, 1988
    Date of Patent: May 30, 1989
    Assignee: Unisys Corporation
    Inventors: Xiaonan Zhang, Xiaolan Wu
  • Patent number: 4821136
    Abstract: A power transistor with self-protection against direct secondary breakdown comprises a plurality of elementary transistors having their emitter terminals mutually connected and forming a common emitter terminal, collector terminals also mutually connected and forming a common collector terminal, and base terminals connected to at least one current source. Switches are furthermore provided selectively associated with some of the elementary transistors, preferably with one elementary transistor every two, and allowing operation of the associated elementary transistors in the saturation operating region and switching off the associated elementary transistors during high-voltage operation.
    Type: Grant
    Filed: September 21, 1987
    Date of Patent: April 11, 1989
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Bruno Murari, Flavio Villa
  • Patent number: 4819120
    Abstract: An impedance arrangement is provided for use in a high-voltage circuit. For example, the impedance arrangement is useful in a circuit which includes reactance elements and a high-voltage circuit-switching device. The impedance arrangement limits transient inrush current and/or voltages in a first frequency range which occur in the circuit during closure of the circuit-switching device and damps transients in a second frequency range which occur in the circuit during opening of the circuit-switching device. The impedance arrangement is also useful in applications requiring tuning reactors and current-limiting to limit abnormal power-frequency currents, harmonics, transients, and/or high-frequency inrush currents. The impedance arrangement functions predominantly as an inductive impedance over a first frequency range; e.g., corresponding to the frequencies of transients encountered during the closing of a circuit-switching device.
    Type: Grant
    Filed: May 18, 1987
    Date of Patent: April 4, 1989
    Assignee: S&C Electric Company
    Inventor: Raymond P. O'Leary
  • Patent number: 4819047
    Abstract: A protection system for CMOS integrated circuits to prevent inadvertent damage caused by electrostatic discharge includes a low impedance power supply bus structure and a plurality of bipolar and MOS clamping networks. The bipolar clamping networks are formed around each of the bonding pads for interlinking all of them together through the low impendance power supply bus structure. When any one of the bonding pads receives a higher voltage than a predetermined value and another remaining one of the bonding pads contacts a ground potential, current is routed from the one bonding pad through the low impedance power supply bus structure to the other bonding pad in order to discharge the same.
    Type: Grant
    Filed: May 15, 1987
    Date of Patent: April 4, 1989
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Glen Gilfeather, Joe W. Peterson
  • Patent number: 4819117
    Abstract: A method and apparatus are disclosed for detecting excessive current draw in an electrical load particularly of the type having an in-rush current when first energized. The electrical load is connectable to an energy source through a current sensing circuit and an actuatable switch. The current sensing circuit provides a load sense signal that varies in response to current draw by the load. A control signal is provided to actuate the switch. A coupling network temporarily couples the control signal to the load sense signal to offset the change in the load sense signal resulting from current in-rush. The load sense signal is compared against a reference signal. The comparator outputs a signal indicative of whether the load sense signal is greater or less than the reference signal. One signal from the comparator is indicative of excessive current draw.
    Type: Grant
    Filed: August 25, 1987
    Date of Patent: April 4, 1989
    Assignee: TRW Inc.
    Inventors: Daniel G. Brennan, Mark J. Gutwald, Leonard J. Miller
  • Patent number: 4816956
    Abstract: Stray voltage reduction apparatus for installation in an electrical power system to complete a path of electrical continuity between a primary neutral of a power distribution transformer and a grounding conductor at a service entrance, the primary neutral being also attached to a ground connection but nevertheless having a stray voltage relative to true earth which would appear on the grounding conductor at the service entrance if the primary neutral were directly connected to the grounding conductor at the service entrance. The stray voltage reduction apparatus includes a coil having turns wound around a core establishing a magnetic circuit for the coil. The core is made of a material having an initial permeability in excess of about 50,000 and being substantially saturated when the flux density is no more than about 10,000 gauss. The coil is wound around the core to have an impedance at 60 Hz.
    Type: Grant
    Filed: February 23, 1988
    Date of Patent: March 28, 1989
    Assignee: Ronk Electrical Industries, Inc.
    Inventors: Claude M. Hertz, Leroy B. Ronk
  • Patent number: 4811156
    Abstract: The medical current limiting circuit is for use with medical electrodes and associated diagnostic and therapeutic apparatus. The device protects the apparatus and patient from current flow. The device has circuitry comprising a pair of external connectors, a pair of n-type field effect transistors connected in cascade, a resistor, a p-type field effect transistor, a capacitor to latch the p-FET in a non-conductive state upon its initial activation and a diode to prevent capacitor discharge to the current source.
    Type: Grant
    Filed: February 26, 1988
    Date of Patent: March 7, 1989
    Assignee: Cherne Medical, Inc.
    Inventor: Mark W. Kroll
  • Patent number: 4811155
    Abstract: Two resistors are connected in series between an input bonding electrode and an internal circuit, and respective conducting terminals of a first bipolar transistor are connected between the two resistors and a GND bonding electrode which is connected to the internal circuit. Respective conducting terminals of a second bipolar transistor are connected between the two resistors and a V.sub.DD bonding electrode which is connected to the internal circuit. Control terminals of the respective ones of the first and second bipolar transistors are connected to the GND bonding electrode respectively.
    Type: Grant
    Filed: January 11, 1988
    Date of Patent: March 7, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirotada Kuriyama, Tomohisa Wada, Shuuji Murakami
  • Patent number: 4809124
    Abstract: This surge arrester is for protecting against high-energy and very fast surges and comprises first and second electrodes and a metal oxide varistor (MOV) disk between the electrodes. Each electrode has a central region and, at generally diametrically-opposed sides thereof, a source terminal and a load terminal. The terminals of each electrode are connected in the protected circuit in such a manner that load current in each of the conductors of the protected circuit flows through the electrode via a path that extends in series through the source terminal, the central region, and the load terminal. The source terminals of the two electrodes are generally aligned with each other about the periphery of the MOV disk, and the load terminals are also generally aligned with each other about the periphery of the disk.
    Type: Grant
    Filed: March 24, 1988
    Date of Patent: February 28, 1989
    Assignee: General Electric Company
    Inventor: James S. Kresge
  • Patent number: 4809122
    Abstract: A self-protective driver circuit with automatic reset features is provided for a marine electric fuel pump (2, 102) energized by the boat battery (4, 104) as controlled by a series connected semiconductor switch (6, 106). A first stage protective subcircuit (28, 128) senses surge current through the semiconductor switch at initial turn on with the fuel pump at rest and causes the semiconductor switch to depart from saturated conduction and thus limit the current until the pump starts running and the current decreases to a safer level, to protect the semiconductor switch from excessive current.
    Type: Grant
    Filed: July 31, 1987
    Date of Patent: February 28, 1989
    Assignee: Brunswick Corporation
    Inventor: Arthur O. Fitzner