Impedance Insertion Patents (Class 361/58)
  • Patent number: 5724219
    Abstract: A semiconductor device according to this invention comprises a first power supply (Vcc) wiring, a second power supply (Gnd) wiring, a first, a second and a third protective elements (3-1, 3-2 and 3-3), a first connecting wiring which connects in common one ends of the first, the second and the third protective elements, a second connecting wiring which connects the other ends of the first, the second and the third protective elements, and a third connecting wiring which connects the first connecting wiring and the first power supply wiring. The third connecting wiring has a resistance which is higher than that of the first connecting wiring.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: March 3, 1998
    Assignee: NEC Corporation
    Inventor: Kaoru Narita
  • Patent number: 5714809
    Abstract: A hot-plugging circuit for controlling the rate of application or withdrawal of both voltage and current to a user circuit to permit power up or down of the user circuit either to conserve energy usage in operation or to facilitate non-disruptive insertion or extraction of the user circuit from a larger, continually-powered, circuit. A semiconductor switch is used as the principle current and voltage control element. Current through the switch is monitored during transitions, and is converted to a voltage level. A voltage ramp relative to the voltage applied to the user circuit is generated and compared with the current representing voltage level to generate a control signal for controlling the rate of turn ON or turn OFF of the semiconductor switch. The voltage ramp generation is controlled by an ON/OFF control voltage level.
    Type: Grant
    Filed: October 12, 1995
    Date of Patent: February 3, 1998
    Assignee: International Business Machines Corporation
    Inventor: Raymond Mathew Clemo
  • Patent number: 5712754
    Abstract: A protection circuit for a computer system having PCI expansion cards and PCI expansion slots with multiple power rails for supplying power to the PCI expansion cards, the protection circuit including a current monitor that monitors the current levels drawn by the PCI expansion card at each power rail; an inrush current controller for controlling the initial current applied to each of the power rails when an expansion card is initially inserted into an expansion slot; a voltage monitor that monitors the voltage levels applied to selected power rails; and a disconnector for disconnecting the power to the PCI expansion slot when either the current level drawn by the PCI expansion card at any of the power rails goes beyond a selected range or when the voltage levels at any of the selected monitored power rails are below a selected threshold or when commanded by the computer system.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: January 27, 1998
    Assignee: Compaq Computer Corporation
    Inventors: Chi Kim Sides, Philip James McKenzie, Barry S. Basile
  • Patent number: 5699219
    Abstract: A ground fault current limiter, in which reactors are connected in series to a neutral point for compensating for capacitances to ground of a power switches capable of turning ON/OFF at a high speed are connected in parallel with respective reactors, occurrence of a ground fault is detected from a phase difference between a zero-phase sequence current and a zero-phase sequence voltage at time of sampling, an optimal compensation quantity of capacitances to ground is computed based on the zero-phase sequence current and the zero-phase sequence voltage at time of occurrence of a ground fault, and ON/OFF of the switches are controlled thereby to alter the reactor quantity so as to correspond to the compensation quantity.
    Type: Grant
    Filed: May 16, 1995
    Date of Patent: December 16, 1997
    Assignees: Hitachi, Ltd, Chubu Electric Power Co., Inc.
    Inventors: Hiroshi Arita, Junzo Kida, Yoshiaki Matsui, Tokio Yamagiwa, Shigeyuki Sugimoto, Sadanori Neo
  • Patent number: 5689396
    Abstract: A signal input unit for a semiconductor memory device comprising a signal input terminal, an electrostatic discharge protection circuit for discharging an electrostatic signal of high level from the input terminal to a ground voltage source, a signal transfer circuit connected in parallel to the electrostatic discharge protection circuit, for switching a normal input signal from the input terminal, a signal transfer control circuit for controlling a switching operation of the signal transfer circuit, and a signal input circuit for buffering an output signal from the electrostatic discharge protection circuit or the signal transfer circuit and transferring the buffered signal to an internal circuit of the semiconductor memory device. The electrostatic discharge protection circuit sufficiently discharges the external electrostatic signal to the ground voltage source in a standby mode of the semiconductor memory device.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: November 18, 1997
    Assignee: Hyundai Electronics Industries, Co., Ltd.
    Inventor: Jae Jin Lee
  • Patent number: 5675896
    Abstract: A portable electric working machine of the present invention includes a motor case portion housing an electric motor, a working portion driven by the electric motor, a handle connected to the motor case portion or the working portion and a power source switch disposed within a grip portion of the handle. Electric power is supplied to the electric motor through the power source switch. A spark-preventing capacitor accommodated within the motor case portion is interposed between a pair of terminals of the electric motor. The portable electric working machine of the present invention does not require a large-sized grip portion of a handle, and can prevent a locking of contacts of a power source switch due to contact transition by preventing sparking between the contacts so that a small-sized microswitch can be used.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: October 14, 1997
    Assignee: Kioritz Corporation
    Inventors: Fumihiko Aiyama, Tatsuhiko Matsubayashi, Naoki Tsuda
  • Patent number: 5675467
    Abstract: The present invention relates to a circuit mounting unit that can prevent a voltage drop and noise occurrence due to current inflow at the time of a hot insertion or withdrawal operation without mounting a capacitor with large capacitance on the side of a main unit. The circuit mounting unit includes a first voltage control unit that controls to increase gradually a voltage supplied to a load voltage converter from the main unit side to a predetermined voltage when the circuit mounting unit is exchangeably inserted into or pulled out of the main unit without halting electric power supplied from the main unit. The circuit mounting unit is mounted onto a printed wiring board on which various elements such as ICs and LSIs are previously mounted to form a predetermined circuit.
    Type: Grant
    Filed: June 28, 1995
    Date of Patent: October 7, 1997
    Assignee: Fujitsu Limited
    Inventors: Hisayuki Nishimura, Shigeru Honda, Naohiro Shibata
  • Patent number: 5671110
    Abstract: A method and apparatus are provided for protecting a non-isolated data communications cable against ground skew used with an AC power source. A current summing transformer is coupled to an AC power source. The current summing transformer includes a single transformer core and a plurality of coils. One of the coils is connected in series with each phase, neutral (if present) and ground line in the AC power source. The plurality of coils are substantially identical. Each coil has an identical number of turns and an identical direction of winding on the transformer core. The current summing transformer is only needed in the power path to one of two or more interconnected systems. The current summing transformer introduces a high impedance to surge current in the data cable ground of one or many non-isolated data cables attached to the system and at the same time offers substantially zero impedance to the normal power currents including leakage and fault ground currents.
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: September 23, 1997
    Assignee: Oneac Corporation
    Inventors: Thomas McCartney, Laurence H. Fish
  • Patent number: 5666255
    Abstract: A transformerless conditioner of a power distribution system consists of an electronically enhanced filter (EEF) for suppression of transient impulses on the power line and neutral line, and a transformerless ground conditioner for suppression of transient impulses on the ground line. The filter includes a normal mode filter having an inductor located on the power line and an inductor located on the neutral line between source and load of the power distribution system, and a pair of capacitors arranged in series and connected between the power and neutral lines, whereby a midpoint tap is formed between the pair of capacitors. The EEF also includes a unique common mode filter which is formed by the series connection of either inductor of the power line or the neutral line, or both, to its corresponding capacitor and then to the midpoint, from which an electronic impulse detector is connected to ground.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 9, 1997
    Assignee: Powervar, Inc.
    Inventor: Norman F. Muelleman
  • Patent number: 5657195
    Abstract: An overcurrent protection device designed to be connected in series between a load and an electric supply includes a switch which is controlled by a voltage present across a current limiting device. The switch is formed by a GTO thyristor connected in series with the current limiting device. The output of the current limiting device is connected to the load.
    Type: Grant
    Filed: April 12, 1995
    Date of Patent: August 12, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Pierre Rault
  • Patent number: 5654860
    Abstract: A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.
    Type: Grant
    Filed: August 16, 1995
    Date of Patent: August 5, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Stephen L. Casper, Manny K. F. Ma, Joseph C. Sher
  • Patent number: 5650904
    Abstract: Fault tolerant thermoelectric device circuit (18) is provided including a plurality of thermoelectric elements (19, 20, 21, and 22) and a plurality of secondary by-pass circuits (24, 25, 26, and 27) coupled in parallel with a number of the thermoelectric elements. The secondary by-pass circuits provide by-pass paths to failed thermoelectric elements, thereby allowing the remaining elements to continue operating. Primary by-pass circuit (30) is also provided to provide a by-pass path to all of the thermoelectric elements as required.
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: July 22, 1997
    Assignee: Marlow Industries, Inc.
    Inventors: Michael D. Gilley, Michael J. Doke
  • Patent number: 5650903
    Abstract: A superconductive-magnet electrical circuit includes a superconductive-coil assemblage having first, second, third, and fourth coil portions sequentially coupled together in series. A bipolar current-bypass electrical-circuit element (such as a pair of diodes opposingly coupled together in parallel) has:an impedance less than generally one-thousandth that of the coil portions; a first terminal coupled in parallel with the first and second coil portions; and a second terminal coupled in parallel with the third and fourth coil portions. A localized quench in one coil portion is quickly shared with the other coil portions to reduce damage from the quench. A resistor has a lead coupled in parallel with the second and third coil portions to limit quench voltages.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: July 22, 1997
    Assignee: General Electric Company
    Inventors: Dan Arthur Gross, David Charles Mack, Timothy John Havens
  • Patent number: 5650901
    Abstract: A circuit breaker for a distribution system includes a non-self-extinction type semiconductor switch, a current limiting element connected in series to the semiconductor switch for suppressing a fault current. The semiconductor switch and the current limiting element constitute a series circuit. A mechanical type high-speed switch is connected in parallel to the series circuit of the semiconductor switch and the current limiting element. Upon occurrence of a fault in the distribution system, an electric current flowing through the distribution system is commutated to the series circuit from the mechanical type high-speed switch.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: July 22, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Yamamoto
  • Patent number: 5648739
    Abstract: A switching device has at least a first connection and a second connection, as well as a control connection. The switching device includes at least a first transistor and a second transistor. A load is connected to the second connection of the switching device, and a control unit is connected to the control connection of the switching device. A power supply is normally connected to the first connection, and the second connection is normally connected to ground via the load. The switching device further includes a polarity reversal protection system for protecting the switching device and the load from damage in case of a polarity reversal, which occurs when the power supply is connected to the second connection through the load, and the first connection is connected to ground. The second transistor is connected in series between the first connection of the switching device and the first transistor. The second transistor is operated inversely with respect to the first transistor.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: July 15, 1997
    Assignee: Robert Bosch GmbH
    Inventors: Michael Walther, Gerhard Siese
  • Patent number: 5646810
    Abstract: The invention is a combination of an altered AC to DC circuit utilized with typical power protection components for improved power protection purposes. More particularly, in accordance with the present invention there is provided a parallel circuit to protect electrical and electronic equipment from transients from an electrical system. The circuit comprises (a) first uni-directional diodes attached to line, neutral and/or ground connection of the electrical system; (b) a DC capacitor with a positive pole being fed by said first uni-directional diodes; (c) uni-directional diodes attached and feeding back to line, neutral and/or ground connection, said negative pole feeding said second uni-directional diodes; and (d) a discharge resistor in parallel with said DC capacitor.
    Type: Grant
    Filed: October 3, 1995
    Date of Patent: July 8, 1997
    Inventor: James Funke
  • Patent number: 5642249
    Abstract: The present invention pertains to an electrical fault limiter. The fault limiter comprises a first magnetic core. There is also a second magnetic core opposing the first magnetic core. The fault limiter additionally comprises a third magnetic core adjacent the first magnetic core. Also, there is a fourth magnetic core opposing the third magnetic core and adjacent the second magnetic core. The electrical fault limiter also moreover comprises a rotor disposed between the first and second magnetic cores, and the third and fourth magnetic cores. The rotor is rotatable about a rotor axis. The first and second magnetic cores are disposed on a first side of the rotor axis and the third and fourth magnetic cores are disposed on a second side of the rotor axis. Each core has a first arm, a second arm and a body to which the first and second arms are connected. Each body has a superconducting bias coil disposed about it. Each arm has a conduction mode coil disposed about it.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: June 24, 1997
    Inventor: Stephen B. Kuznetsov
  • Patent number: 5640059
    Abstract: A power supply system including a thermal current limiting device operating due to high temperatures. At predetermined temperatures, the device acts to incrementally control the output of a power supply. An implementation of the device may be found in a voltage or power regulator wherein a constant output voltage or power is desired. As temperature increases, the power supply system is not switched off, rather current output is adjusted in a controlled manner thereby eliminating the need for the device to be entirely shut down for a time period. A back-up battery is used to provide supplementing current needed by the load.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: June 17, 1997
    Assignee: Reltec Corporation
    Inventors: Neil A. Kammiller, Brian D. Goodlive, Zissis L. Kalivas
  • Patent number: 5638246
    Abstract: In a semiconductor device including a power MOSFET (M.sub.0) for the output stage, a temperature detection circuit produces an output signal upon detecting an abnormal rise in the chip temperature, the signal turns on a set input element (M.sub.1) in a latch circuit so that the latch circuit becomes a set state, the set output of the latch circuit turns on a control element (M.sub.5), causing the power MOSFET to become non-conductive so that it is protected from destruction. The latch circuit is not brought to a reset state even if the external gate terminal of the device is brought to zero volt. With a voltage outside the range of the normal input signal, e.g., a large negative voltage, being applied to the external gate terminal, the gate capacitance of the control element (M.sub.5) discharges, and consequently the latch circuit is brought to the reset state and the protective operation is cancelled.
    Type: Grant
    Filed: January 28, 1993
    Date of Patent: June 10, 1997
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Kozo Sakamoto, Isao Yoshida, Masatoshi Morikawa, Shigeo Ohtaka, Hideki Tsunoda
  • Patent number: 5631794
    Abstract: A differential shunt-type detector circuit includes a voltage-regulator component series combined with one or more than one shunt components in a circuit connected in parallel with, for example, a thermostatic switch element, such that when the terminal voltage of the shunt components is within the voltage-regulator component work range, no shunt or distribution or shunting effect is generated by the voltage-regulator component, while when the terminal voltage exceeds the voltage-regulator component work range, a shunt or distribution effect is obtained.
    Type: Grant
    Filed: October 3, 1994
    Date of Patent: May 20, 1997
    Inventor: Tai-Her Yang
  • Patent number: 5629569
    Abstract: A self-configuring photoelectric control circuit for controlling operation of a load based on ambient light. The photocontrol circuit comprises a photocell responsive to ambient light, a heating resistor connected to the photocell, a bimetallic element in proximity to the heating resistor and movable in response to generation of heat from the heating resistor. A switch is operated by the bimetallic element and is connected between an input connected to a power source and an output connected to the load. A series resistor is connected to the heating resistor and a shunt is connected across the series resistor to provide a current bypass around the series resistor for operation with a low voltage power source, for instance 120 volts. The shunt is maintained in a flexed condition to form the bypass and a connection of the shunt across the series resistor is formed of a meltable material.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: May 13, 1997
    Assignee: Intermatic, Inc.
    Inventor: Rudy Janda
  • Patent number: 5627738
    Abstract: A soft start circuit for a high-power module permits trickle-charging of the capacitor bank prior to power switch actuation, and avoids large current surges or inrush at power up. Positive temperature coefficient thermistor devices, or PTCs are place in shunt across the switch elements or poles of the actuator or other power switch. In a power module that is powered by three-phase AC, the three power conductors are coupled through a three-pole contactor to AC inputs of a polyphase rectifier bridge, which has DC outputs coupled to the capacitor bank and to a load device, such as a high-power RF amplifier. The PTCs are connected, one per pole, in shunt across each pole of the contactor. Alternatively, metallized film capacitors can be employed in lieu of the PTCs.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: May 6, 1997
    Assignee: ENI, A Division of Astec America, Inc.
    Inventors: Vadim Lubomirsky, Jeff C. Sellers
  • Patent number: 5621600
    Abstract: A portable apparatus to test an automobile wiring harness for the location of a short in one of the wires. A transmitter is used to apply a low frequency, low duty cycle, pulsed signal to the wire under test. A receiver, with an inductive sensor, detects magnetic fields generated by the pulsed signal current flow between the transmitter and the short. The receiver generates a humanly discernable signal in response to the detected magnetic field. The operator finds the short by following the detected magnetic field of the signal pulse through the wire under test. By noting the location of a dramatic discontinuity in magnetic field strength, the operator can gauge the location of the short in the wire. The low voltage amplitude, low duty cycle, pulse signal allows the transmitter to be operated with a small battery. The low power signals also provide safety to circuits connected to the wire. The low frequency and power of the pulsed signal minimizes coupling between wires.
    Type: Grant
    Filed: February 1, 1994
    Date of Patent: April 15, 1997
    Inventor: Akira Iijima
  • Patent number: 5621599
    Abstract: A metal oxide varistor in series with a semiconductor switch forms a protection circuit that reduces the steady-state voltage across the metal oxide varistor during normal operation, During an overvoltage transient condition, the semiconductor switch is gated on and the metal oxide varistor is placed in the voltage clamping mode.
    Type: Grant
    Filed: September 13, 1994
    Date of Patent: April 15, 1997
    Assignee: General Electric Company
    Inventors: Einar V. Larsen, Murray A. Eitzmann, Loren H. Walker
  • Patent number: 5617284
    Abstract: A power surge protection apparatus (10) protects circuitry from electrical surges induced in an alternating current power connection to the circuity. The apparatus (10) comprises first, second, and third stages (16, 17, 18), which serve to clamp and dissipate superfluous energy, such as that from a power surge, on the power connection (12a, 12b). The first stage (16) comprises a metal oxide varistor MOV 1 and a capacitor (C1) for helping to clamp and dissipate large-duration continuous surges on the power connection (12a, 12b). The second stage comprises an RC-LC filter with resistor R1, capacitor C2, inductor L1, and capacitor C3. Moreover, the second stage (17) has a metal oxide varistor MOV 2. Importantly, the second stage (17) further comprises a bifilar transformer T1 situated between the connections (24A, 24b).
    Type: Grant
    Filed: August 5, 1994
    Date of Patent: April 1, 1997
    Inventor: Rick Paradise
  • Patent number: 5617282
    Abstract: A data communication system, particularly for motor vehicles, includes a bus system with transmission lines which connect terminal devices to a common node. A protective circuit is connected between the transmission lines and a reference potential such as ground. If the ground connection of one of the terminal devices becomes detached, this protective circuit allows communication among the remaining terminal devices. The protective circuit is simultaneously secured against destruction in case of a short circuit.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: April 1, 1997
    Assignee: Daimler-Benz AG
    Inventors: Bernhard Rall, Jurgen Dorner
  • Patent number: 5612847
    Abstract: A vehicle door (22) has a window (24) capable of being opened and closed. A master power window switch assembly (26) is mountable in an arm rest (28) of the door (22) near a driver of the vehicle. A polyswitch resettable fuse (56) is connected to a printed circuit board (50) of a master power window switch assembly (26) through a jumper terminal (58). An electrically conductive trace (52) is electrically connected to the jumper terminal (58). The polyswitch resettable fuse (56) may be used to limit current in the conductive trace (52) on the circuit board (50). Locating the polyswitch resettable fuse (56) between the power source (40) and the circuit board (50) permits design of the conductive traces (52), (53) and the circuit board electrical components for normal operating currents instead of significantly larger foreseeable motor stall current levels.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: March 18, 1997
    Assignee: TRW Inc.
    Inventors: Joseph F. Malecke, Dennis D. Kaufman, Derrick Titus
  • Patent number: 5608594
    Abstract: A semiconductor integrated circuit includes an internal circuit, and ground and power supply lines for activating the internal circuit. An output MISFET is activated by peripheral circuit ground and power supply lines. For protection of the internal circuit from the effects of ground or power supply line noise, an impedance electrically separates the power supply lines for the internal and peripheral circuits and/or the ground lines for the peripheral and internal circuits. A surge protection circuit is provided between the gate of the output MISFET, and either or both of the ground and power supply lines for the peripheral circuitry.
    Type: Grant
    Filed: August 14, 1995
    Date of Patent: March 4, 1997
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasuhiro Fukuda
  • Patent number: 5596469
    Abstract: An electrical fault limiter having first, second, third, and fourth magnetic cores. The first magnetic core opposes the second magnetic core and is adjacent to the third magnetic core. The fourth magnetic core opposes the third magnetic core and is adjacent to the second magnetic core. A rotor is disposed between the first and second magnetic cores, and the third and fourth magnetic cores. The rotor is rotatable about a rotor axis. The first and second magnetic cores are disposed on a first side of the rotor axis and the third and fourth magnetic cores are disposed on a second side of the rotor axis. Each core has a first arm, a second arm and a body to which the first and second arms are connected. Each body has a superconduction bias coil disposed about it. Each arm has a conduction mode coil disposed about it.
    Type: Grant
    Filed: February 13, 1996
    Date of Patent: January 21, 1997
    Assignee: Power Superconductor Applications Co.
    Inventor: Stephen B. Kuznetsov
  • Patent number: 5590011
    Abstract: A method and apparatus for providing electrical protection for circuits that use splice connections between a source of electrical power and wires of respective circuits. The splices provide a common connection of wires to the power source. The splice includes a positive temperature coefficient device in electrical series between the power source and the wires. The positive temperature coefficient device reduces the flow of current to the wires, and to any loads connected to the wires, when an excess amount of current flows through at least one of the wires and the splice. The temperature rise in the positive temperature coefficient device reaches a trip point, and the device remains in a trip state until power fed to the splice is removed.
    Type: Grant
    Filed: July 27, 1995
    Date of Patent: December 31, 1996
    Assignee: Alcoa Fujikura Limited
    Inventor: David A. Hein
  • Patent number: 5587685
    Abstract: Individual devices of a redundant array of independent devices (RAID) are coupled to an electrical power supply. For devices having widely varying load impedances, such as disks, incident with the coupling of electrical power thereto, the replacement or addition of a device in the system, while the system is in operation, causes unacceptable power transients in the power supply. To minimize such power transients, a transient suppression circuit is employed to isolate the load impedance of the device from the power supply. Isolation is achieved in the transient suppression circuit by employing an active circuit element, such as a MOSFET power transistor, as the power coupler. A capacitor controlled voltage divider circuit, incident with the coupling of electrical power thereto, couples a time varying gate voltage, which changes as a function of the rate of charge of the capacitor, to the MOSFET power transistor.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: December 24, 1996
    Assignee: Hewlett-Packard Company
    Inventor: Christopher W. Johansson
  • Patent number: 5585994
    Abstract: A first series circuit of a current detector and a first switch is connected in series with a battery, and a second series circuit of a resistor and a second switch is connected in parallel with the first series circuit. A control device controls an on and off state of the first and second switches to provide over-current protection of the battery. In particular, the control device turns off the first switch to cut-off battery over-current and turns on the second switch when the battery current exceeds a specified level as detected by the current detector. Then, after the battery current, which flows through the second series current, drops below the specified level, the first switch is returned to an on state to again allow battery discharge.
    Type: Grant
    Filed: January 13, 1994
    Date of Patent: December 17, 1996
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Mikitaka Tamai, Takaharu Ohira, Tetsuya Okada
  • Patent number: 5581433
    Abstract: A solid state circuit breaker for use in electronic devices which may be connected to an active computer bus. In one embodiment the solid state circuit breaker includes a digital to analog converter by way of which digital control signals are used to set the value at which the circuit breaker determines that a fault condition exists. Fault time is measured from when the fault condition is detected, and when the fault time exceeds a predetermined value, the circuit breaker opens, thereby preventing current flow through the circuit breaker for a second predetermined amount of time. Once this second predetermined amount of time elapses, the circuit breaker again permits current flow, and if a fault condition is determined to continue to exist, the cycle is repeated.The circuit breaker also includes a current limiting portion which restricts current flow to a maximum permissible value should the current flowing through the circuit breaker attempt to exceed this maximum permissible value.
    Type: Grant
    Filed: April 22, 1994
    Date of Patent: December 3, 1996
    Assignee: Unitrode Corporation
    Inventor: Mark G. Jordan
  • Patent number: 5581095
    Abstract: A bidirectional Shockley diode includes an N-type layer sandwiched between two P-type layers. A first N-type region in the P-type region extends over substantially one half of the upper surface. A second N-type region extends in the P-type layer substantially over one half of the lower surface. Each first and second region protrudes with respect to the median plane of the component by a length r such that ratio r/e is smaller than 0.5, e being the thickness of the component.
    Type: Grant
    Filed: August 30, 1994
    Date of Patent: December 3, 1996
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Jean-Claude Salbreux
  • Patent number: 5581192
    Abstract: Novel conductive liquid compositions which have low resistivity when carrying an applied steady-state current (I.sub.Steady-State) but exhibit sharp increases in resistivity when subject to an applied fault current (I.sub.Fault). When used in circuit protection devices, the novel conductive liquid compositions having low resistivity are contained within an elongated flexible tube sealed by electrodes electrically connected to a load of an electrical circuit. The conductive liquid compositions carry an applied normal current under steady-state conditions.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: December 3, 1996
    Assignee: Eaton Corporation
    Inventors: John J. Shea, James D. B. Smith, Karl F. Schoch, Jr.
  • Patent number: 5574614
    Abstract: An over-voltage protection plug for telecommunication installations, including a housing with a printed-circuit board, a voltagesurge suppressor, a slider, a spring, an earth plate, a signalling element. Reliable protection against voltage surges is provided, wherein the solder position is loaded to a minimum extent only. The plug is composed of few parts only and further permits automated manufacture at low cost, and which clearly shows the tripped condition at the outside. The slider is pre-loaded over a support face and over an edge at the inner housing wall in the housing by the spring. A shaped part of solder material is loaded to a minimum extent only by the spring force (pressure force) of the slider.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: November 12, 1996
    Assignee: Krone Aktiengesellschaft
    Inventors: Ralf-Dieter Busse, Harlad Klein, Johann Oltmanns, Gerd Richter
  • Patent number: 5572395
    Abstract: A circuit embodied within an adapter card for hot-plugging with a card slot in a card slot coupled to a processor based system utilizes a biasing circuit for ensuring that the input voltage to the load of the adapter card is of a sufficient magnitude. The circuit also includes a FET/feedback circuit for opening and closing the circuit provided between the input voltage to the adapter card and the load. This FET/feedback circuit operates as a constant current source to charge the input capacitance of the load and converts to a switched mode when the load capacitance is fully charged. The biasing circuit controls the FET/feedback circuit so that it remains open during hot-plugging of the adapter card into the card slot to alleviate pin arching. A monitor/timer circuit prevents the FET/feedback circuit from operating in the constant-current mode for no longer than a predetermined amount of time.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: November 5, 1996
    Assignee: International Business Machines Corporation
    Inventors: Todd M. Rasums, Frederick K. Yu
  • Patent number: 5570255
    Abstract: An overcurrent detecting circuit provided within a battery pack detects any overcurrent flowing in a circuit electrically connecting the battery and connection terminals. Upon detection of any overcurrent by this overcurrent detecting circuit, a switch circuit intercepts the electric connection between the battery and the terminals, and opens the so far closed circuit.
    Type: Grant
    Filed: February 2, 1995
    Date of Patent: October 29, 1996
    Assignee: NEC Corporation
    Inventor: Masaru Hirata
  • Patent number: 5568346
    Abstract: A input circuit provides ESD protection to an integrated circuit comprising a V.sub.dd pad, a V.sub.ss pad, a plurality of input and output pads, a V.sub.dd power rail, and a V.sub.ss power rail. A large diode sufficient to carry ESD current is placed directly between the V.sub.ss pad and the V.sub.dd power rail, and the input pads are connected to the V.sub.dd power rail through respective diodes.
    Type: Grant
    Filed: February 8, 1995
    Date of Patent: October 22, 1996
    Assignee: Mitel Corporation
    Inventor: Jonathan H. Orchard-Webb
  • Patent number: 5566040
    Abstract: A protection arrangement for an electronic device sensitive to electromagic radiation comprises a single printed circuit board which is disposed within a metal casing so that it passes perpendicularly through a metal partition separating an upstream zone in which electromagnetic fields prevail from a screened downstream zone, the board thus having a first part situated in the upstream zone and a second part, which is intended to carry the electronic device, situated in the downstream zone. Electrical signals are conveyed from the upstream zone to the downstream zone by means of conductive lines printed on at least one inner layer of the printed circuit board, and the board is provided with means for filtering the electrical signals comprising surface-mounted components in the vicinity of the metal partition and capacitive elements integrated in the printed circuit board where it passes through the partition.
    Type: Grant
    Filed: May 16, 1995
    Date of Patent: October 15, 1996
    Assignee: Societe Nationale d'Etude et de Construction de Moteurs D'Aviation
    Inventors: Jean M. Cosquer, Alain J. Fabre, Robert Poirier
  • Patent number: 5565826
    Abstract: The protective device for protecting against over currents in electric circuits includes at least one electrically conductive body and two electrodes which function to supply circuit current through the conductive body and which lie against the conductive body at corresponding positions either directly or through the medium of an intermediate part. An abutment pressure is applied to the electrode so that the electrodes are maintained in abutment at the corresponding positions of the conductive body. When the devices are subjected to high short circuiting currents, the current density in the deformed abutment surfaces of the conductive body will increase, thus increasing the resistance of the device.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: October 15, 1996
    Inventor: Per Olof Karlstrom
  • Patent number: 5559660
    Abstract: A method and apparatus for preventing current inrush upon the application of power to a load includes the steps of applying a first increasing DC voltage from a voltage source to the load through a single signal path which includes a transistor having a control electrode coupled to the voltage source and a second electrode coupled to the load. The transistor has a first operating region with an ON resistance characteristic which decreases between first and second applied control voltages. The transistor has a second operating mode in which the transistor has a relatively low on resistance R.sub.ON. The transistor is thus disposed in the single signal path to both limit inrush current and to provide a low loss signal path between the voltage source and the load.
    Type: Grant
    Filed: March 22, 1994
    Date of Patent: September 24, 1996
    Assignee: EMC Corporation
    Inventors: Donald R. Watson, Christopher A. Heyden
  • Patent number: 5559656
    Abstract: A circuit for preventing switching voltage transients from damaging the IGBT during short circuit shut off, utilizing electronic gate control which decrease the rate of fall of the gate voltage of the IGBT only when a short circuit condition is sensed, thereby avoiding any losses during normal switching operation. In a first embodiment, a considerably higher value of gate resistor is switched-in in series with the gate resistor during a short circuit condition. In a second embodiment, a considerably higher value of external capacitor is switched-in in parallel with the IGBT gate input capacitance during a short circuit condition.
    Type: Grant
    Filed: February 22, 1995
    Date of Patent: September 24, 1996
    Assignee: International Rectifier Corporation
    Inventor: Rahul S. Chokhawala
  • Patent number: 5555510
    Abstract: A method applicable to a host computer system having a system bus connected to a CPU, and a PCMCIA controller having status registers, means for supplying back off signals to the CPU and line buffers capable of being in a normal and high impedance state. A multi pin connector is located in each card socket and connected to a line buffer. Each connector has common address, data and control pins, power pins, ground pins longer than the data pins and card detect signal pins shorter than the signal pins. The first step is to detect the commencement of an insertion or removal of a PCMCIA card to or from a socket by monitoring the ground and card detect signal pins. After detection, commence termination of all CPU usage of common address, data and control lines by asserting a back off signal. Next, determine if the usage is terminated by monitoring the status registers in the controller. Next, place the common address, data and control lines in a high impedance state.
    Type: Grant
    Filed: August 2, 1994
    Date of Patent: September 10, 1996
    Assignee: Intel Corporation
    Inventors: Jerry Verseput, Fong-Shek Lam, Prasanna Shah
  • Patent number: 5555150
    Abstract: Disclosed is a surge suppression system employed in a system comprising Hot and Neutral power line segments coupled via a filter to protected electronic circuitry. The surge suppression elements include a spark gap comprising a first electrode connected to the Neutral line segment and a second electrode connected to the ground potential; and a voltage clamping device electrically connected to the Hot and Neutral line segments at a point which is electrically closer to the protected electronic circuitry than the spark gap. The invention permits the filter to ring up to high voltages, and provides a mechanism whereby electrical breakdown occurs at a prescribed point. Surge suppression is provided after the filter by the single ungrounded clamping device.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: September 10, 1996
    Assignee: Lutron Electronics Co., Inc.
    Inventor: Robert C. Newman, Jr.
  • Patent number: 5546261
    Abstract: A superconducting fault current limiter composed of an induction coil wound around a core made of a soft magnetic material such as soft iron, ferrite or the like, a cylindrical superconductive body arranged in surrounding relationship with the induction coil and a cooling container formed to contain only the superconductive body therein and filled with cooling liquid such as liquid nitrogen or helium to immerse therein the superconductive body.
    Type: Grant
    Filed: March 28, 1994
    Date of Patent: August 13, 1996
    Assignee: NGK Insulators, Ltd.
    Inventors: Shinji Yoshida, Shuichiro Motoyama, Takashi Ohashi, Masamichi Ishihara
  • Patent number: 5541804
    Abstract: A current-limiting protector package for use in conjunction with telephone terminal blocks comprises a two-piece interfitting housing which is made up of two housing halves soncially welded together. A pair of tip or ring terminals is disposed within each housing half along with a current-limiting device in the form of a positive-temperature-coefficient (PTC) device of the conductive polymer type. Lower end portions of the tip or ring terminals project outwardly from the housing so as to be capable of electrical engagement with opposed sets of terminals provided upon the telephone terminal block, while upper end portions of the tip or ring terminals project outwardly from the housing so as to be accessible to a line test probe whereby the lines or circuits of the telephone terminal block can be tested in connection with their operative status without necessitating removal of the protector package from the terminal block.
    Type: Grant
    Filed: July 11, 1994
    Date of Patent: July 30, 1996
    Assignee: Illinois Tool Works Inc.
    Inventor: Bjarne Frederiksen
  • Patent number: 5535085
    Abstract: A snubber energy recovery circuit for protecting switching devices from current and voltage, which comprises a snubber circuit connected in parallel with a switching device, a recovery path for recovery the energy stored in the snubber circuit, and a constant-current source for maintaining current flowing in the recovery path at a constant value. The snubber circuit is composed of a snubber diode and a snubber capacitor, with one end of the recovery path being connected to the junction point of the snubber capacitor and snubber diode.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: July 9, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeru Tanaka, William Ofosu-Amaah
  • Patent number: 5532897
    Abstract: A high voltage substation level surge suppression system is disclosed comprising three primary elements. Two surge arrestors are used, separated by a surge interceptor. The first surge arrestor encountered is a high energy dissipater. It conducts most of the energy from a lightning induced or other fast rising high voltage surge to ground. The surge interceptor, comprises an inductor formed by wrapping insulated wire around a tube through which is inserted a parallel high energy resistor. The inductor element in the Surge Interceptor operates to delay the fast rise surge or transient long enough that the high energy dissipater can operate. The resistor element operates to dampen ringing or oscillations caused by the interaction between the inductor and a high voltage lightning strike and to dissipate some of that energy. Finally, the second arrestor, the voltage controller, operates to clamp the voltage after the Surge Interceptor to a set level.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: July 2, 1996
    Assignee: Lightning Eliminators & Consultants, Inc.
    Inventor: Roy B. Carpenter, Jr.
  • Patent number: 5530613
    Abstract: A circuit controller for selectively connecting a power source to a load includes a non-overcurrent protective electrical switching mechanism and a conductive polymer current limiter connected in series with the load for limiting the current which flows through the switching mechanism whenever the power source is selectively connected to the load. The conductive polymer current limiter may include a plurality of parallel conductive polymer positive temperature coefficient (PTC) resistors. The circuit controller may include an electrical switching mechanism which, under short circuit conditions, remains selectively connected to the load. The short circuit current which is limited by the conductive polymer current limiter continues to flow through the electrical switching mechanism. The switching mechanism may include a contactor having separable contacts, and may further include a circuit interrupter, in order to provide a separate circuit disconnection mechanism.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: June 25, 1996
    Assignee: Eaton Corporation
    Inventors: James A. Bauer, Denis A. Mueller, Henry A. Wehrli, III, James D. B. Smith