Impedance Insertion Patents (Class 361/58)
  • Patent number: 5907463
    Abstract: An overcurrent protection circuit for a switching mode power supply which has a switching transformer for transforming a rectified voltage into a plurality of drive voltages and a pulse width modulation circuit for generating a pulse width modulation signal in response to a desired one of the drive voltages from the switching transformer. The overcurrent protection circuit is connected between a drive voltage output terminal of the switching transformer and a drive voltage input terminal of the pulse width modulation circuit. The overcurrent protection circuit consists of a parallel circuit composed of an inductance and a resistance. When the switching transformer is short-circuited, the overcurrent protection circuit accelerates a drop of the drive voltage which is supplied from the switching transformer to the pulse width modulation circuit.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: May 25, 1999
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Hyoung-Sik Choi
  • Patent number: 5907464
    Abstract: Electrostatic discharge protection circuits adapted for use in low voltage CMOS processes have at least one PFET in the primary charge conduction path, and timer circuits configured to enable the primary conduction path during ESD events and to disable the primary conduction path during steady state conditions.In a further aspect of the present invention, bias circuits for maintaining steady state gate voltages below the dielectric breakdown level are included.In a still further aspect of the present invention a bridge circuit couples a first power supply node to a second power supply node, where the second power supply node is coupled to an ESD protection circuit.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: May 25, 1999
    Assignee: Intel Corporation
    Inventors: Timothy J. Maloney, Travis M. Eiles
  • Patent number: 5903421
    Abstract: A high-frequency composite part includes a high-frequency switch and an amplifier in a transmission circuit side among high-frequency parts constituting a PHS portable telephone. In the telephone, the high-frequency switch is used for switching between the connection of the transmission circuit Tx and an antenna, and the connection of a receiving circuit Rx and the antenna. The amplifier at the Tx side amplifies a signal to be transmitted which has been converted into an RF signal and passes through a filter at the Tx side, and sends it to the high-frequency switch.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: May 11, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koji Furutani, Norio Nakajima, Hidefumi Suzaki
  • Patent number: 5898844
    Abstract: A hot-plug circuit for receiving a high-current load is disclosed. In accordance with a preferred embodiment of the present invention, the hot-plug circuit comprises a transistor, a capacitor, a resistor, and a control circuit module. The transistor is coupled between a power supply and an input that is adapted to receive the high-power adaptor card. The capacitor is coupled between a first terminal and a second terminal of the transistor. The resistor is coupled to the first terminal of the transistor. Finally, the control circuit module is for applying a first bias voltage to the second terminal of the transistor via the resistor in order to turn the transistor off during an absence of the high-current load, and for applying a second bias voltage to the second terminal of the transistor via the resistor in order to turn the transistor on under a linear conduction mode upon an initial contact of said high-current load to the input.
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: April 27, 1999
    Assignee: International Business Machines Corporation
    Inventor: Guy Alan Thompson
  • Patent number: 5896264
    Abstract: A current-limiting device comprises at least one polymer-based electrically conducting body with two contact surfaces and at least two electrodes. Close to a first one of the two contact surfaces of the polymer-based electrically conducting body, a surface layer is arranged. The resistivity of the surface layer is reduced relative to the resistivity of the bulk of the polymer body, and at the same time at least the second contact surface of the body is adapted to make free contact with at least one of the electrodes or other electrically conducting body.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: April 20, 1999
    Assignee: ABB Research Ltd.
    Inventors: Maria Bijlenga, Lars Banghammar, Tomas Hansson, Ola Jeppsson
  • Patent number: 5892644
    Abstract: A passive current limiting device and isolator is particularly adapted for use at high power levels for limiting excessive currents in a circuit in a fault condition such as an electrical short. The current limiting device comprises a magnetic core wound with two magnetically opposed, parallel connected coils of copper, a high temperature superconductor or other electrically conducting material, and a fault element connected in series with one of the coils. Under normal operating conditions, the magnetic flux density produced by the two coils cancel each other. Under a fault condition, the fault element is triggered to cause an imbalance in the magnetic flux density between the two coils which results in an increase in the impedance in the coils. While the fault element may be a separate current limiter, switch, fuse, bimetal strip or the like, it preferably is a superconductor current limiter conducting one-half of the current load compared to the same limiter wired to carry the total current of the circuit.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: April 6, 1999
    Assignee: The University of Chicago
    Inventors: Daniel J. Evans, Yung S. Cha
  • Patent number: 5886431
    Abstract: This apparatus and method controls and limits the flow of in-rush current to a peripheral device coupled to a main power supply unit through a power bus and a ground bus. The apparatus and method essentially isolate and limit in-rush current flow to a capacitive load until operational current flow occurs to the peripheral device. A switching device is coupled to the power bus and the ground bus through a load. A resistive device is coupled to the power bus and the ground bus through the load. A control circuit is connected to the switching device. During initial start-up or "hot plugging" of the device, the control circuit turns "off" the switching device causing the load to be charged from the power bus through the resistive device until a predetermined condition occurs whereupon the switching circuit is turned "on" to bypass the resistive device and connect the load and the peripheral device to the power bus.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: March 23, 1999
    Assignee: International Business Machines Corporation
    Inventor: Jeffrey Paul Rutigliano
  • Patent number: 5883774
    Abstract: A current limiter used for stable control of an electric power system, and particularly applied to a high voltage of the electric power system, has a reduced voltage for suppressing the overcurrent of the electric power system. The current limiter is not enlarged so that the current limiter secures the insulation of the voltage withstanding level, and the current limiter is easy to be introduced to the system. A limiting device is inserted between a low potential terminal of a winding of a star-connection of a three-phase transformer that has at least one winding of the star-connection and a ground point.
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: March 16, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Junzo Kida, Hiroshi Arita
  • Patent number: 5883578
    Abstract: The positive sequence voltage on the power line is measured at a given time, i.e. the present time, and also for one cycle earlier, and the ratio thereof is then compared against a threshold value of 0.9. There are four other supervisory tests which also must be true for a loss of potential condition to be indicated. These include determination of change in positive sequence current and angle and zero sequence current and angle. If the change in those values is smaller than selected thresholds, then a loss of potential condition is indicated.
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: March 16, 1999
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: Jeffrey B. Roberts, Daging Hou
  • Patent number: 5880917
    Abstract: A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.
    Type: Grant
    Filed: August 4, 1997
    Date of Patent: March 9, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Stephen L. Casper, Manny K. F. Ma, Joseph C. Sher
  • Patent number: 5869873
    Abstract: An electrostatic discharge protection circuit protects an internal circuit that is coupled to a pad from electrostatic discharge damage. The electrostatic discharge protection circuit comprises a PNP transistor, a NPN transistor, and an erasable programmable read only memory. The PNP and NPN transistors have an emitter, a base, and a collector, respectively. The PNP transistor is configured with its emitter connected to the pad, its base connected to the collector of the NPN transistor, and its collector connected to the base of the NPN transistor. The emitter of the NPN transistor is connected to a circuit node. The erasable programmable read only memory is configured with a drain connected to the base of the PNP transistor, a source connected to the circuit node, and a control gate coupled to the circuit node. When electrostatic discharge stress occurs at the pad, the erasable programmable read only memory enters breakdown to be programmed and triggers the conduction of the transistors.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: February 9, 1999
    Assignee: Winbond Electronics Corp.
    Inventor: Ta-Lee Yu
  • Patent number: 5867358
    Abstract: A fault-current-limiting circuit for a poly-phase circuit of the type including a plurality of inductive windings each of which has a first terminal connected to a common point and at least one of the windings having a second terminal connected to an electrical load is disclosed. The fault-current-limiting circuit has a first electrical path between the common point and ground which includes a current-limiting device having a first state whereat current passes through the device and a second state whereat current through the device is limited and wherein the device switches from the first state to the second state when current through the device exceeds a predetermined maximum and a second electrical path between the common point and ground having an electrical resistance significantly greater than a resistance of the first path when a device is in its first state.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: February 2, 1999
    Assignee: IPC Resistors, Inc.
    Inventor: John S. Campbell
  • Patent number: 5847429
    Abstract: An ESD protection device is provided which reduces the layout area required, utilizing multiple-node configurations and multiple node electrical couplings.
    Type: Grant
    Filed: July 31, 1996
    Date of Patent: December 8, 1998
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, Paul Y. M. Shy
  • Patent number: 5847915
    Abstract: Static isolator for the DC supply circuit of a load (MO) in the event of a surge, consisting of a dipole intended to be inserted into the power circuit of the load and comprising means for detecting a surge (R1, R2, T3, CI), means for filtering and storing the supply voltage (C, R1), means for cutting off the supply to the load (T3, R2, R8, R9, T4, T1, R7, R4), means for detecting the disappearance of the supply voltage (C, R1, R3, R6, T6) and means for erasing the storage means (R2, R6, T3, T6).
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: December 8, 1998
    Assignee: Somfy
    Inventor: Alain Tranchand
  • Patent number: 5844760
    Abstract: An insulated-gate controlled semiconductor device includes a main circuit that is controlled by an insulated gate having a gate resistor, an overload detector having the insulated gate for use in common with the main circuit, the overload detector being of the same construction as that of the main circuit, a current detector for detecting current passing through the overload detector, and a field effect transistor having a gate which responds to the voltage drop across the current detector. The main circuit is protected by lowering the voltage applied to the insulated gate through the gate resistor and through the low on-resistance of the field effect transistor while the field effect transistor is held on.
    Type: Grant
    Filed: January 7, 1993
    Date of Patent: December 1, 1998
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Naoki Kumagai, Katsunori Ueno
  • Patent number: 5835534
    Abstract: In a field bus system for performing communication between at least one field device and at least one higher-rank apparatus which are connected on a field bus transmission line constituted by a pair of transmission lines, an intrinsically safe barrier disposed between a hazardous area and a safe area on the transmission line in order to limit energy to be used in the hazardous area, the intrinsically safe barrier comprising impedance converting circuits provided in the barrier for reducing impedance in a frequency band of communication data.
    Type: Grant
    Filed: August 20, 1996
    Date of Patent: November 10, 1998
    Assignee: Hitachi, Ltd.
    Inventor: Makoto Kogure
  • Patent number: 5835327
    Abstract: An electro-static discharge (ESD) protection continuous monitoring device includes two or more resistance comparison circuits which compare the grounding resistances to earth ground of two or more electrical nodes to a maximum acceptable ESD protection resistance mandated by the ESD protection specification. An ESD protection failure indicator is driven by a logic circuit coupled to the resistance comparison circuits and activates when one or more of the resistance comparison circuits detects that the grounding resistance is greater than the maximum acceptable ESD protection resistance. The ESD protection continuous monitoring device includes a reference resistor which represents the maximum acceptable ESD protection resistance for any given monitored node. A reference resistor failure indicator notifies the operator that the reference resistor is faulty.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: November 10, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Adriel Siew, Lee Seah Doo
  • Patent number: 5828078
    Abstract: The present invention presents an electrostatic discharge and power surge protected circuit board (10) and method for providing an electrostatic discharge and power surge protected circuit board. The protected circuit board (10) includes temperature sensitive conducting material (14) and semiconductor circuit components (12). The temperature sensitive conducting material (14) has a critical current density, provides a high impedance when the critical current density is exceeded, and preferably comprises a high temperature superconductor. Preferably, the temperature sensitive conducting material (14) and the semiconductor circuit components (12) are coupled in series. In a method aspect of the present invention, an electrostatic discharge protected circuit board (10) is provided by providing a current carrying mechanism (16) on the circuit board (10), and coupling the current carrying mechanism (16) to temperature sensitive conducting material (14).
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: October 27, 1998
    Assignee: Hughes Electronics
    Inventor: Nicholas A. Doudoumopoulos
  • Patent number: 5818672
    Abstract: Apparatus and process are provided for suppressing interference caused by ground loop currents associated with two A.C. power-line operated electrical/electronic equipment units, such as an audio source and an amplifier, where typically the ground loop includes a shielded signal cable interconnecting the two equipment units. A signal representing current sensed from a selected region of the ground loop is amplified and injected into a second region of the ground loop as a counteractive current having polarity opposite that of the original ground loop current, thus tending to nullify the interference. The amplification may be made adjustable for optimal suppression. Ground loop current may be sensed by a sensing transformer coupled to the loop or by a pair of sense lines, connected to selected nodes in the ground loop such as respective ground terminals of the two equipment units, and providing the sensed signal to differential amplifier inputs.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: October 6, 1998
    Inventor: Thomas C. Hilbe
  • Patent number: 5818669
    Abstract: A circuit that utilizes a Zener diode to protect elements of a circuit from an over-voltage condition. When a fault occurs, causing an over-voltage condition, the voltage applied to the elements of the circuit is limited by the Zener diode. In addition, the circuit senses the over-voltage condition. Upon sensing the over-voltage condition, the circuit gradually reduces the power applied to that portion of the circuit to a minimum level. If the over-voltage condition persists for a predetermined amount of time, power is shut down to that portion of the circuit until the circuit is re-started. Because the amount of time that an over-voltage condition may occur is limited, the Zener diode may have a lower power rating than would otherwise be required. This is because the power dissipation capabilities of a Zener diode conducting current under a reverse bias are greater when the reverse bias is of a short duration than when the reverse bias is of a long duration.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: October 6, 1998
    Assignee: Micro Linear Corporation
    Inventor: Urs H. Mader
  • Patent number: 5815353
    Abstract: An overvoltage arrester (8) consists of a plurality of limiter elements (15) connected in series. Parallel to this series of limiter elements (15) is a series of controlled switches (18). The two circuits interconnect ladder-style by means of cross links (23), so that individual limiter elements (15) can be tested by closing the switches (18). The limiter elements (15) are dimensioned so that each limiter element (15) has a breakdown or forward voltage which is less than the lowest operating voltage to be expected at the overvoltage line (8).
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: September 29, 1998
    Assignee: Pilz GmbH & Co.
    Inventor: Hans Dieter Schwenkel
  • Patent number: 5815356
    Abstract: Transient protection apparatus and circuitry that allows a circuit being protected to operate during the transient and after the transient. Two types are included, one being a blocking type for use in severe conditions when little is known about the source of the transients and protection must be provided, and the other being a shunt suppresser type for use where the impedance of the transient or other parameters known about the transient allows such use. For the blocking type, when a transient voltage is detected, a series component (Q-1) decouples prevents the transient from reaching the circuit being protected. A charge pump (A-1) is provided that powers the circuit being protected during the duration of the transient. A shunt suppressor type provides a zener threshold (Z1) detector with a power boost provided by a MOSFET or IGBT (Q-30.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: September 29, 1998
    Assignee: Power Micro, Inc.
    Inventors: Edward T. Rodriguez, Gary R. Fuchs
  • Patent number: 5812352
    Abstract: Apparatus and method for opening circuit breakers in a circuit are disclosed. The apparatus includes input terminals adapted to be connected to the circuit, a switch and a load. When the apparatus is connected to the circuit and the switch is closed, a current is created in the circuit which overloads the circuit breaker. The apparatus also includes a fuse to protect the device and a LED to indicate when the device is in use. The apparatus can also include multiple loads to be able to create the overload in different circuits.
    Type: Grant
    Filed: June 26, 1996
    Date of Patent: September 22, 1998
    Assignee: Rokey Corporation
    Inventors: Stephen R. Rokita, John J. Davis
  • Patent number: 5812353
    Abstract: A current limiter arrangement particularly adapted to be positioned at a substation of an electrical power system for limiting the fault current for a predetermined period of time to permit protective devices positioned downstream in the network to clear the fault. If the fault is not cleared and the fault persists for a predetermined period of time the current limiting arrangement acts as a circuit breaker to open the load circuit. The arrangement includes an SCR bridge having a superconducting coil connected across two nodes. A novel gate pulse firing circuit generates two pulses per ac cycle for application to the gates of the SCR's of the bridge at 90.degree. and 270.degree. of each 360.degree. cycle and is ON at all times to provide for prompt dc charging of the super conducting coil with no ac load current and non-fault conduction of ac current at less than the maximum current limit.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: September 22, 1998
    Assignee: Lockheed Martin Corporation
    Inventors: Gary W. Albert, Kenneth B. Muehleman
  • Patent number: 5808538
    Abstract: An electrical apparatus comprising first and second PTC elements composed of a polymer composition with conductive particles dispersed therein, an insulating body, and first and second conductive terminals. Flexible conductive members having a first end that can be electrically connected to a source of electrical power and a second end that is adapted to receive and make electrical contact with the apparatus are provided. The PTC element and the insulating body are positioned between the first and second conductive terminals so that when the apparatus is inserted between the flexible conductive members, the members exert a pressure on the insulating body.
    Type: Grant
    Filed: June 19, 1996
    Date of Patent: September 15, 1998
    Assignee: Littelfuse, Inc.
    Inventor: Thinh Nguyen
  • Patent number: 5796568
    Abstract: A reversible short circuit current limiter which has at least one PTC thermistor connected in parallel with a shunt impedance branch, and is connected in series with at least one capacitor or a capacitor bank of the DC intermediate circuit. The short circuit current limiter may be arranged in the DC intermediate circuit or in the current convertor. A diode may be connected in the reverse-bias direction of a short circuit path in parallel with the PTC thermistor. The shunt impedance branch has a varistor connected in series with an ohmic resistor or a PTC thermistor and, if appropriate, an inductor. Structures of metal-based nonblocking PTC thermistors are specified.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: August 18, 1998
    Assignee: Asea Brown Boveri AG
    Inventor: Tudor Baiatu
  • Patent number: 5796567
    Abstract: A semiconductor electronic circuit with a protection device against supply voltage overloading, being of the type which comprises a first power circuit portion connected to a power supply line and enabled through at least a first transistor.This transistor has a control terminal driven by a voltage sensor connected to the power supply line. The semiconductor electronic circuit is characterized, moreover, in that it comprises a second signal circuit portion connected to the power supply line in a structurally independent manner of the first power circuit portion and through a controlled switch.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: August 18, 1998
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Edoardo Botti, Tiziana Mandrini
  • Patent number: 5793589
    Abstract: Circuit arrangement for current limiting, which contains, in a series path, the source-drain path of a field-effect transistor (12) and a current sensor (8) connected in series therewith. In order to achieve effective protection against momentary overcurrents, the rate of rise of the current is limited with the aid of an inductor (9) contained in the current sensor (8). A diode (11) acting as a freewheeling diode is arranged in parallel with the current sensor (8). The circuit arrangement can advantageously be used in apparatuses for supplying power to electrical telecommunications equipment.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: August 11, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventor: Karl Friedl
  • Patent number: 5786972
    Abstract: A voltage clamp for protecting a load from transients in a supply line comprising pass transistors coupled to a bias circuit path. The bias circuit path determines the clamp turn-on voltage of the voltage clamp and comprises transistors configured as zener diodes and transistors configured as forward biased pn junctions. The pass transistors are coupled to the bias path so as to conduct current from the supply line to ground when the voltage drop across the bias circuit path reaches the clamp turn-on voltage. The collector-to-emitter voltage drops of the pass transistors during current conduction are equal to one another and sum up to the clamp turn-on voltage, and therefore, the pass transistors advantageously share equally the clamp turn-on voltage drop across their collector-to-emitter junctions. The bias circuit path is temperature compensated so that the clamp turn-on voltage is substantially independent of temperature.
    Type: Grant
    Filed: June 7, 1996
    Date of Patent: July 28, 1998
    Assignee: Cherry Semiconductor Corporation
    Inventors: Denis P. Galipeau, Jon A. Rhan
  • Patent number: 5784236
    Abstract: The invention provides a circuit to protect an AC motor powered by a Variable Frequency Drive (VFD) from overvoltages caused by reflected waves. A full wave bridge rectifier circuit across the lines of the motor to be protected provides rectified voltage output to a capacitor, across which a low resistance discharge resistor in series with one or more zener diodes is attached. When an overvoltage above the clamping voltage of the zener diode(s) occurs across the protected lines, the zener diode(s) will conduct, causing the excess charge across the capacitor to discharge through the resistor until the voltage drops below the clamping voltage of the diode(s).
    Type: Grant
    Filed: May 22, 1997
    Date of Patent: July 21, 1998
    Assignee: Tycor International Corp.
    Inventors: Dale Tardiff, James Funke
  • Patent number: 5781386
    Abstract: The present invention relates to suppressing transient impulses in a power distribution system and more particularly to a device and method for suppressing transient impulses at frequencies which exceed the power frequencies while maintaining an acceptable "safety" impedance level at the power frequencies.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: July 14, 1998
    Assignee: Powervar, Inc.
    Inventor: Norman F. Muelleman
  • Patent number: 5774321
    Abstract: A power supply circuit interrupts power to a load in response to a short-circuit or an open-circuit condition and automatically restores power after a momentary short-circuit. A short-circuit detector monitors the current flowing through the load and generates a short-circuit signal if the current exceeds a predetermined level. An open-circuit detector monitors the load voltage and generates an open-circuit signal if the voltage exceeds a predetermined level. A latch converts the short-circuit signal to a latch signal. A logic unit combines the latch signal with the open-circuit signal and a pulse signal from a pulse generator to generate a drive signal. A driver uses the drive signal to control a switch which is connected between the power source and the load to interrupt power to the load. During a short-circuit, a timer generates a periodic pulse signal that toggles the latch signal and intermittently restarts the power to the load. If the short-circuit was of short duration, power is restored to the load.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: June 30, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Ho Kim, Young-Sik Lee
  • Patent number: 5771140
    Abstract: An improved electro-static discharge and latch-up prevention circuit capable of preventing circuit malfunctions caused by an electro-static discharge and permitting an integrated circuit, in which a bias condition is stable, to perform a signal input/output operation by applying an electro-static having a certain level having a limited range to the integrated circuit, which includes an electro-static discharge prevention unit provided in the interior of or at the outside of an integrated circuit and connected between a positive voltage and a negative voltage in series for preventing positive and negative electro-static discharges; a switching unit connected between the electro-static discharge prevention unit and the interior circuit of the integrated circuit chip for switching; and a control unit for outputting a control signal so as to control a switching operation of the switching unit.
    Type: Grant
    Filed: March 28, 1996
    Date of Patent: June 23, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventor: Dae Seong Kim
  • Patent number: 5764470
    Abstract: A rush current suppression circuit suppresses a peak value of a rush current flowing into a heater. The rush current suppression circuit includes a parallel circuit formed by a positive-characteristic thermistor and a negative-characteristic thermistor. The negative-characteristic thermistor has a resistance at a normal temperature higher than that of the positive-characteristics thermistor. The parallel circuit is connected in series to the heater.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: June 9, 1998
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenjiro Mihara, Hideaki Niimi, Yuichi Takaoka
  • Patent number: 5764926
    Abstract: A circuit unit to be inserted or removed by live wire work into or from a system having a plurality of circuit units and a power source to supply power to the plurality of circuit units includes a first circuit to supply power to the circuit unit from the power source when the circuit unit is inserted into the system; and a second circuit to supply power to the circuit unit in normal operation after the circuit unit is inserted into the system. The first circuit nearly stops supplying power about the time when the second circuit starts supplying power and by this arrangement, it becomes possible to vary the timing of inrush currents attending on a supply of power from a plurality of power sources. A removal permission indicator can be installed which can be turned on by a voltage supplied from the power source under a condition that permission to remove the unit has been issued.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: June 9, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Kimio Fukuda, Kazuo Morita
  • Patent number: 5761020
    Abstract: In a power integrated device having temperature monitoring circuits powered from input signal pulses, an overtemperature signal is memorized in a small capacitor (30 picofarads) to guarantee that the overtemperature signal will not be lost between two input pulses at a frequency greater than about 16 kHz. A larger charge storage capacitor (100 picofarads) is also added to store the input voltage V.sub.cc needed to power the overtemperature circuits.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: June 2, 1998
    Assignee: International Rectifier Corporation
    Inventor: Bruno C. Nadd
  • Patent number: 5761019
    Abstract: A medical current limiter protects medical electrodes and associated diagnostic apparatus from overcurrents. The medical current limiter includes first and second external terminal connections and first and second cascade circuits, each formed of a pair of n-channel field effect transistors and a p-channel field effect transistor consecutively connected in series between one of the first and second external terminals and a low value resistor. The p-channel field effect transistor and one of the n-channel field effect transistors connected thereto in each cascade circuit have a pinch-off voltage of less than 0.7 volts.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: June 2, 1998
    Assignee: L.Vad Technology, Inc.
    Inventor: Mark W. Kroll
  • Patent number: 5757597
    Abstract: A Ground Fault Interrupter ("GFI") combined with a plug-receiving receptacle is mounted in combination with a weathertight container. The container is additionally configured with a weathertight opening through which, a three prong male end of a pigtail from a remote power source is electrically connected to a GFI-protected receptacle. A weathertight lid covering for the container and weathertight rain shield for the container openings assures that the combination is functional during field use or for final storage for user transport of tools and other electrical apparatus. The device is optionally configured with a removable, storable, pedestal pole-mounted light assembly having GFI-protected wiring on the interior of the light pole which may be assembled in combination with the container.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: May 26, 1998
    Inventor: William D. Frank, Sr.
  • Patent number: 5754797
    Abstract: An interface between a main computer 20 and a peripheral unit 30 allows connection/disconnection of the peripheral unit to and from the main computer during the operation of the main computer, while achieving reduction of fluctuation in the source voltage caused by hot line connection/disconnection, as well as a reduction of the circuit size. The interface includes a connector having long terminal pairs and short terminal pairs, by which the peripheral unit 30 is connected to the main computer 20. The peripheral unit 30 contains a delay circuit comprised of a FET 10 for controlling ON/OFF operation of the electric current path, a capacitor C1, and resistors R1 and R2. The signal path containing R1 and R2 forms a closed loop only when the peripheral unit is completely inserted into the main computer. During the insertion, the long terminal pairs are first connected, which is followed by connection of the short terminal pair.
    Type: Grant
    Filed: February 7, 1996
    Date of Patent: May 19, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akira Takahashi
  • Patent number: 5751534
    Abstract: The invention is a surge protector which can provide voltage and current protection in coaxial cable systems. The protector includes a central conductor which is coupled in series with a variable resistance, and a voltage surge arrestor which is coupled between the conductor and the housing of the protector. A capacitor may also be coupled in parallel with the resistor. The protector provides both an ac and dc signal path.
    Type: Grant
    Filed: May 29, 1996
    Date of Patent: May 12, 1998
    Assignee: Lucent Technologies Inc.
    Inventor: George Andrew DeBalko
  • Patent number: 5748426
    Abstract: A circuit card is interfaced to a powered electrical bus by applying power to the circuit card before it interfaces to the electrical bus or by removing power from the circuit card after it has been removed from the bus. This is accomplished using a power cord that connects the equipment's power supply to a mating connector on the card to be inserted or removed. Attaching the power cord to the mating connector of the card disables the output drivers that provide output signals to the equipment's communication bus and places the card in a reset state. This prevents introducing error signals onto the communication bus. Additionally, the contacts on the edge connector are sequenced to prevent applying power to the circuit card before a ground is available. Additionally, the power cord and circuit card are keyed to prevent improper insertion and the power card includes an inductor to provide surge protection.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: May 5, 1998
    Assignee: Paradyne Corporation
    Inventors: John Bedingfield, Michael A. Hicks
  • Patent number: 5745328
    Abstract: An electrical impulse suppressor comprising a band pass filter formed with strip transmission lines adapted to attenuate the flow of energy therethrough above and below a band limited range of frequencies. The suppressor used the impedance of a discharge means connected to a strip transmission live element to form the first of two resonant circuits used in the construction of the band pass filter.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: April 28, 1998
    Assignee: Watkins-Johnson Company
    Inventor: John V. Bellantoni
  • Patent number: 5745327
    Abstract: A circuit that protects electronic components from damage caused by current and voltage surges generated on signal or data transmission lines when an electrically energized host device is connected to or disconnected from a peripheral device. The circuit uses transistor elements to switch off or interrupt the signal or data transmission line thus protecting circuit elements from damage. The protective circuit is enabled automatically whenever the connection of ground pins between the peripheral and the host fails to be established, as opposed to enabling the protective circuit when a voltage surge or a current surge is detected by a circuit element. When the ground pins between peripheral and host are finally connected, the circuit automatically responds by allowing data and signals to be transmitted between the host and the peripheral.
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: April 28, 1998
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Youn-Chul Choo
  • Patent number: 5742463
    Abstract: A device which may protect circuits or equipment from overload or transients is disclosed. The device includes a unit consisting of a p-channel FET and an n-channel FET connected with their conductive channels in series and the gate of each transistor coupled to the drain terminal of the other.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: April 21, 1998
    Assignee: The University of Queensland
    Inventor: Richard Allen Harris
  • Patent number: 5737161
    Abstract: Overcurrent protection arrangements including a relay comprising two coils wound on a common magnetic core and a PTC device coupled in parallel with the relay contacts. The arrangement comprises a circuit interruption element which has a normal state which permits the flow of a normal circuit current, I.sub.NORMAL, to pass through the system, and a fault state which permits the flow of at most a reduced current, I.sub.REDUCED, substantially less than I.sub.NORMAL. A first control element is coupled in series between the power supply and the load, and is functionally linked to the circuit interruption element so that when the current through the first control element increases from I.sub.NORMAL to a relatively high current, I.sub.FAULT, the first control element can convert the circuit interruption element into the fault state.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: April 7, 1998
    Assignee: Raychem Corporation
    Inventor: Brian Thomas
  • Patent number: 5737165
    Abstract: Apparatus for replacing conventional fault isolation resistors includes a terminal coupled to one winding of a transformer whose other winding is coupled across the two-line databus. Enhancement-mode-field-effect transistors have their source and drain electrodes each coupled between one end of the other winding and one of the databus lines and their control electrodes coupled at spaced intervals along the other winding. The winding voltage is zero when a terminal is not transmitting, turning off the field-effect transistors, presenting an open circuit. The parasitic body diodes of the transistors are connected in series and are poled to oppose each other to prevent conduction of signals from the databus. Thus, signals on the databus are not loaded by the terminal's output impedance. When winding voltage exceeds a threshold, one transistor conducts, providing substantially a short-circuit. The parasitic body diode of the remaining transistor also conducts.
    Type: Grant
    Filed: February 8, 1996
    Date of Patent: April 7, 1998
    Assignee: ILC Data Device Corporation
    Inventor: Barry E. Becker
  • Patent number: 5737160
    Abstract: An electrical switch arrangement, comprising a first mechanical switch, a second mechanical switch and a PTC device, with (a) the PTC device and second switch connected in parallel and the parallel combination connected in series with the first switch, or (b) the PTC device and first switch connected in series and the series combination connected in parallel with the second switch. The arrangement can interrupt a current and voltage higher than the rated currents and voltages of each of the switches and the PTC devices. The parallel switch can be rated to interrupt the rated interrupt current of the electrical switch arrangement at a voltage below the rated voltage of the electrical switch arrangement, and the series switch can be rated to interrupt a current below the rated interrupt current of the electrical switch arrangement at the rated voltage of the electrical switch arrangement.
    Type: Grant
    Filed: November 29, 1995
    Date of Patent: April 7, 1998
    Assignee: Raychem Corporation
    Inventor: Hugh Duffy
  • Patent number: 5729418
    Abstract: A high voltage current limiting protection circuit for measurement equipment and measurement probes. The circuit is comprised of a plurality of elements one of which is variable resistance means which are coupled between a first terminal and a second terminal of the circuit for generating a low resistance level to allow a fast response by the measurement equipment to measure current flowing between the two terminals. The variable resistance means generates a high resistance level to limit current flow to a minimum level between the two terminals when a predetermined maximum voltage level across the two terminals is exceeded. Voltage trip point means are coupled to the variable resistance means for setting the predetermined maximum voltage level to trigger the variable resistance means to generate the high resistance level to limit current flow between the two terminals to the minimum level.
    Type: Grant
    Filed: August 29, 1996
    Date of Patent: March 17, 1998
    Assignee: Supertex, Inc.
    Inventor: Jimes Lei
  • Patent number: 5729062
    Abstract: In an active plug-in circuit, a mode setting section sets either a plug-in mode or a regular mode, depending on the power source voltage of a package. When the plug-in mode is set, a power consumption controller maintains an electronic circuit built in the package in a low power consumption mode. After the power source voltage of the electronic circuit has been stabilized, the mode setting section sets the regular mode. The circuit reduces the variation of power source current to occur when a power source pin mounted on a package connector is connected to the corresponding terminal of a mother board connector and on the transition from the plug-in mode to the regular mode.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: March 17, 1998
    Assignee: NEC Corporation
    Inventor: Shunji Satoh
  • Patent number: 5726848
    Abstract: A solid-state circuit breaker and current limiter for a load served by an alternating current source having a source impedance, the solid-state circuit breaker and current limiter comprising a thyristor bridge interposed between the alternating current source and the load, the thyristor bridge having four thyristor legs and four nodes, with a first node connected to the alternating current source, and a second node connected to the load. A coil is connected from a third node to a fourth node, the coil having an impedance of a value calculated to limit the current flowing therethrough to a predetermined value.
    Type: Grant
    Filed: May 8, 1996
    Date of Patent: March 10, 1998
    Assignee: The Regents of the University of California
    Inventor: Heinrich J. Boenig