Abstract: The reader/writer of this invention includes a high voltage withstanding amplifier, plural resonance circuits and plural high voltage withstanding analog switching circuits. The high voltage withstanding amplifier amplifies an analog signal to be sent to the outside. Each of the resonance circuits sends the analog signal amplified by the high voltage withstanding amplifier to the outside. The high voltage withstanding analog switching circuits are provided between the high voltage withstanding amplifier and the resonance circuits correspondingly to the resonance circuits. Each of the high voltage withstanding analog switching circuits electrically connects/disconnects the high voltage withstanding amplifier to/from the corresponding resonance circuit. Since the reader/writer includes the high voltage withstanding analog switching circuits, there is no need to provide high voltage withstanding amplifiers at the previous stages of the resonance circuits as in a conventional reader/writer.

Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.

Abstract: An electrostatic discharge (ESD) protection circuit which includes an Insulated Gate Bipolar Transistor (IGBT), a collector clamp, and a resistor. The IGBT collector is coupled with a circuit pad, and the emitter is coupled to ground. The collector clamp is coupled with the pad and the IGBT gate, and the resistor is coupled with the IGBT emitter and gate. When the voltage at the pad is below the trigger voltage of collector clamp, the collector clamp remains in a blocking state, thus preventing the IGBT from conducting. At the onset of an ESD event, when a voltage greater than the trigger voltage of the collector clamp appears at the pad, the collector clamp conducts, causing current flow through the resistor, thus turning on the IGBT and latching a parasitic thyristor formed in the IGBT until the ESD charge is dissipated.

Abstract: An integrated circuit including an output pad, an output block coupled to the output pad via a capacitor, a first one-way conduction element for connecting the pad to a supply line when the voltage on the pad exceeds the voltage of the supply line by a first threshold voltage, a second one-way conduction element for connecting the pad to the circuit ground when the voltage on the pad is smaller than the ground voltage by a second threshold voltage, a resistor coupled on the one hand to the output pad and on the other hand to the supply line via a switch which is turned off when the circuit is idle and which is turned on when the circuit is in a normal operating mode.

Abstract: An improved probe includes a conductive tubular housing or body containing a coil spring and a conductive plunger movable in the housing and having a contact tip outwardly extending from one end of the housing. The plunger and tip are urged to a normally outward position by the bias force of the spring. The opposite end of the housing has an opening for mating with a conductive pin of a connector. The connector is retained in a mounting plate of an associated fixture and has terminal ends of desired configuration. The terminal end may include a wire-wrap pin, a crimp type terminal or wire jack for attachment to a wire, or the terminal may include a spring loaded pin for engagement with an associated electrical contact. An air tight seal may be provided between the probe and the connector and the connector may be mounted in a mounting such that when vacuum is applied to an associated test fixture, air cannot be drawn through the fixture or through the body of the probe.

Abstract: A power distribution panel having circuit elements such as KTK and GMT fuses removably mounted to a unit housing by means of module members, thereby allowing for ease of customization of the circuit elements of the power distribution panel.

Abstract: The present invention relates to a passive electronic component architecture employed in conjunction with various dielectric and combinations of dielectric materials to provide one or more differential and common mode filters for the suppression of electromagnetic emissions and surge protection. The architecture allows single or multiple components to be assembled within a single package such as an integrated circuit or connector. The component's architecture is dielectric independent and provides for integration of various electrical characteristics within a single component to perform the functions of filtering, decoupling, fusing and surge suppression, alone or in combination.

Abstract: The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10) comprising at least one input element (20) is protected by a protective circuit (40). The protective circuit (40) is operable to protect the integrated circuit (10) from damage due to electrostatic discharge and may be coupled to the input element (20). The protective circuit (40) comprises a lateral NPN transistor (T1) coupled to the input element (20) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (20). The protective circuit (40) also may comprise a lateral PNP transistor (T2) coupled to the input element (20) and to the lateral NPN transistor (T1). The lateral PNP transistor (T2) is operable to aid in raising a potential of the base of the lateral NPN transistor (T1).

Abstract: A rectifier assembly including a fusible cutout is configured as a polarity reversal protection device. The fusible cutout includes a semiconductor chip having a positive temperature coefficient so that when it overheats, it becomes unsoldered and interrupts the current flow.

Abstract: A miniaturized cost-saving intermittent short circuit determining device located between a power source and an electric load in a vehicle electric circuit. The determining device includes detecting means for detecting current flowing through the electric circuit, determining means for determining whether the current detected by the detecting means is an intermittent short circuit, and disconnecting means for disconnecting the electric circuit when the determining means judges that there is an abnormality. The determining means is connected to an external switch circuit, which selectively supplies and stops current to the electric load of the electric circuit. The determining means determines whether the external switch circuit is switched on or off, and switches the disconnecting means on or off according to the determination.

Abstract: The present invention relates to an ultra-low power (ULP) MOS diode. The diode has a first and a second terminal. It comprises an n-MOS transistor having a channel, a first N+ doped diffusion region at one extremity of the channel and a second N+ diffusion region at the other extremity of the channel, and a p-MOS transistor having a channel and a first P+ doped diffusion region at one extremity of the channel and a second P+ diffusion region at the other extremity of the channel. The first N+ diffusion region of the n-MOS transistor is coupled to the first P+ diffusion region of the p-MOS transistor, the gate of the n-MOS transistor is coupled to the second P+ diffusion region of the p-MOS transistor, and the gate of the p-MOS transistor is coupled to the second N+ diffusion region of the n-MOS transistor.

Abstract: Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.

Abstract: An inrush current limiter circuit (20) includes a mirrored transistor (50) responsive to a control signal (VDRIVE) developed from a sense current (ISENSE), and has a first source (51) coupled to a supply voltage, a common drain (53) that routes a load current (ILOAD) to an output node (45), and a second source that samples the load current to produce the sense current. A fault protection circuit (64) disables the mirrored transistor in response to a first fault condition (TEMP, UVLO) and is coupled to a first lead (43) for externally adjusting a fault threshold. A fault communication circuit (250) is coupled to the first lead to receive a fault signal representative of an external fault condition to disable the mirrored transistor.

Abstract: Disclosed herein is an anisotropically conductive sheet capable of holding charge in its surfaces under an unpressurised state, and moving the charge held in the surface in a thickness-wise direction thereof in a state pressurised in the thickness-wise direction, thereby controlling the quantity of the charge at the surface. This anisotropically conductive sheet comprises a sheet base composed of an elastomer and conductive particles exhibiting magnetism contained in the sheet base in a state oriented so as to arrange in rows in a thickness-wise direction of the sheet base, and dispersed in a plane direction thereof. Supposing that a volume resistivity in the thickness-wise direction under an unpressurised state is R0, and a volume resistivity in the thickness-wise direction in a state pressurised under a pressure of 1 g/mm2 in the thickness-wise direction is R1, the volume resistivity R1 is 1×107 to 1×1012 ?·m, and a ratio (R0/R1) of the volume resistivity R0 to the volume resistivity R1 is 1×101 to 1×104.

Abstract: An inductor obtained by laminating a plurality of ceramic layers having an internal coil conductor, and a thermistor obtained by laminating a plurality of ceramic layers having internal electrodes and having a predetermined resistance-temperature characteristic are laminated via an intermediate insulating layer. Both ends of the internal coil conductor of the inductor and the internal electrodes of the thermistor are connected to a pair of external electrodes. Thus, the inductor and the thermistor are connected in parallel.

Abstract: A current limiter circuit for limiting current in an electrical circuit element such as the magneto-resistive portion of a read head forming a portion of a hard disk drive and including: a first circuit connected to one end of the circuit element for applying a bias current of a desired value to the circuit element in response to the value to an input signal; a second circuit connected to the other end of the circuit element for setting the amplitude of the voltage signal generated across the circuit element in response to the bias current; and a third electrical circuit connected to both the first and second circuits for limiting the value of bias current to a predetermined level for an abnormal event such as a current surge, a short circuit, or any other type of undesired current operating condition.

Abstract: A quarter wavelength transmission line is provided between a signal transmission line for transmitting a high frequency signal and a ground node. The quarter wavelength transmission line has a length equal to a quarter of an effective wavelength of an operation frequency of a semiconductor device. A surge absorbing element is connected between the quarter wavelength transmission line and an internal circuit. The signal transmission line is coupled to the internal circuit through a capacitor. A clamp circuit is provided between a power supply line and a ground line. The clamp circuit clamps the voltage difference between the power supply line and the ground line to a prescribed voltage level or less. A high frequency semiconductor device is thus implemented which is capable of preventing breakdown of an internal circuit element due to an electrostatic discharge phenomenon (ESD) without degrading high frequency characteristics.

Abstract: A power use circuit breaker includes an arc generating switching unit which adds an electrical resistance in a circuit during current interruption to attenuate a current to be interrupted, a vacuum bulb which is electrically connected in series with the arc generating switching unit and interrupts the attenuated current and a current conducting switching unit connected in parallel with the series circuit of the vacuum bulb and the arc generating switching unit. For current conduction the current conducting switching unit is closed after the vacuum bulb and the arc generating switching unit are closed, and for current interruption after opening the current conducting switching unit, the vacuum bulb and the arc generating switching unit are opened.

Abstract: Apparatus and systems, as well as methods for using them, may include launching a pulse into an input port of a quarter-wave directional coupler having an thru port and an isolated port, and receiving a leading edge of the pulse as a voltage spike at an output port of the coupler. A switch may be activated to couple a pulse source to the input port. The impedance of the coupler may be selected to match the resistance of the switch added to the impedance of a charge line included in the pulse source.

Abstract: Apparatus and methods for protecting devices such as micro-switches (100) and micro-relays from adverse effects of electrostatic discharge (ESD). A protection device is provided that includes a two terminal switch (102, 104) that can be actuated by an ESD event to protect an EDS-sensitive micro-switch or micro-relay from potential malfunction and/or damage. The two terminal switch is configured to close in less time than the micro-switch or micro-relay it is protecting, thereby disipating the energy associated with the ESD event without causing damage to the micro-relays which are provided with increased immunity to the adverse effects of ESD events. The micro-switch includes respective drain/gate terminal pairs at respective ends of the device. The micro-relay includes at least two drain terminals (106) and a gate terminal (102) at respective ends of the device.

Abstract: A semiconductor module is provided which includes a beat spreader, at least two semiconductors thermally coupled to the heat spreader, and a plurality of electrically conductive leads electrically connected to the semiconductors. At least one of the electrically conductive leads is common to both of the semiconductors The semiconductor module also includes a termination resistor electrically coupled to at least one of the semiconductors. A method of making a semiconductor module is also taught, whereby a plurality of electrically conductive leads are provided. At least two semiconductors are electrically coupled to the plurality of electrically conductive leads, where at least one of the electrically conductive leads is common to both of the semiconductors. The semiconductors are then thermally coupled to a heat spreader. Subsequently, a termination resistor is electrically coupled to at least one of the semiconductors.

Abstract: Methods of forming thermal ink jet resistor structures for use in nucleating ink are described. In one embodiment, the method comprises forming a layer of conductive material over a substrate, and patterning and etching the layer of conductive material effective to form one or more arrays of resistors. Individual arrays comprise multiple, parallel-connected resistor elements and the resistor elements are configured such that failure of any one resistor element will not render its associated resistor array inoperative for nucleating ink. The resistor elements of individual arrays are formed such that collectively, the resistor elements are not independently addressable. Other embodiments are described.

Abstract: The present invention relates to a device for intrinsically safe, redundant current-voltage supply for electric loads in an explosion-proof area. In a device according to the invention there are at least two supply circuits for making available the current/voltage supply and a protective device for intrinsically safe current and voltage limitation of the power supplied by the supply circuits to the load in the explosion-proof area. According to the invention, the device is characterized in that the supply circuits are connected in parallel to one another and that the protective device has at least one resistive current limiting device for intrinsic safety in parallel-active supply circuits.

Abstract: A string set of series-connected incandescent bulbs in which substantially all of the bulb filaments in the set are individually provided with a shunt circuit which includes a voltage responsive switch which is inoperative during normal operation of the string set when connected to a source of operating potential and which becomes operative only in response to an increase in the voltage thereacross which exceeds its rating, and in which the remaining bulbs of the circuit continue to receive substantially rated current therethrough and substantially rated voltage thereacross and further continue to be illuminated at substantially constant illumination even though other or substantially all of the other bulbs in the string are either inoperative or are missing from their respective sockets. If flasher bulbs are used in the string, they will twinkle off and on when the operating potential is applied.

Abstract: A method and circuitry for pre-conditioning an electrical signal. The method comprises limiting the strength of the signal to not exceed a limit signal strength corresponding to the onset of substantial non-linear response of an amplifier to which the limited signal is to be supplied for amplification.

Abstract: A method for isolating suites includes the steps of isolating the suites when an alarm is initiated, setting a timer during isolation creating a window of time to clear a short circuit, clearing said short circuit, removing isolation from the suites as the timer reaches completion, determining if there is a short circuit in each of the suites, and isolating suites that have a short circuit.

Abstract: The present invention provides a method and the apparatus thereof to protect MOS components from antenna effect. Via the bypass PMOS and NMOS transistors, charges with either polarity are conveyed and neutralized. The present invention thus protects the gate oxide layer of the MOS component in the IC circuit from damage or degradation.

Abstract: The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.

Abstract: An inductor operable under various supply voltages includes a first coil, a second coil, a bobbin and a core, wherein the coil diameter of the first coil is larger than the coil diameter of the second coil and the first and the second coils are connected in series, whereby input electric current flows through one coil selected from said first and second coils by utilizing a selecting switch, so as to generate sufficient corresponding inductance according to various input supply voltages.

Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.

Abstract: An input section of an RF interface is shown in conjunction with a tuner circuit. The input, in one embodiment, is constructed using co-planner wave guide techniques and serves to provide low return loss, low insertion loss, high voltage protection, all within a single housing without causing RF interference problems.

Abstract: One embodiment of the disclosures made herein is a network equipment protection module configured for being removably mounted on a network equipment protector block. In accordance with such a network equipment protection module, the network equipment protection module includes surge protection circuitry configured for providing surge protection functionality, AC coupling-DC blocking circuitry configured for providing AC coupling-DC blocking functionality and DC blocking circuitry configured for providing DC blocking functionality. The DC blocking circuitry enables the DC blocking functionality to be selectively activated and deactivated. In this manner, such a network equipment protection module enables the combination of surge protection, DSL signal transmission, full metallic loop testing (MLT) and bridging of a DC voltage to be facilitated in association with a twisted pair transmission line.

Abstract: Grounding elements are used to properly ground floor coverings and other elements whereby a floor covering, such as a carpet, need not be removed and reinstalled to correct a grounding problem. Properly grounded floor coverings and other devices reduces the effects of electrostatic discharge (ESD) and eliminates disruptive leak paths. One form of the invention has an element that is touched by a user layered on top of an ESD grounded work surface.

Abstract: Surge protector which includes a film pattern (2) formed on a suitable substrate (1) is characterized in that the film pattern (2) essentially consists of narrow lines (2a, 2b, 2c) which extend parallel and adjacent to each other and are electrically in parallel relationship to each other, and bridges (11-24) between the lines. Advantageously, there are three parallel lines. The resistance of the film pattern (2) is trimmed advantageously by cutting (T5, T6, T7, T8, T9, T10) one of the lines (2c) between successive bridges.

Abstract: An integrated circuit includes circuit nodes (111 and 131), a resistor (210) coupling together the nodes, a comparator (230) having two inputs and an output where a first one of the two inputs is coupled to the resistor and a first one of the nodes, and a three-terminal device (220) having a first terminal coupled to a second one of the nodes and the resistor and also having a second terminal coupled to the output of the comparator.

Abstract: The present invention provides diode bridge and a parallel type, capacitor based, phase to phase surge suppressor. The suppressor acts to suppress transient energy as soon as the spike exceeds the prevailing peak of the ac waveform. The system dissipates the spike by drawing current through the system impedance between the suppressor sand the source of the surge.

Abstract: Embodiments of the present invention provide methods and circuitry for protecting a circuit during hot-swap events. Hot swap protection circuitry includes as overcurrent detection circuit which decouples power from a load. Circuitry is provided to detect ground-fault conditions. Noise detection circuitry is provided to reduce noise in the power that is delivered to the load.

Abstract: A fused electrical disconnect device comprises a housing and line and load connectors extending from one side of the housing. A line buss is disposed within the housing and is electrically connected to the line connector. A load buss is also disposed within the housing and is electrically connected to the load connector. A fuse holding cartridge is removably insertable into the housing. The fuse holding cartridge includes a body and line and load terminal blades extending from one side of the body. The line terminal blade contacts the line buss and the load terminal blade contacts the load buss when the fuse holding cartridge is inserted into the housing. A load protection fuse is removably insertable between the line and load terminal blades to establish an electrical current path between the line and load terminal blades.

Abstract: A semiconductor circuit for multi-voltage operation having built-in electrostatic discharge (ESD) protection is described, comprising a drain extended nMOS transistor and a pnpn silicon controlled rectifier (SCR) merged with the transistor so that a dual npn structure is created and both the source of the transistor and the cathode of the SCR are connected to electrical ground potential, forming a dual cathode, whereby the ESD protection is enhanced. The rectifier has a diffusion region, forming an abrupt junction, resistively coupled to the drain, whereby the electrical breakdown-to-substrate of the SCR can be triggered prior to the breakdown of the nMOS transistor drain. The SCR has anode and cathode regions spaced apart by semiconductor surface regions and insulating layers positioned over the surface regions with a thickness suitable for high voltage operation and ESD protection.

Abstract: A high-impedance-insertion system suppresses load-produced electromagnetic noise from interfering into a power source by coupling the load to the power source through a switch. If the power source is an AC power source, the switch couples to the power source through a storage element and a rectifier, such that the switch is OFF (in the high impedance state) when the rectifier is reversed biased (or in a low impedance state). If the power source is a DC power source, the switch couples to the power source through a storage element and a second switch, such that the switch is OFF (in the high impedance state) when the second switch is ON (in the low impedance state).

Abstract: Compact and integral arrangements for an energy-conditioning arrangement having various predetermined energy pathways utilized in part for the purpose of conditioning energies of either one or multiple of circuitry. Some energy-conditioning arrangement variants can be operable to provide multiple, energy-conditioning operations.

Abstract: A power use circuit breaker includes an arc generating switching unit which adds an electrical resistance in a circuit during current interruption to attenuate a current to be interrupted, a vacuum bulb which is electrically connected in series with the arc generating switching unit and interrupts the attenuated current and a current conducting switching unit connected in parallel with the series circuit of the vacuum bulb and the arc generating switching unit. For current conduction the current conducting switching unit is closed after the vacuum bulb and the arc generating switching unit are closed, and for current interruption after opening the current conducting switching unit, the vacuum bulb and the arc generating switching unit are opened.

Abstract: Compact and integral arrangements for an energy-conditioning arrangement having various predetermined energy pathways utilized in part for the purpose of conditioning energies of either one or multiple of circuitry that would otherwise detrimentally effect a predetermined application having a single or multiple, circuitry systems. Some energy-conditioning arrangement variants can be operable to provide multiple energy-conditioning operations.

Abstract: An electrostatic discharge protection circuit is connected to a bonding pad and a pre-stage driver. The electrostatic discharge protection circuit includes a PMOS transistor and a NMOS transistor and both connect in series. A source/drain region of the PMOS transistor is connected to a system power source, and the gate electrode is connected to a pre-stage drive, and the other source/drain region is connected to a source/drain region of the NMOS transistor, which is also connected to the bonding pad. Another source/drain region of the NMOS transistor is ground. The gate electrode of the NMOS transistor receives an output of the pre-stage driver. Another PMOS transistor is connected to a capacitor and is also connected to the source/drain region of a system power source and the gate electrode of the NMOS transistor.

Abstract: The invention relates to an inrush current protection circuit for a power supply. The power supply includes a rectification circuit coupled to a main body of the power supply through an energy-storage capacitor. The main body of the power supply is provided with a reference voltage, and the setup time of the reference voltage is greater than a threshold value. The inrush current protection circuit includes a current limiting resistor coupled between a negative terminal of the rectification circuit and a ground terminal of the energy-storage capacitor for preventing the generation of an inrush current the instant that the power supply is powered on, and a switch coupled in parallel with the current limiting resistor and which is controlled by the reference voltage. When the reference voltage is set up, the switch switches from an open state to a short state, so as to bypass the current limiting resistor.

Abstract: A DC arc-suppressor for network appliance power managers comprises an electromechanical relay that controls the flow of battery power to a network appliance by remote control. The relay includes electrical contacts that open to interrupt the flow of current in response to an off-command signal. A transistor is connected in shunt across the relay contacts to temporarily divert such flow of current. A timing circuit is connected to respond to the off-command signal by first turning on the shunt transistor, then open the relay contacts, then turn off the shunt transistor. Such shunt transistor is sized to carry the full rated power of the relay contacts, but only for the few milliseconds that are needed to allow the relay contacts to fully separate.

Abstract: A communication interface circuit transfers signals between a TTL microcontroller and a RS232 device while avoiding level translation. The interface circuit includes two switch elements. A first switch element is connected between the TTL receive terminal and the ground supply. The second switch element includes a first node that is an electrical communication with the TTL transmit data terminal, the RS232 transmit data terminal and the RS232 receive data terminal, a second node in electrical communication with the first TTL power supply and a control node in electrical communication with the TTL receive data terminal. The interface circuit is configurable to a first switching state in which electrically connects the first TTL power supply terminal to the RS 232 receive data terminal.

Abstract: A microtransformer for a high-performance system-on-chip power supply is disclosed. Through-wafer openings in a substrate allow the primary and secondary wiring on both surfaces of the silicon substrate. An insulating silicon oxide layer is first deposited on all surfaces of the substrate. A magnetic film is further deposited on the silicon oxide layer followed by the application of another insulating layer. Coils are fabricated next by patterned deposition on both sides of the substrate and through the holes. The coils can be, e.g., single coils or primary or secondary coils of a transformer structure, with secondary having one or more output taps to supply different output voltages. For better flux closure, various magnetic layers and insulators can be deposited on top of the windings.

Abstract: A new method to form a LVT-SCR device in the manufacture of an integrated circuit device is achieved. The method comprises providing a SOI substrate comprising a silicon layer overlying a buried oxide layer. The silicon layer further comprises a first well of a first type and a second well of a second type. First and second doped regions of the first type are formed. The first doped region is in the first well. The second doped region is in the second well and forms an anode. Third, fourth, and fifth doped regions of the second type are formed. The third and fourth doped regions are in the first well. The fifth doped region is partly in the first well and partly in the second well. The first and third doped regions form a cathode. First and second gates are formed overlying the silicon layer. The first gate is between the third and fourth doped regions. The second gate is between the fourth and fifth doped regions. The doped regions are not separated by isolation oxide.

Abstract: An inrush current limiting circuit, a power source device, and a power conversion device. The circuit and devices limit an inrush current with high reliability and durability while reducing overall weight and volume of the device even under a high rated power. A switch, a capacitor, and a switching element are connected in series to one another, and the serial circuit formed thereof is connected to the main power source. An inverter is connected to the capacitor. A serial circuit formed of a capacitor and a resistor is connected between a collector and a gate of the switching element. A drive circuit drives a switching element to turn ON when the switch turns ON.