Abstract: An electronic apparatus includes an electronic component electrically connected to a substrate positioned beneath the electronic component. A member includes a plurality of decoupling capacitors having different voltages, and the decoupling capacitors are electrically connected to the electronic component. A plurality of voltage planes in the member are electrically connected to the decoupling capacitors. The decoupling capacitors, via the voltage planes in the member, provide different voltages to the voltage planes and thus the electronic component.

Abstract: A circuit system comprising: forming a lower electrode over a substrate; forming a resistive film over the lower electrode; forming a multi-layered insulating stack over a portion of the resistive film; and forming an upper electrode over a portion of the multi-layered insulating stack.

Abstract: For the purpose of providing a semiconductor element built-in type multilayered circuit board in which a semiconductor element is closely joined to a recess of an insulating substrate to effectively disperse heat generated from the semiconductor element through the insulating substrate at a working temperature region of the semiconductor element circuit board, to surely conduct an electrical connection of an electronic part such as semiconductor element or the like in a short wiring and to enable the high density mounting of semiconductor elements, miniaturization and increase of working speed, there is proposed a semiconductor element built-in type multilayered circuit board formed by laminating a plurality of semiconductor element built-in type boards each comprising an insulating substrate and a semiconductor element accommodated in a recess formed therein, characterized in that a difference between a linear expansion coefficient of the insulating substrate and a linear expansion coefficient of the semicon

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract: Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.

Abstract: A printed wiring board includes an insulating layer and a capacitor including a ceramic high dielectric layer being interposed between a first and a second electrode, and a semiconductor device mounting pad, including a first and a second pad, formed on an outermost resin insulating layer of the resin insulating layers. An underfill which covers an area larger than that of the high dielectric layer is formed, when the underfill covered area is projected along a lamination direction of the resin insulating layers to a face on which the high dielectric layer is formed. The capacitor is located immediately beneath the underfill covered area.

Abstract: An ultra-wideband assembly in an electrical circuit having a circuit board with a conductive micro-strip line is provided. The assembly includes a non-conductive tapered core having an outer surface, a distal end, and a proximate end. The distal end is being larger than proximate end. The assembly includes a conductive wire having a proximate end and a distal end and being wound about at least a portion of the non-conductive tapered core. The proximate end of the conductive wire extends away from the proximate end of the non-conductive tapered core and is being conductively coupled to the micro-strip line of the circuit board. The distal end of the conductive wire extends away from the distal end of the non-conductive tapered core. The conductive wire contacts at least a portion of the outer surface of the non-conductive tapered core. The assembly includes a supporting bracket coupled to the non-conductive tapered core. The bracket includes a base portion and a core attachment portion.

Abstract: A power converter is disclosed in which the structure of a connecting portion is highly resistant against vibration and has a low inductance. The power converter includes a plurality of capacitors and a laminate made up of a first wide conductor and a second wide conductor joined in a layered form with an insulation sheet interposed between the first and second wide conductors. The laminate comprises a first flat portion including the plurality of capacitors, which are supported thereon and electrically connected thereto, a second flat portion continuously extending from the first flat portion while being bent, and connecting portions formed at ends of the first flat portion and the second flat portion and electrically connected to the exterior.

Abstract: The present invention relates to a chip embedded printed circuit board and a manufacturing method thereof. The present invention provides the chip embedded printed circuit board including an insulating layer embedding a chip provided with posts at an upper part, vias formed through the insulating layer, upper patterns formed at the upper part of the insulating layer to be connected to the posts and the vias and lower patterns formed at a lower part of the insulating layer to be connected to the vias, and the manufacturing method thereof.

Abstract: A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.

Abstract: According to one embodiment, there is a high frequency circuit having a multi-chip module structure, including a semiconductor substrate set formed with discrete transistors connected in series, a first dielectric substrate set formed with capacitors, and a second dielectric substrate set formed with strip lines.

Abstract: A package substrate includes a main package body including a first principal surface on which an IC is mounted, and a second principal surface, opposed to the first principal surface, on which first bonding materials for mounting are provided. An internal circuit is provided within the main package body and connected to the first bonding materials. A sub-package is arranged on the second principal surface and includes electronic components embedded therein. A thickness direction dimension being the distance from the second principal surface to a portion of the sub-package most distant from the second principal surface, is not more than a thickness direction dimension being the distance from the second principal surface to an edge of the first bonding material at the second principal surface.

Abstract: Disclosed herein are an electromagnetic bandgap structure and a printed circuit board having the same. The bandgap structure includes a conductive layer including a plurality of conductive plates; and a metal layer disposed over or under the conductive layer and including a stitching pattern to electrically connect a first conductive plate to a second conductive plate of the plurality of conductive plates. The bandgap structure includes a spiral stitching pattern formed in a metal layer different from the conductive layer, thus offering a stop-band having a desired bandwidth in a compact structure.

Abstract: Chip capacitors are provided in a printed circuit board. In this manner, the distance between the IC chip and each chip capacitor is shortened, and the loop inductance is reduced. In addition, the chip capacitors are accommodated in a core substrate having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

Abstract: A multilayer printed circuit board, wherein, on a resin-insulating layer that houses a semiconductor element, another resin-insulating layer and a conductor circuit are formed with conductor circuits electrically connected through a via hole, wherein an electromagnetic shielding layer is formed on a resin-insulating layer surrounding a concave portion for housing a semiconductor element or on the inner wall surface of the concave portion, and the semiconductor element is embedded in the concave portion.

Abstract: A method of manufacturing a multilayer printed circuit board of a built-in electronic device provides a substrate having a copper clad laminate and a first dielectric layer. The first dielectric layer is laminated onto the copper clad laminate and has a cavity for accommodating the electronic device. A second dielectric layer is laminated onto the substrate and electronic device to produce a base circuit board with an embedded electronic device. A build-up circuit layer is formed on the base circuit board. The first and second dielectric layers are made of a plastic material.

Abstract: The electronic substrate includes: a substrate having a first face on which an active element is formed, and a second face on an opposite side to the first face and on which a passive element is formed; and an insulating layer including insulating resin and provided on the substrate, wherein the passive element is formed on the insulating layer, and further comprising: an interconnection pattern arranged on or above the second face of the substrate, wherein the passive element is configured from one part of the interconnection pattern, and a resin layer provided on the second face of the substrate, wherein at least one part of the passive element is formed on the resin layer.

Abstract: A printed circuit board having an embedded chip capacitor includes a first conductive layer; a second conductive layer, placed away from the first conductive layer; a chip capacitor, having a first electrode connected to the first conductive layer through being seated in a cavity formed between the first conductive layer and the second conductive layer; a filled material, filled in a space excluding a space occupied by the chip capacitor in the cavity; and a via, penetrating the filled material and connecting the second conductive layer to the second electrode of the chip capacitor.

Abstract: A capacitor with a combined with a resistor and/or fuse is described. This safe capacitor can rapidly discharge through the resistor when shorted. The presence of a fuse in series with the capacitor and results in a resistive failure when this opens during and overcurrent condition. Furthermore, the presence of a resistor in parallel to the capacitor allows the energy to be rapidly dissipated when a failure occurs.

Abstract: A printed circuit board includes first and second layers, a control chip, bonding pads, and several electronic elements. The bonding pads can be selectively applied to interconnect the first and second layers, and the control chip with any of the electronic elements in a simple layout.

Abstract: An EMI noise reduction board using an electromagnetic bandgap structure is disclosed. In the EMI noise reduction board according to an embodiment of the present invention, an electromagnetic bandgap structure having band stop frequency properties can be inserted into an inner portion of the board so as to shield an EMI noise, in which the portion corresponds to an edge of the board and in which the EMI noise is conducted from the inside to the edge of the board and radiates to the outside of the board.

Abstract: In the present electronic structure, a substrate is provided in the form of a circuit board. First and second electronic devices are positioned on opposite sides of the circuit board, each having a plurality of contacts connected to the circuit board. Each of the contacts of the first device is connected to a contact of the second device by a connector though the circuit board. At least one of the contacts of the first device is connected to the contact of the second device which is most adjacent to that contact of the first device across the circuit board.

Abstract: Disclosed is a printed circuit board including an electromagnetic bandgap structure. The electromagnetic bandgap structure, which includes a first dielectric material for interlayer insulation and is for blocking a noise, is inserted into the printed circuit board. The electromagnetic bandgap structure can include a first conductive plate, a second conductive plate arranged on a planar surface that is different from that of the first conductive plate, a third conductive plate arranged on a same planar surface as the first conductive plate, and a stitching via unit configured to connect the first conductive plate and the third conductive plate through the planar surface on which the second conductive plate is arranged. A second dielectric material having a permittivity that is different from that of the first dielectric material is interposed between any two of the first conductive plate, the second conductive plate, and the third conductive plate.

Abstract: Using die side capacitors and embedded resistors, an advantageous power delivery network may be achieved. In some embodiments, the embedded resistors may be more precisely controllable. The number of die side capacitors may be reduced by combining embedded resistors with these capacitors to reduce costs. The embedded resistors may be provided within the metallization layers either at an upper layer or a lower layer, as two examples.

Abstract: An EMI noise reduction board is disclosed. The electromagnetic interference (EMI) noise reduction board having an electromagnetic bandgap structure for shielding a noise includes: a first area having a ground layer and a power layer; a second area placed in a side portion of the first area having an electromagnetic bandgap structure therein. The electromagnetic bandgap structure includes: a plurality of first conductive plates and a plurality of second conductive plates placed on a same planar surface along the side portion of the first area; and a stitching via configured to electrically connect the first conductive plate to the second conductive plate through a planar surface that is different from the first conductive plate and the second conductive plate.

Abstract: A printed circuit board includes a first signal layer, a first reference layer, a second reference layer, and a second signal layer. An integrated circuit mounted on the first signal layer includes a power supply terminal connected to a first power supply via. The second signal layer includes a filter and a power supply wire. The filter includes a power terminal connected to the first power supply via, and a ground terminal connected to the second reference layer. The first power supply via is connected to the first reference layer through the power supply wire and a second power supply via. A void defined in the second reference layer is at least partially vertically overlapping with the power supply wire, and enables the first reference layer to function as a reference plane for the power supply wire, to increase impedance of the power supply wire.

Abstract: A printed circuit board includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the signal transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path. A length of a first axis, perpendicular to the signal transmission line, of the void satisfies a following equation: W 1 ? 8 ? Wpad + 10 ? T 0.8 ? Wtrace + T , wherein Wpad is a width of the pad, Wtrace is a width of the transmission line, T is the height of the pad.

Abstract: A printed circuit board has capacitors, a grounding wiring pattern having a bonding surface on which a semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to first electrodes of the capacitors, and a power supply wiring pattern having a bonding surface on which the semiconductor device is bonded, and a contact surface located opposite from the bonding surface thereof and coupled to second electrodes of the capacitors. The grounding and power supply wiring patterns are alternately arranged in a predetermined direction, and the capacitors are coupled in parallel with respect to the grounding and power supply wiring patterns.

Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

Abstract: A multilayer printed wiring board includes: a build-up layer that is formed on a core substrate and has a conductor pattern disposed on an upper surface; a low elastic modulus layer that is formed on the build-up layer; lands that are disposed on an upper surface of the low elastic modulus layer and connected via solder bumps to a IC chip; and conductor posts that pass through the low elastic modulus layer and electrically connect lands with conductor patterns. The conductor posts have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 ?m, and the aspect ratio Rasp of external conductor posts, which are positioned at external portions of the low elastic modulus layer, is greater than or equal to the aspect ratio Rasp of internal conductor posts, which are positioned at internal portions of the low elastic modulus layer.

Abstract: A printed wiring board includes a mounting portion on which a dual core processor including two processor cores in a single chip can be mounted, power supply lines, ground lines, and a first layered capacitor and a second layered capacitor that are independently provided for each of the processor cores, respectively. Accordingly, even when the electric potentials of the processor cores instantaneously drop, an instantaneous drop of the electric potential can be suppressed by action of the layered capacitors corresponding to the processor cores, respectively. In addition, even when the voltage of one of the processor cores varies, the variation in the voltage does not affect the other processor core, and thus malfunctioning does not occur.

Abstract: A power module is proposed to package an electronic system having flip chip power MOSFET devices. The power module includes a front surface cover board and a multi-layer printed circuit laminate bonded thereto. Notably, the front surface of the printed circuit laminate includes recessed pockets each having printed circuit traces atop its floor. Inside the recessed pockets are power MOSFET and other circuit components bonded to the printed circuit traces. As the circuit components are encased inside the power module, it features a low profile, an increased mechanical robustness and EMI/RFI immunity. Additionally, some circuit components can be provided with a front-side bonding layer that is also bonded to the front surface cover board to realize a double-side bonding to the interior of the power module. Methods for making the low profile power module are also described.

Abstract: A circuit board device includes a circuit board comprising a mounting area, and first and second power lines and a ground pad formed on the mounting area, and a vertical multilayer chip capacitor (MLCC) comprising a capacitor body, a plurality of first and second polarity inner electrodes, first and second outer electrodes, and a third outer electrode, wherein the first and second power lines are separately disposed on the mounting area, connected to the first and second outer electrodes, and electrically connected to each other only by the vertical MLCC, and the ground pad is disposed between the first and second power lines and connected to the third outer electrode.

Abstract: A holder for mounting multiple capacitors onto a circuit board includes a main structure and a plurality of latching member. The main structure has a top plate and a plurality of side plates. The top plate includes a plurality of holding slots, with the latching members off the side plates. Each latching member has an extension portion and an engaging member. The engaging member is located at the end of the extension under the bottom edge of the side plate. The capacitor includes a main body and a pair of electric leads at one end of the main body. At the opposite end of the electric leads, the main body is bounded on top by the top plate of the main structure, where the main body of each capacitor emerges partially above the upper surface of the top plate.

Abstract: In a dielectric element, the angle ? made by either the top face or the bottom face and the side faces is either 0°<?<89°, or is 91°<?<180°, and is an angle other than 89°???91°. By this means, the area of contact of the side faces of the dielectric element with a glass epoxy resin substrate and with insulating material is increased, adhesion with the resin substrates is improved, and strength and reliability can be enhanced when buried between the two resin substrates.

Abstract: Means for Solution: This interposer (10) comprises the silicon substrate (12), a plurality of through-hole conductors (20) formed on the above-described silicon substrate, and a capacitor (15) formed with the upper electrodes (14) and the lower electrodes (18) formed by extending the land portions of the above-described through-hole conductors and the dielectric layer (16) formed between the both electrodes. The rewiring layers (23-1, 23-2) formed as desired are formed on the layers other than the above-described capacitor layer.

Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.

Abstract: According to one embodiment, there is provided a printed-wiring board, includes a first base member including a component mounting face, a first electronic component with a through-electrode mounted on the component mounting face, a second base member stacked on the first base member via an insulating layer covering the first electronic component, a hole part provided in the second base member and communicating with the through-electrode of the first electronic component, and a second electronic component mounted on the second base member and circuit-connected directly to the through-electrode via the hole part.

Abstract: A circuit board includes a semiconductor chip having an upper surface and side surfaces connected to the upper surface. A bonding pad is disposed on the upper surface of the semiconductor chip. A bump is disposed on the bonding pad and projects from the bonding pad by a predetermined height. A circuit board body has a recess part, and the semiconductor chip is positioned in the recess part so that the circuit board body covers the upper surface and the side surfaces of the semiconductor chip while exposing an end of the bump. A wiring line is disposed on the circuit board body and part of the wiring line is positioned over the bump. An opening is formed in a portion of the part of the wiring line over the bump to expose the bump. A reinforcing member physically and electrically connects the exposed bump and the wiring line.

Abstract: In a method for manufacturing a ceramic multilayer substrate, when a green ceramic stack prepared by stacking a plurality of ceramic green sheets is fired simultaneously with a ceramic chip electronic component disposed inside the green ceramic stack and including an external terminal electrode to produce a ceramic multilayer substrate having the ceramic chip electronic component inside, a paste layer is disposed in advance between the ceramic chip electronic component and the green ceramic stack, and these three are fired.

Abstract: The invention provides a multilayer printed wiring board including: a power supply wiring layer and a ground wiring layer provided so as to oppose each other via an insulation layer; mounted integrated circuits; and decoupling capacitors mounted in proximity to the integrated circuits and connected between the power supply wiring layer and the ground wiring layer to absorb noise from the integrated circuits. The power supply wiring layer includes through holes for connecting the decoupling capacitors to the power supply wiring layer and has a polygonal form formed by straight lines which link some of the through holes.

Abstract: A printed circuit board has a core substrate including a resin substrate having an opening, a capacitor formed in the opening and having a first electrode structure having a portion facing to the upper surface of the core substrate and a second electrode structure having a portion facing to the lower surface of the core substrate, an upper insulating layer formed over the upper surface of the core substrate and having a conductive circuit formed over the upper insulating layer and a via hole electrically connecting the portion of the first electrode structure and the conductive circuit of the upper insulating layer, and a lower insulating layer formed over the lower surface of the core substrate and having a conductive circuit formed over the lower insulating layer and a via hole electrically connecting the portion of the second electrode structure and the conductive circuit of the lower insulating layer.

Abstract: A printed circuit board includes a chip capacitor having electrodes and a metal film formed on one or more of the electrodes, an accommodating layer accommodating the chip capacitor inside the accommodating layer, a connection layer formed over the accommodating layer and having a via hole opening extending to the metal film, and a first via hole structure formed in the via hole opening of the connection layer and connected to the metal film on the one or more of the electrodes of the chip capacitor.

Abstract: A component-embedded module includes a module substrate having wiring electrodes on the upper surface thereof, first circuit components mounted on the wiring electrodes, a sub-module disposed on an area on which no wiring electrodes are provided, and an insulating resin layer provided on substantially the entire upper surface of the module substrate such that the insulating resin layer covers at least a portion of the first circuit components and sub-module. The second circuit components including an integrated circuit element are mounted on the sub-module or embedded therein. Via conductors are provided through the module substrate from the lower surface thereof and are directly coupled to terminal electrodes on the lower surface of the sub-module. By using a substrate having a wiring greater accuracy than that of the module substrate, a reliable component-embedded module is obtained.

Abstract: Disclosed herein is a printed circuit board having an RF module power stage circuit embedded therein. Specifically, this invention relates to a printed circuit board having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.

Abstract: In a hybrid integrated circuit device that uses a metal substrate, a sound noise is prevented, which would otherwise be generated due to transmission, to the metal substrate, of vibration caused when a ceramic capacitor expands and contracts by switching ON and OFF a transistor. For improving a heat dissipation effect, a switching transistor driven by a driving pulse and a ceramic capacitor connected to the switching transistor are incorporated on a conductive path on an insulated metal substrate. Both ends of the ceramic capacitor are fixed to the conductive path by solders which are covered with a hard resin to be protected from a solder crack by thermal expansion of the metal substrate. The ceramic capacitor and the hard resin are wholly covered with a soft resin which absorbs noise due to expansion caused when the ceramic capacitor is switched, so that the metal substrate is prevented from resonating.

Abstract: In an electronic control device that includes two or more kinds of lead-insertion-type parts, including at least a coil and a capacitor, the parts are installed on a support that has a wiring, a terminal structure and mechanically fixing portions; the leads of the above parts are respectively inserted in and electrically connected to holes formed in the wiring portion of the support; the parts and the support are fixed to each other with an adhesion material for fixation; the upper surfaces of the parts are attached to a metallic chasis with a thermally conductive material of a low elasticity modulus interposed in between; the mechanically fixing portions of the support are fixed to the metallic chasis; and the terminal structure of the support is electrically connected to a circuit board that mounts at least a controlling element.

Abstract: A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

Abstract: A semiconductor device includes a semiconductor element, a supporting substrate where the semiconductor element is mounted, and a capacitor provided on the semiconductor element and coupled to the supporting substrate via an outside connection terminal. The capacitor includes a valve metal part, an anodic oxide film formed on a surface of the valve metal part, and a conductive part formed on the anodic oxide film and made of a conductive material.

Abstract: A connector is provided for simultaneously improving both the NEXT high frequency performance when low crosstalk plugs are used and the NEXT low frequency performance when high crosstalk plugs are used. The connector includes PCB substrates made of materials having different dielectric frequency characteristics.