Abstract: There are provided a signal transmission apparatus and a signal transmission method for use therewith, the apparatus using a small-sized connector configuration and a flexible printed circuit board to prevent a decrease in the quality of a differential signal. The flexible printed circuit board has signal transmission paths for transmitting the differential signal. At least one of connector connection parts of the flexible printed circuit board has a first connection part column and a second connection part column obtained by arranging a plurality of signal line connection parts, the signal line connection parts being connection parts between the signal transmission paths and intra-connector wiring. Each of the signal line connection parts in the connection part columns is configured to be connected with the signal transmission path formed on the back side of the flexible printed circuit board by way of a VIA (through-hole) formed between the first connection part column and the second connection part column.

Abstract: An interconnection for flex circuit boards used, for instance, in a quantum computing system are provided. In one example, the interconnection can include a first flex circuit board having a first side and a second side opposite the first side. The interconnection can include a second flex circuit board having a third side and a fourth side opposite the third side. The first flex circuit board and the second flex circuit board are physically coupled together in an overlap joint in which a portion of the second side for the first flex circuit board overlaps a portion of the third side of the flex circuit board. The interconnection can include a signal pad structure positioned in the overlap joint that electrically couples a first via in the first flex circuit board and a second via in the second flex circuit board.

Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.

Abstract: An ultrasound probe and method for using the same are described. In one embodiment, the ultrasound probe comprises: a probe array assembly having a probe tip; a first enclosure disposed around a portion of the probe array assembly, where the first enclosure has first and second openings and comprises a thermally conductive material; and one or more thermally conductive fins contained within the first enclosure, each of the one or more thermally conductive fins having one end enclosed within the probe array assembly and a portion extending away from the probe array assembly and in thermal contact with an inner surface of the first enclosure to create a thermal path from the first opening to the second opening in the first enclosure.

Abstract: A flexible electronic device including a flexible substrate, a plurality of first signal lines, a plurality of first transmission lines, a plurality of first through holes, and a plurality of first conductive structures is provided. The flexible substrate has a first surface and a second surface opposite to the first surface. The first signal lines are located on the first surface and have a first extending direction. The first transmission lines are located on the second surface and have a second extending direction. A first included angle is provided between the first extending direction and the second extending direction. An angle of the first included angle is between 10° and 80°. The first through holes penetrate through the flexible substrate. The first conductive structures are located in the first through holes and are electrically connected to the first signal lines and the first transmission lines.

Abstract: A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality.

Abstract: A printed circuit board includes: a first flexible base member; a first metal line disposed on the first flexible base member; a first plating line disposed on the first metal line and including a first connecting portion, a first interconnection portion extending from the first connecting portion, and a first bending portion extending from the first interconnection portion; a first protective layer covering the first interconnection portion and exposing the first connecting portion and the first bending portion; a connection part disposed on the first bending portion and connected to the first bending portion; a second protective layer extending from a side surface of the connection part; a second plating line disposed on the second protective layer; a second metal line disposed on the second plating line; and a second flexible base member disposed on the second metal line.

Abstract: A method is provided. The method includes one or more of securing a die into a cavity of a hermetic package base, providing one or more bond connections to the die, placing a hermetic package lid on the package base, and 3D printing, by a 3D printer, hermetic lid seal material to a joint between the hermetic package base and the hermetic package lid, at a temperature at or below 100 degrees Celsius.

Abstract: A microelectronic circuit having at least one component adjacent a carrier that is not a semiconductor or sapphire. The circuit includes a component bearing stack of one or more layers having one or more passive components, which are adjacent or bonded to the carrier. In certain embodiments, the circuit also includes an etch stop layer of a material having a slower etch rate than silicon and a bond layer bonding the carrier and the component bearing one or more layers.

Abstract: An electronic device and a method of waterproofing a key thereof are provided. The electronic device includes a body, a display device disposed in the body, a key disposed in the body, and a key-waterproof structure including an insert-injected product that includes an insert-injected sealing area, and a bonding area where a silicon-not-attached portion is formed. The method includes assembling a flexible printed circuit board, to which a key is attached, through a silicon-not-attached portion of an insert-injected product, which is made by insert-injecting a bracket and silicon rubber, and bonding the silicon-not-attached portion.

Abstract: An electronic component includes an external terminal member made of a conductive metal and an insulating section in contact with the external terminal member. The external terminal member includes an exposed portion which faces outside and which is located on the predetermined surface side thereof. The electronic component is fixed with solder applied to the exposed portion of the external terminal member. The exposed portion of the external terminal member is given by a base plating film made of nickel or a nickel alloy and an outer plating film which is placed on the base plating film and which is made of gold, tin, or an alloy containing at least one of gold and tin. The outer plating film includes a relatively thick region and a relatively thin region surrounding the relatively thick region.

Abstract: A method is described. The method is a method for making a constraining ceramic assembly. The method includes applying at least one metallic electrode to a substrate. The method also includes applying a porous ceramic layer to the substrate to cover the metallic electrode. The method also includes sintering the substrate, the porous ceramic layer, and the metallic electrode together at a sintering temperature above a melting point of the metallic electrode.

Abstract: A flexible display substrate, a flexible organic light emitting display device, and a method of manufacturing the same are provided. The flexible display substrate comprises a flexible substrate including a display area and a non-display area extending from the display area, a first wire formed on the display area of the flexible substrate, and a second wire formed on the non-display area of the flexible substrate, wherein at least a part of the non-display area of the flexible substrate is curved in a bending direction, and the second wire formed on at least a part of the non-display area of the flexible substrate includes a first portion formed to extend in a first direction and a second portion formed to extend in a second direction.

Abstract: In a method for producing a printed circuit board consisting of at least two printed circuit regions, wherein the printed circuit board regions each comprise at least one conductive layer and/or at least one device or one conductive component, wherein printed circuit board regions to be connected to one another, in the region of in each case at least one lateral surface directly adjoining one another, are connected to one another by a coupling or connection, and wherein, after a coupling or connection of printed circuit board regions, at least one additional layer or ply of the printed circuit board is applied over the printed circuit board regions, the additional layer is embodied as a conductive layer, which is contact-connected via plated-through holes to conductive layers or devices or components integrated in the printed circuit board regions.

Abstract: A component-embedded substrate having a multilayer substrate formed by laminating a plurality of thermoplastic sheets in a predetermined direction, an internal component provided in the multilayer substrate, and a surface-mount component mounted on a surface of the multilayer substrate using bumps. The surface-mount component, when viewed in a plan view in the predetermined direction, is positioned so as to cross an outline of the internal component, with the bumps on the surface-mount component located 50 ?m or more from the outline of the internal component.

Abstract: Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used.

Abstract: A manufacturing method of a package carrier includes the following steps. Firstly, two base metal layers are bonded together. Then, two supporting layers are laminated onto the base metal layers respectively. Next, two release metal films are disposed on the supporting layers respectively, wherein each of the release metal films includes a first metal film and a second metal film separable from each other. Next, two patterned metal layers are formed on the release metal films respectively, wherein each of the patterned metal layers is suitable for carrying and electrically connected to a chip. Then, the base metal layers are separated from each other to form two package carriers independent from each other. A package carrier formed by the manufacturing method described above is also provided.

Abstract: Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used.

Abstract: A power overlay (POL) packaging structure that incorporates a leadframe connection is disclosed. The a POL structure includes a POL sub-module having a dielectric layer, at least one semiconductor device attached to the dielectric layer and that includes a substrate composed of a semiconductor material and a plurality of connection pads formed on the substrate, and a metal interconnect structure electrically coupled to the plurality of connection pads of the at least one semiconductor device, with the metal interconnect structure extending through vias formed through the dielectric layer so as to be connected to the plurality of connection pads. The POL structure also includes a leadframe electrically coupled to the POL sub-module, with the leadframe comprising leads configured to make an interconnection to an external circuit structure.

Abstract: An electrical circuit structure can include a first trace formed using a first conductive layer and a second trace formed using a second conductive layer. The first trace can be vertically aligned with the second trace. The electrical circuit structure can include a via segment formed of conductive material in a third conductive layer between the first conductive layer and the second conductive layer. The via segment can contact the first trace and the second trace forming a first conductor structure configured to convey an electrical signal in a direction parallel to the first conductive layer.

Abstract: A method is provided for fabricating a substrate having multiple metal layers separated by one or more dielectric layers, respectively. The method includes forming a cavity in at least one dielectric layer through an exposed portion of a top dielectric layer of the substrate, applying metal to side and bottom surfaces of the cavity, forming a pattern through a portion of the metal applied to the bottom surface of the cavity, and micro-etching the metal applied to the bottom surface of the cavity. The micro-etching extends the pattern through a remaining portion of the metal applied to the bottom surface of the cavity.

Abstract: An semiconductor device includes a semiconductor substrate; a metal layer arranged above the semiconductor substrate; a first passivation film that contacts at least a portion of one side surface of the metal layer; and a second passivation film that is arranged extending from the first passivation film to the metal layer, and contacts an upper surface of the first passivation film, and contacts at least a portion of an upper surface of the metal layer.

Abstract: A printed circuit board includes a motherboard and a daughterboard. The motherboard includes at least one first signal pad and defines at least one via under the at least one first signal pad. The daughterboard includes at least one second signal pad and defines at least one via under the at least one second signal pad. The at least one first signal pad and the at least one second signal pad are sucked into the respective vias on the motherboard and the daughterboard according to siphon principle to allow each of the first signal pads and the second signal pads to form uneven top surfaces, the uneven top surfaces of the at least one first signal pads and the at least one second signal pads are connected to each other for electronically connecting the daughterboard to the motherboard.

Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

Abstract: A method of manufacturing a power module substrate in which a plurality of ceramic substrates and metal plates are alternately laminated, and bonded, and the metal plates on both sides of the ceramic substrates are in a connected state through penetration holes formed in the ceramic substrate, wherein, when the ceramic substrates and the metal plates are laminated, columnar metallic members that are longer than the penetration holes are inserted into the penetration holes in the ceramic substrate, and, when the ceramic substrates and the metal plates are bonded, the metallic members are pressurized and plastically deformed so that the metal plates on both sides of the ceramic substrates are bonded through the metallic members.

Abstract: A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring.

Abstract: Disclosed herein is a printed circuit board having electronic components embedded therein. The printed circuit board having electronic components embedded therein includes: a metal core layer connected to a ground terminal of an external power supply to be grounded and having a cavity or a groove part formed thereon; an electronic component accommodated in the cavity and having a plurality of terminals, a ground terminal included in the plurality of terminals being connected to the metal core layer; an internal insulating layer stacked on both sides of the metal core layer; and circuit patterns formed on an external surface of the internal insulating layer.

Abstract: A multilayered printed wiring board includes a plurality of insulating layers; a plurality of wiring layers which are located between the corresponding adjacent insulating layers; and a plurality of interlayer connection conductors for electrically connecting the wiring layers through the insulating layers; wherein a cavity is formed through one or more of the insulating layers so as to insert a first electric/electronic component and an area for embedding a second electric/electronic component is defined for the insulating layers.

Abstract: A wiring board including a first rigid wiring board having an accommodation portion and a conductor, a second rigid wiring board accommodated in the accommodation portion of the first rigid wiring board and having a conductor electrically connected to the conductor of the first rigid wiring board, and an insulation layer formed on the first rigid wiring board and the second rigid wiring board. The accommodation portion of the first rigid wiring board has wall surfaces tapering from a first surface of the first rigid wiring board to a second surface on the opposite side of the first surface, and the second rigid wiring board has side surfaces tapering such that the side surfaces of the second rigid wiring board substantially fit into the wall surfaces of the accommodation portion of the first rigid wiring board.

Abstract: A method of manufacturing a printed circuit board (PCB) having an embedded bare chip includes attaching a tape to one side of an insulated substrate having a penetration hole formed therein, and attaching the bare chip onto the tape inside the penetration hole such that electrode pads of the bare chip face the tape; filling up the penetration hole with a filler, and removing the tape; laminating a metal layer onto a surface of the filler and the insulated substrate from which the tape is removed; and forming electrode bumps by removing portions of the metal layer. The forming of electrode bumps further includes simultaneously removing portions of the metal layer and forming an circuit pattern on one side of the insulated substrate. The circuit pattern is formed directly on the upper side of the insulated substrate and the electrode bumps are formed on the surface of the electrode pads.

Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.

Abstract: An interface module has an integrated component for replacing a component on a circuit board, the terminal contacts on the bottom side of the interface module being designed as provided for the contacts of the component on the circuit board, the interface module being divided into an adaptor part as a base module and a protocol converter part as a tool access module.

Abstract: An apparatus includes a coreless substrate with an embedded die that is integral to the coreless substrate, and at least one device assembled on a surface that is opposite to a ball-grid array disposed on the coreless substrate. The apparatus may include an over-mold layer to protect the at least one device assembled on the surface.

Abstract: A package structure includes a base body having a first encapsulant and a wiring layer embedded in and exposed from the first encapsulant. The wiring layer has a plurality of conductive traces and a plurality of first electrical contact pads. The first encapsulant has openings for exposing the first electrical contact pads, a chip electrically connected to the wiring layer, and a second encapsulant formed on the base body for covering the chip and the wiring layer, thereby providing an even surface for preventing the encapsulant from cracking when the chip is mounted.

Abstract: This relates to systems and methods for providing one or more vias through a module of an electrical system. For example, in some embodiments, the module can include one or more passive elements and/or active of the electrical system around which a packaging has been plastic molded. The module can be stacked under another component of the electrical system. Vias can then be provided that extend through the module. The vias can include, for example, electrically conductive pathways. In this manner, the vias can provide electrical pathways for coupling the component stacked on top of the module to other entities of an electronic device including the electrical system. For example, the component can be coupled to other entities such as other components, other modules, printed circuit boards, other electrical systems, or to any other suitable entity.

Abstract: A multi-chip module includes a chip stack package including at least one pair of stacked dies, the dies having overlapping opposing faces, and at least one capacitive proximity communication (CPC) interconnect between the pair of stacked dies. The CPC interconnect includes a first capacitor plate at a first one of the overlapping opposing faces and a second capacitor plate at a second one of the overlapping opposing faces spaced from and aligned with the first capacitor plate. The CPC interconnect further includes an inductive element connected in series with the first capacitor plate and second capacitor plate, wherein the capacitor plates form part of a capacitor and the capacitor cooperates with the inductor element to form a LC circuit having a resonant frequency.

Abstract: A component is configured for connection with a microelectronic assembly having terminals and a microelectronic element connected with the terminals. The component includes a support structure bearing conductors configured to carry command and address information, and a plurality of contacts coupled to the conductors and configured for connection with the terminals. The contacts have address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate.

Abstract: A module is configured for connection with a microelectronic assembly having terminals and a microelectronic element. The module includes a circuit panel bearing conductors configured to carry command and address information, co-support contacts coupled to the conductors, and module contacts coupled to the conductors. The co-support contacts include first contacts having address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the first contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the first contacts at a second sampling rate greater than the first sampling rate.

Abstract: A method for manufacturing a printed circuit board includes forming an opening portion in a substrate, positioning chip capacitors in the opening portion of the substrate such that the chip capacitors are accommodated in the opening portion of the substrate, forming a buildup structure including an interlayer resin insulating layer and a conductive layer over a surface of the substrate and the chip capacitors accommodated in the opening portion of the substrate, and forming on a surface of the buildup structure bump structures positioned to mount an IC chip such that the chip capacitors in the opening portion of the substrate are positioned directly below the IC chip.

Abstract: A multichip module comprising: a base substrate; a wiring board disposed on the base substrate and having a wiring pattern; an adhesive layer configured to bond the base substrate to the wiring board while maintaining an electrical connection between the base substrate and the wiring board; and a plurality of chips connected to a surface of the wiring board, the surface being opposite the adhesive layer, wherein, assuming that ? is a coefficient of thermal expansion of the wiring board, ? is a coefficient of thermal expansion of the base substrate, and ? is a coefficient of thermal expansion of the adhesive layer, the relationship ?<?<? is satisfied.

Abstract: A motherboard for an electronic device comprising a main printed circuit board (PCB) with a through-hole extending between the upper component surface and the lower surface. The motherboard includes a carrier PCB having a top surface and a bottom surface, and at least one component, e.g. an optical device, sensor, or the like, coupled to the top surface. The carrier PCB is mounted in an in an inverted orientation with respect to the main PCB such that the top surface of the carrier PCB faces the upper component surface of the main PCB. The carrier PCB is aligned with the main PCB such that the component is substantially aligned with the through hole of the main PCB and is visible from the lower surface of the PCB.

Abstract: The present invention provides a method for embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blind vias are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. With this methodology a resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.

Abstract: A system includes a microelectronic assembly having terminals and a microelectronic element, and a component for connection with the microelectronic assembly. The component includes a support structure bearing conductors configured to carry command and address information, and contacts coupled to the conductors and connected with the terminals of the microelectronic assembly. The contacts have address and command information assignments arranged in a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and in a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate.

Abstract: Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.

Abstract: A device includes an interposer and a radio-frequency (RF) device bonded to a first side of the interposer. The interposer includes a first side and a second side opposite to the first side. The interposer does not have through-interposer vias formed therein. First passive devices are formed on the first side of the interposer and electrically coupled to the RF device. Second passive devices are formed on the second side of the interposer. The first and the second passive devices are configured to transmit signals wirelessly between the first passive devices and the second passive devices.

Abstract: A plurality of openings are formed in a resin insulation layer on a top surface side of a wiring laminate portion, and a plurality of openings are formed in a resin insulation layer on a bottom surface side thereof. A plurality of connection terminals are disposed to correspond to the openings. Peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the top surface side, and peripheral portions of terminal outer surfaces of the connection terminals are covered by the resin insulation layer on the bottom surface side. Each of the second-main-surface-side connection terminals has a concave portion at the center of the terminal outer surface, and the deepest portion of the concave portion is located on the interior side in relation to the peripheral portion of the terminal outer surface.

Abstract: Embedding a power modification component such as a capacitance inside of an adaptor board located to extend over and beyond the vias of the main circuit board so that a portion of the interposer board containing the embedded capacitance is located beyond where the vias or blinds are located. This permits that via to conduct through the opening. In this way, the capacitance and the resistance will have a closer contact point to the electrical component. A resistance can also be embedded in an opening in the adaptor board and be vertically aligned within the opening to make contact with a pad on top of the adaptor board and a pad at the bottom of the adaptor board so that electricity conducts through the embedded component.

Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.

Abstract: A printed circuit board includes a core substrate having an opening portion, an electronic component provided in the opening portion of the core substrate and including a dielectric body, a first electrode formed over the dielectric body, and a second electrode formed over the dielectric body such that the dielectric body is interposed between the first electrode and the second electrode, and a resin filling a gap between the core substrate and the electronic component in the opening portion of the core substrate. The resin filling the gap includes a filler.