Plural Contiguous Boards Patents (Class 361/792)
  • Patent number: 10905004
    Abstract: In some embodiments, an interconnectable circuit board may include one or more of the following features: (a) a first electrically conductive pad located on a top of the circuit board, (b) a plated through hole on the conductive pad which passes through the circuit board, (c) a second electrically conductive pad coupled to the plated through hole; the second conductive pad capable of being electrically connected to a third electrically conductive pad attached to a top of a second interconnectable circuit board, (d) cut marks indicating safe locations for separating the circuit board, and (e) a second cut mark adjacent to the first cut mark where the area between the first and second cut mark can be utilized to make a safe cut through the circuit board.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: January 26, 2021
    Assignee: Metrospec Technology, L.L.C.
    Inventors: Henry V. Holec, Wm. Todd Crandell
  • Patent number: 10867896
    Abstract: A device includes a package component comprising a substrate and a plurality of bumps formed on the substrate, a semiconductor die on the substrate, a dielectric layer over the substrate, wherein a top surface of the dielectric layer is level with a top surface of the semiconductor die, and a sidewall of the dielectric layer includes a slope portion and a vertical portion and a top package bonded on the package component, wherein the semiconductor die is located between the top package and the substrate.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 10842029
    Abstract: An electronic device includes a circuit board and an electronic element. The circuit board includes a plate body and multiple through holes extending through the plate body. Each of the through holes has a first diameter. The electronic element includes multiple pins, each of which is inserted into a respective one of the through holes, is secured to the circuit board by a soldering process, and has a second diameter smaller than the first diameter of the respective one of the through holes. For each of the pins, a difference between the second diameter of the pin and the first diameter of the respective one of the through holes ranges from 0.4 mm to 0.6 mm. A method for manufacturing the electronic device is also provided.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 17, 2020
    Assignee: Jabil Circuit (Guangzhou) Ltd.
    Inventors: Jiangang Tan, Jingmin Liang
  • Patent number: 10194524
    Abstract: In one embodiment, an apparatus includes a plurality of layers in a printed circuit board comprising at least one power plane and at least one ground plane, and a plurality of vias extending through the plurality of layers and connecting two or more of the layers, the plurality of vias comprising at least one pair of differential signal vias and at least one pair of power vias, the signal vias and power vias surrounded by a plurality of ground vias. The ground plane includes an anti-pad formed therein by an opening defined by removal of material, with the pair of differential signal vias and pair of power vias extending through the anti-pad in the ground plane to reduce power via resonance.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 29, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Il-Young Park, Jayanthi Natarajan
  • Patent number: 10049935
    Abstract: An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 14, 2018
    Assignee: QDOS FLEXCIRCUITS SDN BHD
    Inventors: Zalina Binti Abdullah, Roslan Bin Ahmad, Poh Cheng Ang, Poh Choon Whong, Hai San Tew, Shin Hung Hwang, Chee Can Lee, Tiyagarajan S/O Arumugham
  • Patent number: 9825399
    Abstract: Provided are a module assembly, a connector, and an electronic device, the module assembly including a first module that includes a pin configured to selectively protrude from a side thereof, a pin installation portion in which the pin is installed to be movable, and a first magnet configured to attract the pin into the pin installation portion, a second module to be coupled to the first module, the second module including a pin receiver configured to receive the pin when the pin protrudes from the first module, and a second magnet configured to attract the pin into the pin receiver, wherein the second magnet is configured to apply, to the pin, a greater magnitude of magnetic force than the first magnet in a case in which a distance between the first module and the second module is less than a preset distance.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: November 21, 2017
    Inventors: Seok Jung Kim, Yoon Son, Sang Hun Oh
  • Patent number: 9750138
    Abstract: A circuit module includes a circuit board and electronic components mounted on the circuit board. The mounted electronic components include at least one discrimination-target electronic component and at least one module-discrimination electronic component. In addition, the circuit board includes land electrodes allowing the module-discrimination electronic component to be mounted at different positions and/or orientations with respect to the circuit board, and the module-discrimination electronic component is mounted at any one position and/or orientation among different positions and/or orientations with respect to the circuit board in accordance with the type of the discrimination-target electronic component.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: August 29, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomoko Saito
  • Patent number: 9616660
    Abstract: A liquid ejection device includes a switching circuit. The switching circuit includes: a multilayer wiring board including a first wiring layer and a second wiring layer; a first transistor and a second transistor mounted on the first wiring layer side of the multilayer wiring board; and a capacitor mounted on the second wiring layer side of the multilayer wiring board. When the multilayer wiring board is viewed in a plan view, a third via conductor is arranged in an area not overlapping a straight-line path connecting a source electrode of the first transistor with a drain electrode of the second transistor in a second wire.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: April 11, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Atsushi Oshima, Noritaka Ide
  • Patent number: 9521758
    Abstract: A semiconductor device includes a semiconductor module that has an electrode terminal projecting externally; a substrate that has a through hole or a cut-out for inserting the electrode terminal; and a guide member that is provided between the semiconductor module and the substrate and guides the electrode terminal in such a manner that the electrode terminal is inserted into the through hole or the cut-out. The guide member becomes out of contact with the electrode terminal after the electrode terminal is inserted into the through hole or the cut-out.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: December 13, 2016
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Keita Hatasa, Arata Harada, Daisuke Harada
  • Patent number: 9513670
    Abstract: A touch panel including a substrate, at least one touch-sensing unit, at least one connecting pad, at least a testing line, at least one ESD protection circuit, and a first isolation layer is provided. The touch-sensing unit is disposed on the substrate. The connecting pad is disposed on the substrate and electrically connected to the touch-sensing unit. The testing line is disposed on the substrate, electrically connected to the connecting pad, and extends to at least an edge of the substrate. The ESD protection circuit is disposed in the edge of the substrate and electrically connected to a ground voltage, wherein a vertical projection of the testing line to the substrate and that of the ESD protection circuit to the substrate is at least partially overlapped. The first isolation layer is disposed between the testing line and the ESD protection circuit.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 6, 2016
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Chi Chen, Chia-Chun Yeh, Chien-Yu Chen, Yi-Ling Lin, Yi-Hsin Lin
  • Patent number: 9419378
    Abstract: Electrical connectors, electrical modules, and systems are provided. In one aspect, an electrical connector includes a housing defining a side surface, an electrical conductor supported by the housing and including an engagement portion proximate the side surface of the housing. The engagement portion is adapted to engage another electrical conductor of another electrical connector. The connector also includes a magnet supported by the housing proximate the side surface of the housing, a projection extending from the side surface of the housing, and a receptacle defined in the side surface of the housing. In other aspects, an electrical module includes at least one of these electrical connectors. In further aspects, a system includes a plurality of these modules and the modules are selectively couplable together.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 16, 2016
    Assignee: littleBits Electronics Inc.
    Inventor: Aya Bdeir
  • Patent number: 9380696
    Abstract: A flexible printed circuit board having a copper foil character with good visibility and without copper foil pattern peeling. The flexible printed circuit board has a base material having optical transparency, a wiring pattern formed on one surface of the base material; a first opaque cover lay film covering a surface of the wiring pattern, a character formed on the other surface of the base material; and a second opaque cover lay film covering a surface of the character. The first opaque cover lay film has an opening portion is formed therein, and the character is formed so as to be visually recognizable through the opening portion.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 28, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Shinsaku Watanabe
  • Patent number: 9312633
    Abstract: A connector for an electronic device has a housing with a peripheral surface and guides defining first and second paths. The second path extends from a first location proximate the peripheral surface to a second location farther from the peripheral surface and closer to the first path. A magnetic contact assembly in the housing is magnetically movable along the first path between a first position for joining the connector in data communication with an adjacent connector, and a second position withdrawn from the peripheral surface. A magnet in the housing and is movable by attraction to an adjacent connector along the second path, to magnetically hold the connector to an adjacent connector. The guides are configured so that the magnet and the magnetic contact assembly magnetically bias one another inwardly along the first and second paths.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: April 12, 2016
    Assignee: Nanoport Technology Inc.
    Inventors: Timothy Jing Yin Szeto, Jeremy Zhi-Qiao Chan
  • Patent number: 9312587
    Abstract: A common mode filter a manufacturing method thereof are disclosed. The common mode filter in accordance with an embodiment of the present invention includes: a magnetic substrate; a receiving groove formed on the magnetic substrate; a dielectric layer formed in the receiving groove and having a coil pattern included therein; and a magnetic layer formed on upper surfaces of the dielectric layer and the magnetic substrate.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 12, 2016
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hong-Ryul Lee, Young-Do Kweon, Sang-Moon Lee
  • Patent number: 9277655
    Abstract: A combined wiring board includes a wiring board set having multiple wiring boards and one or more adhesive agent portions such that the wiring boards are connected each other by the adhesive agent portion or adhesive agent portions, and a metal frame having an accommodation opening portion formed to accommodate the wiring board set such that the wiring board set is positioned in the accommodation opening portion of the metal frame.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: March 1, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Michimasa Takahashi
  • Patent number: 9277650
    Abstract: A combined wiring board includes multiple wiring boards, and a connected metal frame having multiple metal frames and one or more connecting portions such that the metal frames are connected each other by the connecting portion or connecting portions and have accommodation opening portions formed to accommodate the wiring boards, respectively.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: March 1, 2016
    Assignee: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Michimasa Takahashi
  • Patent number: 9232681
    Abstract: A multi-chip socket includes a first cavity having a first support surface to support a first component including a first chip, the first support surface arranged to contact and support the first chip. A second cavity has a second support surface to support a second component including a second chip, the second support surface arranged to contact and support the second chip. The first support surface is in a first plane, and the second support surface is in a second plane, where the first plane is angled with respect to the second plane.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: January 5, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kevin B. Leigh, George D. Megason
  • Patent number: 9214403
    Abstract: A stacked semiconductor package including a first printed circuit board and a second printed circuit board is provided. The first printed circuit board may include a first surface upon which a first semiconductor chip is mounted and a second surface upon which at least one connecting structure is attached. The first printed circuit board may further include at least one thermal via and a heat sink and the at least one thermal via and the heat sink may be disposed under the first semiconductor chip with the heat sink being disposed between the first surface and the second surface. The second printed circuit board may include a third surface upon which a second semiconductor chip is mounted. The second printed circuit board may be disposed under the first printed circuit board with the at least one connecting structure connecting the first printed circuit board to the second printed circuit board.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: December 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-Chan Lee
  • Patent number: 9199836
    Abstract: In a method of manufacturing a semiconductor integrated circuit device having an MEMS element over a single semiconductor chip, the movable part of the MEMS element is fixed before the formation of a rewiring. After formation of the rewiring, the wafer is diced. Then, the movable part of the MEMS element is released by etching the wafer.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: December 1, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Arai
  • Patent number: 9190396
    Abstract: A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: November 17, 2015
    Assignee: NVIDIA Corporation
    Inventors: Donald E. Templeton, Brian S. Schieck
  • Patent number: 9190380
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 17, 2015
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Chia-Pin Chiu
  • Patent number: 9190367
    Abstract: The semiconductor package includes a substrate, a plurality of components, an interposer, an electrical interconnect and a first package body. The substrate has a first surface and a second surface opposite to the first surface. A first component is mounted on the first surface of the substrate, and a second component is mounted on the second surface of the substrate. The interposer has a first surface. The electrical interconnect connects the first surface of the interposer to the second surface of the substrate. The first package body is disposed on the second surface of the substrate and encapsulates the second component, the electrical interconnect and at least a portion of the interposer.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: November 17, 2015
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuo Hsien Liao, Ming-Chiang Lee, Cheng-Nan Lin
  • Patent number: 9171816
    Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: October 27, 2015
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, Chia-Pin Chiu
  • Patent number: 9142486
    Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: September 22, 2015
    Inventors: Tsang-Yu Liu, Yi-Ming Chang, Tzu-Min Chen
  • Patent number: 9123763
    Abstract: A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Mirng-Ji Lii, Ming-Da Cheng, Chih-Wei Lin
  • Patent number: 9093295
    Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: July 28, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Young Kyu Song, Kyu-Pyung Hwang, Dong Wook Kim, Changhan Hobie Yun
  • Patent number: 9058927
    Abstract: A laminate formed by laminating a plurality of insulator layers. First coil conductors are provided in the laminate winding in a predetermined direction when viewed in a plan view in a direction of lamination. Second coil conductors are provided in the laminate on one side in the direction of lamination relative to the first coil conductors, winding in the predetermined direction when viewed in a plan view in the direction of lamination. First via-hole conductors connect downstream ends of the first parallel portion in the predetermined direction. Second via-hole conductors connect downstream ends of the second parallel portions in the predetermined direction. A third via-hole conductor connects the farthest of the first coil conductors on one side to the farthest of the second coil conductors on the other side in the direction of lamination. The first through third via-hole conductors are not connected in a series.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: June 16, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kaori Takezawa
  • Patent number: 9059490
    Abstract: Embodiments are directed to a transition structure for interfacing an integrated circuit chip and a substrate, comprising: a co-planar waveguide (CPW) structure formed based on ground-signal-ground (GSG) pads on the integrated circuit chip, a grounded co-planar waveguide (CPWG) structure coupled to the GSG pads, and a microstrip coupled to the CPWG structure.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: June 16, 2015
    Assignee: BlackBerry Limited
    Inventors: Christopher Andrew DeVries, Houssam Kanj, Morris Repeta, Huanhuan Gu
  • Patent number: 9042116
    Abstract: A printed circuit board includes a motherboard and a daughterboard. The motherboard includes at least one first signal pad and defines at least one via under the at least one first signal pad. The daughterboard includes at least one second signal pad and defines at least one via under the at least one second signal pad. The at least one first signal pad and the at least one second signal pad are sucked into the respective vias on the motherboard and the daughterboard according to siphon principle to allow each of the first signal pads and the second signal pads to form uneven top surfaces, the uneven top surfaces of the at least one first signal pads and the at least one second signal pads are connected to each other for electronically connecting the daughterboard to the motherboard.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: May 26, 2015
    Assignees: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Kuan Wu, Hou-Yuan Chou
  • Patent number: 9030838
    Abstract: Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se-Ho You, Heeseok Lee, Chiyoung Lee, Yun-Hee Lee
  • Patent number: 9025341
    Abstract: A power module includes a power module body portion and a wiring board. The power module body portion includes P-side semiconductor elements and N-side semiconductor elements, and a P-side terminal connection portion, a U-phase terminal connection portion, and an N-side terminal connection portion which establish electrical connection with the wiring board on an upper surface of the power module body portion and into which a current flows from the wiring board and from which a current flows to the wiring board.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventor: Yasuhiko Kawanami
  • Patent number: 9019709
    Abstract: A protection circuit board is disclosed. The protection circuit board includes a main printed circuit board and an auxiliary printed circuit board. In the auxiliary printed circuit board, a thermistor is electrically interposed between an external electrode terminal and auxiliary electrodes.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: April 28, 2015
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Young-Cheol Jang
  • Patent number: 9019718
    Abstract: Electrical connectors, electrical modules, and systems are provided. In one aspect, an electrical connector includes a housing defining a side surface, an electrical conductor supported by the housing and including an engagement portion proximate the side surface of the housing. The engagement portion is adapted to engage another electrical conductor of another electrical connector. The connector also includes a magnet supported by the housing proximate the side surface of the housing, a projection extending from the side surface of the housing, and a receptacle defined in the side surface of the housing. In other aspects, an electrical module includes at least one of these electrical connectors. In further aspects, a system includes a plurality of these modules and the modules are selectively couplable together.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 28, 2015
    Assignee: littleBits Electronics Inc.
    Inventor: Aya Bdeir
  • Patent number: 9000306
    Abstract: An electronic apparatus (100) has an electronic device (151), a power supply plane (121) and a power supply plane (122) disposed with a gap (123) therebetween, a connection member (152) that electrically connects the power supply plane (122) and the electronic device (151), a ground plane (141) facing the power supply plane (121) or the power supply plane (122), a connection member (153) that electrically connects the ground plane (141) and the electronic device (151), a plurality of conductor elements (131) that is repeatedly arrayed, and open stubs (111) formed at a location overlapping the gap (123) included in an area surrounded by the conductor elements (131). In addition, at least some of the open stubs (111) face the power supply plane (122) which is not in contact with the open stubs (111).
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: April 7, 2015
    Assignee: NEC Corporation
    Inventors: Hiroshi Toyao, Manabu Kusumoto, Naoki Kobayashi, Noriaki Ando
  • Patent number: 8995143
    Abstract: A pivotal assembly applied to a board includes a first board, a first pivotal member, and a pivotal plate. The first pivotal member is fixed to the first board and has a first retaining structure. The pivotal plate is pivotally connected to the first pivotal member and has a first protrusion. The first protrusion is retained in the first retaining structure, so as to make the first board limitedly rotate to be perpendicular or parallel to the pivotal plate.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 31, 2015
    Assignees: Inventec (Pudong) Technology Corporation, Inventec Corporation
    Inventor: Yen-Cheng Lin
  • Patent number: 8978245
    Abstract: A method includes securing a midplane to a bracket disposed between a first and second ends of a chassis, wherein a first surface of the midplane engages the bracket and faces the first end of the chassis. A first electronic device is secured within the first end of the chassis with a first device connector coupled to a first midplane connector on the first surface of the midplane and a first device latch secured directly to a first slot in the chassis adjacent the first end. A sub-chassis is secured within the second end of the chassis, wherein the sub-chassis has a proximal end that engages a second surface of the midplane. Furthermore, a second electronic device is secured within the sub-chassis with a second device connector coupled to a second midplane connector on the second surface of the midplane and a second device latch secured directly to a slot in the sub-chassis adjacent the distal end of the sub-chassis.
    Type: Grant
    Filed: December 30, 2012
    Date of Patent: March 17, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Karl K. Dittus, David J. Jensen, Brian A. Trumbo
  • Publication number: 20150062855
    Abstract: A hybrid circuit assembly includes an integrated metal substrate (IMS) having high-voltage, high-power components mounted thereon. The IMS includes a metal base plate an insulating adhesive on the metal base plate, and one or more wiring layers on the insulating adhesive. The hybrid circuit assembly includes a multi-layer printed wiring board (PWB) having low-voltage, low-power components mounted thereon. The multi-layer PWB is connected to the IMS and has an upper surface that is co-planar with an upper surface of the IMS. The PWB is mounted on the metal base plate via the insulating adhesive.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: RAYTHEON COMPANY
    Inventors: Peter D. Morico, John D. Walker
  • Patent number: 8964219
    Abstract: An image forming apparatus includes an installation section, a control board, a first connection terminal provided on an outer surface of the control board, a first electrical connection member provided on the installation section and electrically connected to a point of reference potential, a substrate installable in the installation section in a thickness direction of the control board, an external connection terminal provided on the substrate and externally exposed, a second connection terminal provided on a first surface of the substrate and connected to the first connection terminal when the substrate is installed into the installation section, and a second electrical connection member provided on a second surface of the substrate. The second electrical connection member makes contact with the first electrical connection member and is electrically connected to the point of reference potential via the first electrical connection member when the substrate is installed into the installation section.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: February 24, 2015
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Tetsuo Ishizuka
  • Patent number: 8958214
    Abstract: Mechanisms for interconnecting and distributing signals and power between PCBs are provided. A first PCB having land grid arrays (LGAs) and a first wiring layer designed for interconnect components on the first PCB, and a second wiring layer for connecting the components to a second PCB, are provided. The second PCB has opposed parallel first and second surfaces, the first surface having a LGA. A wiring layer designed to interconnect components on the second PCB, and a layer for interconnecting the components on the second PCB with the components on the first PCB, are provided. A first interposer couples to a LGA of a first surface of the first PCB and connects a component to the first PCB. A second interposer is sandwiched between and couples to a LGA of a second surface of the first PCB and to the LGA of the first surface of the second PCB.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: John L. Colbert, Arvind K. Sinha, Roger D. Weekly
  • Patent number: 8952265
    Abstract: An EMI noise reduction package board, having a top layer and a bottom layer, one of which having a semiconductor device mounted thereon, can include: a first area having a signal layer arranged on one surface thereof; and a second area placed on a lateral side of the first area and having unit structures arranged repeatedly therein, the unit structures configured for inhibiting EMI noise from being radiated to an outside through the lateral side of the first area. The unit structure can include: a top conductive plate and a bottom conductive plate, formed, respectively, on the top layer and the bottom layer of the second area to face each other in a pair; and a via, connecting the top conductive plate with the bottom conductive plate.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Han Kim, Dae-Hyun Park, Young-Min Ban
  • Patent number: 8946892
    Abstract: A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yonghoon Kim, Jihyun Lee
  • Patent number: 8942005
    Abstract: An electronics module is provided for utilization onboard an airborne object. In one embodiment, the electronics module includes a housing having a cavity therein, a first printed circuit board (PCB) disposed in the cavity, a second PCB disposed in the cavity above the first PCB, and a supportive interconnect structure. The supportive interconnect structure includes a substantially annular insulative body and a plurality of vias. The substantially annular insulative body extends around an inner circumferential portion of the housing between the first PCB and the second PCB to support the second PCB and to axially space the second PCB from the first PCB. The plurality of vias is formed through the substantially annular insulative body and electrically couples the first PCB to the second PCB.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: January 27, 2015
    Assignee: Raytheon Company
    Inventor: Chris E. Geswender
  • Publication number: 20150022990
    Abstract: Two system boards may be connected by a blind plug connector assembly. The top system board supports a first connector and has a hole adjacent the first connector that secures a guide bracket. The blind plug connector assembly is selectively received in the guide bracket to position a proximal connector on the assembly for connecting to the first connector on the top system board and position a distal connector on the assembly for connecting to a second connector on the lower system board. A flexible wired connection extends within the assembly between the proximal connector and the distal connector, and may form a scalability cable. The interaction between the assembly and the guide bracket provide alignment of the connectors.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 22, 2015
    Inventors: Michael D. French, JR., Edward J. McNulty, Tony C. Sass, Paul A. Wormsbecher
  • Patent number: 8934261
    Abstract: High density electronic device assemblies and techniques for forming high density electronic device assemblies are disclosed. These assemblies and techniques can be used to form compact electronic devices. In one embodiment, substrate arrangements that include a multiple-part substrate can be used to form a high density electronic device assembly. In another embodiment, one or more clips can be used in a high density electronic device assembly to provide mechanical and electrical interconnection between electrical structures that are to be removably coupled together as parts of the high density electronic device assembly. In still another embodiment, a removable cap (and a method for forming the removable cap) can be used for an electronic device housing.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 13, 2015
    Assignee: Apple Inc.
    Inventors: Wey-Jiun Lin, Kevin Pan, Conrado Sacluti de la Cruz
  • Patent number: 8934262
    Abstract: A wiring board including a first rigid wiring board having an accommodation portion and a conductor, a second rigid wiring board accommodated in the accommodation portion of the first rigid wiring board and having a conductor electrically connected to the conductor of the first rigid wiring board, and an insulation layer formed on the first rigid wiring board and the second rigid wiring board. The accommodation portion of the first rigid wiring board has wall surfaces tapering from a first surface of the first rigid wiring board to a second surface on the opposite side of the first surface, and the second rigid wiring board has side surfaces tapering such that the side surfaces of the second rigid wiring board substantially fit into the wall surfaces of the accommodation portion of the first rigid wiring board.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: January 13, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Masakazu Aoyama, Hidetoshi Noguchi
  • Patent number: 8928114
    Abstract: A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Patent number: 8923011
    Abstract: A combination of an interconnect board and a module board for connecting a plurality of electronic modules to a processing unit is described. The interconnect board comprises a plurality of interconnect data lines connected between a plurality of interconnect board input terminals and interconnect board output terminals. The module board comprises at least one electronic module connected to a module connection input terminal, a plurality of module board data lines connected between a plurality of module board input terminals and a plurality of module board output terminals, and an unconnected module board output terminal. A first one of the interconnect board output terminals is connectable to the module connection input terminal, and the unconnected module board output terminal is connectable to one of the interconnect board input terminals.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: December 30, 2014
    Assignee: Kathrein-Werke KG
    Inventors: Lothar Schmidt, Christoph Kutscher
  • Patent number: 8923003
    Abstract: An electronic device may contain components such as flexible printed circuits and rigid printed circuits. Electrical contact pads on a flexible printed circuit may be coupled electrical contact pads on a rigid printed circuit using a coupling member. The coupling member may be configured to electrically couple contact pads on a top surface of the flexible circuit to contact pads on a top surface of the rigid circuit. The coupling member may be configured to bear against a top surface of the flexible circuit so that pads on a bottom surface of the flexible circuit rest against pads on a top surface of the rigid circuit. The coupling member may bear against the top surface of the flexible circuit. The coupling member may include protrusions that extend into openings in the rigid printed circuit. The protrusions may be engaged with engagement members in the openings.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: December 30, 2014
    Assignee: Apple Inc.
    Inventors: Alexander D. Schlaupitz, Joshua G. Wurzel
  • Publication number: 20140362553
    Abstract: A reconfigurable advanced rapid-prototyping environment (RARE) solution provides a three-dimensional (x, y, z) interconnection fabric that is a modular, reconfigurable, fully scalable high performance computing architecture. RARE allows processing nodes (modules) to communicate with other processing nodes (modules) in a three-dimensional mesh architecture where every processing node (module) has access to all other nodes (modules) in the system. The RARE architecture is a modular form-factor design which is fully stand-alone. It does not require the use of a backplane or chassis infrastructure for connectivity. RARE is widely scalable and provides full cross-channel communication in all three dimensions (x, y, z). RARE yields a scalable and morphable hardware architecture for a processing system where the system can scale by one module at a time without limit and it can take on any shape and those shapes can be easily changed.
    Type: Application
    Filed: June 6, 2013
    Publication date: December 11, 2014
    Inventor: Lawrence James Scally
  • Patent number: 8898362
    Abstract: A lane jumper for transmitting at least one lane from a first interface to a second interface is disclosed. The at least one lane is connected with the first interface. The first interface defines a first pin group and a second pin group, and the second interface defines a third pin group connected with the second pin group. The lane jumper includes a fourth pin group and a fifth pin group, wherein the fourth pin group and the fifth pin group of the lane jumper are configured for being respectively connected with the first pin group and the second pin group. The at least one lane is transmitted from the first interface to the second interface sequentially through the first pin group, the fourth pin group, the fifth pin group, the second pin group, and the third pin group.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: November 25, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Zheng-Heng Sun