Abstract: A circuit module includes: a multilayer board having a plurality of first through-holes each penetrating at least one layer thereof; a plurality of high frequency components disposed in the plurality of first through-holes, respectively; and a plurality of shield parts individually surrounding the plurality of high frequency components. The multilayer board has a second through-hole penetrating at least a layer in which each high frequency component is disposed. Each of the plurality of shield parts includes a first conductor, a second conductor, and a third conductor. The first conductor and the second conductor sandwich the high frequency component in a lamination direction of the multilayer board. The third conductor is disposed in the second through-hole.

Abstract: A method and apparatus for multiple flexible circuit cable attachment is described herein. Gold bumps are bonded on interconnection pads of a substrate to create a columnar structure and solder or conductive epoxy is dispensed on the flexible cable circuit. The substrate and flexible cable circuit are aligned and pressed together using force or placement of a weight on either the substrate or flexible cable circuit. Appropriate heat is applied to reflow the solder or cure the epoxy. The solder wets to the substrate pads, assisted by the gold bumps, and have reduced bridging risk due to the columnar structure. A nonconductive underfill epoxy is applied to increase mechanical strength.

Abstract: An information handling system includes a printed circuit board, a surface mount connector including first and second surface mount connector portions, first and second different pairs, and a ground plane. The first and second surface mount connector portions are mounted on the printed circuit board. The first differential pair is located on the first surface mount connector portion, and the second differential pair is located on the second surface mount connector portion. The ground plane is located in between the first and second surface mount connector portions within the printed circuit board. The first ground via is in physical communication with the ground plane and a first ground pad on a surface of the printed circuit board. The second ground via is in physical communication with the ground plane and a second ground pad on the surface of the printed circuit board.

Abstract: An enclosed electrical device such as a battery pack for an electric powertrain system includes an enclosure having a tray and cover. The tray and cover together define an enclosure cavity. A radio frequency (RF) receiving node is located within the cavity. Printed circuit board assemblies (PCBAs) include an RF transmitting node. The PCBAs(s) are spaced apart from one another within the cavity. An RF shield guide layer is positioned between the PCBAs and the cover, such that the RF shield guide layer covers the PCBAs without covering the RF transmitting node. A battery pack and an electric powertrain system include the RF shield guide layer.

Abstract: A printed circuit board may include a top side, a bottom side, and a circumferential surface that connects the top side to the bottom side. The circumferential surface may have a toothing for forming a gear wheel. The toothing may be circumferentially closed and may be arranged over an entire surface area of the circumferential surface. The toothing may be configured as an involute toothing, an epicycloid toothing, a hypocycloid toothing, or a lantern gear toothing. The printed circuit board may be formed of fiber-reinforced plastic. Further, the printed circuit board may include a track, a surface structure, and/or a conductor track configured for inductive sampling, capacitive sampling, optical sampling, and/or acoustic sampling.

Abstract: A printed wiring board includes a lower layer including conductor layers and insulating layers, a conductor layer formed on the outermost insulating layer in the lower layer, and a solder resist layer formed on the conductor layer such that the solder resist layer is covering the conductor layer on the outermost insulating layer, and a two-dimensional code structure formed on the lower layer and including the conductor layer and a portion of the solder resist layer such that the portion of the solder resist layer has openings forming exposed portions of the conductor layer and that the openings of the solder resist layer and the exposed portions of the conductor layer form the two-dimensional code structure. The conductor layer includes a portion corresponding to the two-dimensional code structure such that the portion of the conductor layer has a residual copper rate that allows the two-dimensional code structure to be read.

Abstract: According to various aspects, exemplary embodiments are disclosed of board level shield (BLS) frames or fences including pickup members with pickup areas. In exemplary embodiments, the pickup member may be configured such that the pickup area is allowed to rotate in place when the pickup member is drawn to raise the pickup area.

Abstract: A storage system, blades, removable modules, and method of configuring a storage system are described. The storage system has blades with computing resources and storage resources. At least one of the blades has, or has added, one or more removable modules.

Abstract: Provided is a circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate is disposed between the second substrate and the fourth substrate. The third substrate has an opening penetrating the third substrate and includes a first dielectric layer filling the opening. The conductive via structure penetrates the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate, and is electrically connected to the first substrate and the fourth substrate to define a signal path. The first substrate, the second substrate, the third substrate and the fourth substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.

Abstract: A module assembly is attached on a headlining of a vehicle and includes a base where an upper portion thereof is open, a first printed circuit board (PCB) and a second PCB sequentially stacked on a plurality of supporting pillars extending in a vertical direction to an inner bottom surface of the base and electrically connected to each other by a flexible cable, and a cover assembled with the base to cover the first and second PCBs stacked on the base.

Abstract: A harness connector for an electronics device is disclosed, the electronics device having a housing and a printed circuit board disposed in the housing, and the housing including an opening exposing electrical contacts of the printed circuit board. The harness connector includes a base member with a plurality of apertures defined therein, the base member directly attached to the housing and disposed over the opening, and a plurality electrical contacts electrically connected to the electrical contacts of the printed circuit board.

Abstract: Disclosed herein is an electronic component that includes a substrate and a plurality of conductive layers and a plurality of insulating layers which are alternately laminated on the substrate. The side surface of at least one of the plurality of insulating layers has a recessed part set back from a side surface of the substrate and a projecting part projecting from the recessed part.

Abstract: A method of manufacturing copper powder according to the present invention includes: a first step of reducing copper particles in water by using at least one compound selected from the group consisting of potassium borohydride, sodiumborohydride, and lithium borohydride; after the first step, a second step of washing with water; a third step of washing copper powder obtained in the second step with at least one compound selected from the group consisting of ether compounds and alcohol compounds; and a fourth step of bringing the copper powder obtained in the third step into contact with an organic acid solution, in which at least one compound selected from the group consisting of ether compounds and alcohol compounds is used as a solvent.

Abstract: In an electrical connection device in which a adhesive layer is disposed on a flexible base and a conductor pattern is provided on the adhesive layer, an elastomer pattern obtained by curing an ink containing an elastomer composition is formed on the adhesive layer, the conductor pattern obtained by curing an ink containing a conductive particle is formed on the elastomer pattern, and a longitudinal elastic modulus of the elastomer pattern is set to be larger than a longitudinal elastic modulus of the adhesive layer.

Abstract: An electronic device including a shielding structure is provided. The electronic device includes a housing, a first board disposed in an inner space of the housing and including a first electrical element and a first ground layer, a second board disposed in the inner space to be spaced apart from the first board and including a second electrical element, and an interposer disposed between the first board and the second board so as to electrically connect the first board and the second board to each other. The second board includes a first surface facing the first board, a second surface facing away from the first surface, insulating layers disposed between the first surface and the second surface, first slits formed at a predetermined interval in a first conductive area disposed in a first insulating layer among the insulating layers, and second slits formed at a predetermined interval in a second conductive area disposed in a second insulating layer between the first insulating layer and the second surface.

Abstract: A semiconductor device package includes a semiconductor chip mounted to an upper surface of a package substrate by a package ball. The package substrate includes a ball pad on the upper surface of the package substrate and connected to the package ball, a signal trace located below the upper surface of the package substrate, and an impedance matching element connected between the ball pad and the signal trace. The impedance matching element is configured to establish impedance matching with a termination impedance of the semiconductor chip.

Abstract: Disclosed are an array substrate and a display panel formed by cutting the array substrate, the array substrate includes a substrate body, a first test line, a second test line, and a cutting line; the substrate body includes a plurality of display units and a cutting area located between the plurality of display units; the first test line and the second test line are disposed in the cutting area; the first test line is disposed across the second test line and insulated from each other; the first test line and/or the second test line includes a bending segment disposed across the cutting line.

Abstract: A printed wiring board includes: an inner insulating layer including a conductive wire; a first outermost insulating layer disposed on a first surface of the inner insulating layer; and a second outermost insulating layer disposed on a second surface of the inner insulating layer. A bending elastic modulus of each of the first outermost insulating layer and the second outermost insulating layer ranges from ¼ to ¾, inclusive, of a bending elastic modulus of the inner insulating layer. A glass transition temperature of each of the first outermost insulating layer and the second outermost insulating layer falls within ±20° C. of a glass transition temperature of the inner insulating layer.

Abstract: A multilayer substrate includes a stacked body including first and second flexible insulating base material layers, and an actuator conductor pattern on at least the first insulating base material layer. The stacked body includes a first region including stacked first and second insulating base material layers, and a second region including stacked second insulating base material layers. The first region includes an actuator function portion in a portion thereof, the actuator function portion including the actuator conductor pattern. The thickness of the first insulating base material layer including the actuator conductor pattern is smaller than the thickness of one second insulating base material layer.

Abstract: In some embodiments, an interconnectable circuit board may include one or more of the following features: (a) a first electrically conductive pad located on a top of the circuit board, (b) a plated through hole on the conductive pad which passes through the circuit board, (c) a second electrically conductive pad coupled to the plated through hole; the second conductive pad capable of being electrically connected to a third electrically conductive pad attached to a top of a second interconnectable circuit board, (d) cut marks indicating safe locations for separating the circuit board, and (e) a second cut mark adjacent to the first cut mark where the area between the first and second cut mark can be utilized to make a safe cut through the circuit board.

Abstract: A device includes a package component comprising a substrate and a plurality of bumps formed on the substrate, a semiconductor die on the substrate, a dielectric layer over the substrate, wherein a top surface of the dielectric layer is level with a top surface of the semiconductor die, and a sidewall of the dielectric layer includes a slope portion and a vertical portion and a top package bonded on the package component, wherein the semiconductor die is located between the top package and the substrate.

Abstract: An electronic device includes a circuit board and an electronic element. The circuit board includes a plate body and multiple through holes extending through the plate body. Each of the through holes has a first diameter. The electronic element includes multiple pins, each of which is inserted into a respective one of the through holes, is secured to the circuit board by a soldering process, and has a second diameter smaller than the first diameter of the respective one of the through holes. For each of the pins, a difference between the second diameter of the pin and the first diameter of the respective one of the through holes ranges from 0.4 mm to 0.6 mm. A method for manufacturing the electronic device is also provided.

Abstract: In one embodiment, an apparatus includes a plurality of layers in a printed circuit board comprising at least one power plane and at least one ground plane, and a plurality of vias extending through the plurality of layers and connecting two or more of the layers, the plurality of vias comprising at least one pair of differential signal vias and at least one pair of power vias, the signal vias and power vias surrounded by a plurality of ground vias. The ground plane includes an anti-pad formed therein by an opening defined by removal of material, with the pair of differential signal vias and pair of power vias extending through the anti-pad in the ground plane to reduce power via resonance.

Abstract: An integrated circuit package and manufacturing method thereof are described. The integrated circuit package includes pin up conductive plating to form an interconnect, where an opening on a patterned fifth layer photo-resist material located at bottom portion of a base developed for etching selectively the base to form at least an internal opening and at least a positioning opening, wherein the internal opening corresponds with an inside area of a first patterned conductive layer, and the positioning opening corresponds with an outside area of the first patterned conductive layer.

Abstract: Provided are a module assembly, a connector, and an electronic device, the module assembly including a first module that includes a pin configured to selectively protrude from a side thereof, a pin installation portion in which the pin is installed to be movable, and a first magnet configured to attract the pin into the pin installation portion, a second module to be coupled to the first module, the second module including a pin receiver configured to receive the pin when the pin protrudes from the first module, and a second magnet configured to attract the pin into the pin receiver, wherein the second magnet is configured to apply, to the pin, a greater magnitude of magnetic force than the first magnet in a case in which a distance between the first module and the second module is less than a preset distance.

Abstract: A circuit module includes a circuit board and electronic components mounted on the circuit board. The mounted electronic components include at least one discrimination-target electronic component and at least one module-discrimination electronic component. In addition, the circuit board includes land electrodes allowing the module-discrimination electronic component to be mounted at different positions and/or orientations with respect to the circuit board, and the module-discrimination electronic component is mounted at any one position and/or orientation among different positions and/or orientations with respect to the circuit board in accordance with the type of the discrimination-target electronic component.

Abstract: A liquid ejection device includes a switching circuit. The switching circuit includes: a multilayer wiring board including a first wiring layer and a second wiring layer; a first transistor and a second transistor mounted on the first wiring layer side of the multilayer wiring board; and a capacitor mounted on the second wiring layer side of the multilayer wiring board. When the multilayer wiring board is viewed in a plan view, a third via conductor is arranged in an area not overlapping a straight-line path connecting a source electrode of the first transistor with a drain electrode of the second transistor in a second wire.

Abstract: A semiconductor device includes a semiconductor module that has an electrode terminal projecting externally; a substrate that has a through hole or a cut-out for inserting the electrode terminal; and a guide member that is provided between the semiconductor module and the substrate and guides the electrode terminal in such a manner that the electrode terminal is inserted into the through hole or the cut-out. The guide member becomes out of contact with the electrode terminal after the electrode terminal is inserted into the through hole or the cut-out.

Abstract: A touch panel including a substrate, at least one touch-sensing unit, at least one connecting pad, at least a testing line, at least one ESD protection circuit, and a first isolation layer is provided. The touch-sensing unit is disposed on the substrate. The connecting pad is disposed on the substrate and electrically connected to the touch-sensing unit. The testing line is disposed on the substrate, electrically connected to the connecting pad, and extends to at least an edge of the substrate. The ESD protection circuit is disposed in the edge of the substrate and electrically connected to a ground voltage, wherein a vertical projection of the testing line to the substrate and that of the ESD protection circuit to the substrate is at least partially overlapped. The first isolation layer is disposed between the testing line and the ESD protection circuit.

Abstract: Electrical connectors, electrical modules, and systems are provided. In one aspect, an electrical connector includes a housing defining a side surface, an electrical conductor supported by the housing and including an engagement portion proximate the side surface of the housing. The engagement portion is adapted to engage another electrical conductor of another electrical connector. The connector also includes a magnet supported by the housing proximate the side surface of the housing, a projection extending from the side surface of the housing, and a receptacle defined in the side surface of the housing. In other aspects, an electrical module includes at least one of these electrical connectors. In further aspects, a system includes a plurality of these modules and the modules are selectively couplable together.

Abstract: A flexible printed circuit board having a copper foil character with good visibility and without copper foil pattern peeling. The flexible printed circuit board has a base material having optical transparency, a wiring pattern formed on one surface of the base material; a first opaque cover lay film covering a surface of the wiring pattern, a character formed on the other surface of the base material; and a second opaque cover lay film covering a surface of the character. The first opaque cover lay film has an opening portion is formed therein, and the character is formed so as to be visually recognizable through the opening portion.

Abstract: A connector for an electronic device has a housing with a peripheral surface and guides defining first and second paths. The second path extends from a first location proximate the peripheral surface to a second location farther from the peripheral surface and closer to the first path. A magnetic contact assembly in the housing is magnetically movable along the first path between a first position for joining the connector in data communication with an adjacent connector, and a second position withdrawn from the peripheral surface. A magnet in the housing and is movable by attraction to an adjacent connector along the second path, to magnetically hold the connector to an adjacent connector. The guides are configured so that the magnet and the magnetic contact assembly magnetically bias one another inwardly along the first and second paths.

Abstract: A common mode filter a manufacturing method thereof are disclosed. The common mode filter in accordance with an embodiment of the present invention includes: a magnetic substrate; a receiving groove formed on the magnetic substrate; a dielectric layer formed in the receiving groove and having a coil pattern included therein; and a magnetic layer formed on upper surfaces of the dielectric layer and the magnetic substrate.

Abstract: A combined wiring board includes a wiring board set having multiple wiring boards and one or more adhesive agent portions such that the wiring boards are connected each other by the adhesive agent portion or adhesive agent portions, and a metal frame having an accommodation opening portion formed to accommodate the wiring board set such that the wiring board set is positioned in the accommodation opening portion of the metal frame.

Abstract: A combined wiring board includes multiple wiring boards, and a connected metal frame having multiple metal frames and one or more connecting portions such that the metal frames are connected each other by the connecting portion or connecting portions and have accommodation opening portions formed to accommodate the wiring boards, respectively.

Abstract: A multi-chip socket includes a first cavity having a first support surface to support a first component including a first chip, the first support surface arranged to contact and support the first chip. A second cavity has a second support surface to support a second component including a second chip, the second support surface arranged to contact and support the second chip. The first support surface is in a first plane, and the second support surface is in a second plane, where the first plane is angled with respect to the second plane.

Abstract: A stacked semiconductor package including a first printed circuit board and a second printed circuit board is provided. The first printed circuit board may include a first surface upon which a first semiconductor chip is mounted and a second surface upon which at least one connecting structure is attached. The first printed circuit board may further include at least one thermal via and a heat sink and the at least one thermal via and the heat sink may be disposed under the first semiconductor chip with the heat sink being disposed between the first surface and the second surface. The second printed circuit board may include a third surface upon which a second semiconductor chip is mounted. The second printed circuit board may be disposed under the first printed circuit board with the at least one connecting structure connecting the first printed circuit board to the second printed circuit board.

Abstract: In a method of manufacturing a semiconductor integrated circuit device having an MEMS element over a single semiconductor chip, the movable part of the MEMS element is fixed before the formation of a rewiring. After formation of the rewiring, the wafer is diced. Then, the movable part of the MEMS element is released by etching the wafer.

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract: A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system.

Abstract: The semiconductor package includes a substrate, a plurality of components, an interposer, an electrical interconnect and a first package body. The substrate has a first surface and a second surface opposite to the first surface. A first component is mounted on the first surface of the substrate, and a second component is mounted on the second surface of the substrate. The interposer has a first surface. The electrical interconnect connects the first surface of the interposer to the second surface of the substrate. The first package body is disposed on the second surface of the substrate and encapsulates the second component, the electrical interconnect and at least a portion of the interposer.

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.

Abstract: A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL.

Abstract: A multilayer capacitor is provided that includes a plurality of vias configured to receive interconnects from a die.

Abstract: A laminate formed by laminating a plurality of insulator layers. First coil conductors are provided in the laminate winding in a predetermined direction when viewed in a plan view in a direction of lamination. Second coil conductors are provided in the laminate on one side in the direction of lamination relative to the first coil conductors, winding in the predetermined direction when viewed in a plan view in the direction of lamination. First via-hole conductors connect downstream ends of the first parallel portion in the predetermined direction. Second via-hole conductors connect downstream ends of the second parallel portions in the predetermined direction. A third via-hole conductor connects the farthest of the first coil conductors on one side to the farthest of the second coil conductors on the other side in the direction of lamination. The first through third via-hole conductors are not connected in a series.

Abstract: Embodiments are directed to a transition structure for interfacing an integrated circuit chip and a substrate, comprising: a co-planar waveguide (CPW) structure formed based on ground-signal-ground (GSG) pads on the integrated circuit chip, a grounded co-planar waveguide (CPWG) structure coupled to the GSG pads, and a microstrip coupled to the CPWG structure.

Abstract: A printed circuit board includes a motherboard and a daughterboard. The motherboard includes at least one first signal pad and defines at least one via under the at least one first signal pad. The daughterboard includes at least one second signal pad and defines at least one via under the at least one second signal pad. The at least one first signal pad and the at least one second signal pad are sucked into the respective vias on the motherboard and the daughterboard according to siphon principle to allow each of the first signal pads and the second signal pads to form uneven top surfaces, the uneven top surfaces of the at least one first signal pads and the at least one second signal pads are connected to each other for electronically connecting the daughterboard to the motherboard.

Abstract: Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.

Abstract: A power module includes a power module body portion and a wiring board. The power module body portion includes P-side semiconductor elements and N-side semiconductor elements, and a P-side terminal connection portion, a U-phase terminal connection portion, and an N-side terminal connection portion which establish electrical connection with the wiring board on an upper surface of the power module body portion and into which a current flows from the wiring board and from which a current flows to the wiring board.