Interconnection Details Patents (Class 361/803)
  • Patent number: 10354985
    Abstract: A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-Gi Chang, Dongwon Lee, Myung-Sung Kang, Hyein Yoo
  • Patent number: 10347864
    Abstract: A display device includes a display device, a window, and an adhesive material. The display panel includes a display area and a non-display area. The window is on the display panel. The adhesive material is between the display panel and the window. The window includes a base substrate and a blocking barrier. The base substrate includes a first area overlapping the display area, a second area overlapping the non-display area, and a third area protruding outwardly from the display panel. The blocking barrier is on the second area of the base substrate, includes convex patterns and an inner surface facing a central portion of the base substrate. The inner surface of the blocking barrier and the convex patterns contact the adhesive material.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jae Hong Kim
  • Patent number: 10342132
    Abstract: Embodiments of the present disclosure are directed towards a memory device insertable into a PCB, e.g., a motherboard of a computing device. In some embodiments, the memory device may include a first PCB having a first thickness, to house one or more memory modules disposed on at least one side of the first PCB. The memory device may further include a layer having a second thickness, which may be attached to the side of the first PCB in an area that is proximate to an edge of the first PCB, to form a memory device portion that may be insertable into a connector slot disposed on a second PCB. The insertable portion may have a thickness that comprises the first and second thicknesses, to fit into the connector slot of the second PCB. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Xiang Li, George Vergis, Slobodan Mrdjan
  • Patent number: 10248158
    Abstract: An enclosure assembly of a monitor device includes an enclosure cover having a cover wall extending substantially in a first plane between a plurality of sides, wherein the cover wall includes an interior surface and an opposing exterior surface. The enclosure assembly includes a first stiffener wing and a second stiffener wing each having one or more mounting portions spaced apart from one or more stiffener portions to define one or more wing body ribs, each mounting portion including a mounting surface opposing a corresponding portion of the interior surface of the cover wall. The first stiffener wing includes a first wing body that extends toward a first side of the enclosure cover, and the second stiffener wing includes a second wing body that extends to a second side of the enclosure cover. Additionally, a display and/or a base assembly may be mounted to the enclosure assembly.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 2, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Timothy M. Sullivan, James D. Wahl, Stephen A. Cummings, David P. Platt
  • Patent number: 10223955
    Abstract: A driving circuit and a liquid crystal display apparatus are provided. The driving circuit includes a printed circuit board, which includes a timing controller for providing a detection signal to a flexible connector, wherein the detection signal is used for testing connection reliability of the flexible connector, and a power chip tier detecting whether the detection signal returned from the flexible connector is received to obtain a detection result, and controlling power output based upon the detection result.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 5, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Mingliang Wang
  • Patent number: 10219375
    Abstract: A hybrid circuit assembly includes an integrated metal substrate (IMS) having high-voltage, high-power components mounted thereon. The IMS includes a metal base plate an insulating adhesive on the metal base plate, and one or more wiring layers on the insulating adhesive. The hybrid circuit assembly includes a multi-layer printed wiring board (PWB) having low-voltage, low-power components mounted thereon. The multi-layer PWB is connected to the IMS and has an upper surface that is co-planar with an upper surface of the IMS. The PWB is mounted on the metal base plate via the insulating adhesive.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: February 26, 2019
    Assignee: RAYTHEON COMPANY
    Inventors: Peter D. Morico, John D. Walker
  • Patent number: 10145517
    Abstract: The present invention relates generally to LED (light emitting diode) array assemblies, and more specifically, to hi-powered LED array assemblies which are compact, cost-effective and easily assembled, while still addressing the issue of thermal management in such systems. An improved LED array assembly is described which is compact, cost-effective and easily assembled, while still addressing the issue of thermal management. An exemplary LED assembly consists of four separate and independent printed circuit boards (PCBs) which are arranged in an elongated square prism on a base PCB to form a “tower”, the four PCBs being mechanically interconnected by means of complementary slots and tabs. Each of the vertically arranged PCBs supports and provides power to one or more LEDs. Other aspects of the invention are also described including a flared base, drainage openings, and retaining notches on the perimeter of the PCB tower.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: December 4, 2018
    Inventors: Umer Anwer, Jerico Wong
  • Patent number: 10079222
    Abstract: A POP structure includes a circuit board, a bottom package structure, a top package structure, and a metal frame structure. The circuit board has a plurality of signal pads and dummy pads. The dummy pads surround the signal pads. The bottom package structure is disposed over the circuit board. The bottom package structure is electrically connected to the signal pads. The top package structure is disposed over the bottom package structure. The top package structure is electrically connected to the bottom package structure. The metal frame structure includes a body and a plurality of terminal pins. The body is located between the top package structure and the bottom package structure. The terminal pins extend outward from an edge of the top package structure to connect the top package structure and the dummy pads of the circuit board.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: September 18, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Chien-Wei Chou, Yong-Cheng Chuang
  • Patent number: 10021816
    Abstract: A three-dimensional arrangement for a power converter device, e.g., an inverter or a rectifier, is provided. The switching elements, activation electronics, the load connections of the power converter device are arranged on a carrier device in such a way that defines especially short conduction paths. The components of the power converter device (e.g., all required components), such as switching elements, control electronics, and load connections, are arranged on a common carrier device. The carrier device is simultaneously used as a cooling device for the entire switching device. The power converter device may thereby achieve particularly efficient performance.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: July 10, 2018
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Stephan Geisler, Wolfgang Jarausch, Michael Kaspar, Stefan Kiefl, Kai Kriegel, Matthias Neumeister, Julian Seidel
  • Patent number: 9986643
    Abstract: A display circuit board is provided with at least one section being configured as flexible circuit board, wherein the at least one flexible section of the display circuit board has at least one electrode being coupleable with a capacitive sensor device. Furthermore, a display module is provided with a display and a display circuit board. In addition, a method for the production of a display module is provided, wherein the display circuit board is inserted in a module housing together with the display in such a way that the flexible section is at least partially arranged between a side wall of the display and a side wall of the module housing. Finally, an electrical hand-held device, such as a cell phone or the like, is provided with a display module.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: May 29, 2018
    Assignee: MICROCHIP TECHNOLOGY GERMANY GMBH
    Inventor: Andreas Güte
  • Patent number: 9959400
    Abstract: The invention relates to accessing user interfaces for atmosphere controlling, particularly to comfortably accessing dedicated user interfaces of a complex atmosphere control system. A basic idea of the invention is to provide several user interfaces, each of which is provided for a certain control configuration for atmosphere control with an atmosphere creation system and to control the access to the user interfaces.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: May 1, 2018
    Assignee: PHILIPS LIGHTING HOLDING B.V.
    Inventors: Mikhail Victorovich Sorokin, Willem Piet Van Hoof
  • Patent number: 9881658
    Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kang-Yong Kim, Jacob Robert Anderson, Huy Vo
  • Patent number: 9865310
    Abstract: Solid state memory modules are disclosed having increased density for module size/footprint. Different embodiments also provide for improved interconnect arrangements between the memory modules and the corresponding field programmable gate array (FPGA), micro-processor (?P), or application-specific integrated circuit (ASIC). These interconnects provide for greater module interconnect flexibility, operating speed and operating efficiency. Some memory module embodiments according to the present invention comprises a plurality of solid state memory devices arranged on a first printed circuit board. A second printed circuit board is on and electrically connected to the first printed circuit board, with the second printed circuit board having a pin-out for direct coupling to a host device.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: January 9, 2018
    Assignee: INTERCONNECT SYSTEMS, INC.
    Inventors: Allan Cantle, Patrick Weber, Mark Gilliam, Prashant Joshi
  • Patent number: 9772097
    Abstract: A lighting device comprising a housing (102) with a driver electronics module (104) including driver circuitry for driving light sources and an electronics connector (106). The lighting device further comprising a circuit board (108) arranged in the housing, including a board connector (110). Furthermore lighting device comprises at least one light source (109) arranged on the circuit board and being in connection with the board connector, wherein the electronics connector and the board connector extend transverse to a planar extension of the circuit board. The board connector and the electronics connector are aligned so that they have an area of overlap, wherein the board connector and the electronics connector are biased against each other such that there is at least a line of contact which provides a galvanic connection, and wherein a heat induced electrical interconnection is provided along the line of contact. Such a connection is time- and cost efficient to assemble compared to a wire connection.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: September 26, 2017
    Assignee: PHILIPS LIGHTING HOLDING B.V.
    Inventors: Peter Johannes Martinus Bukkems, Machiel Willem Johan Peters
  • Patent number: 9747959
    Abstract: A stacked memory device includes a master semiconductor die and a plurality of slave semiconductor dies stacked on the master semiconductor die. The master semiconductor die includes a first power line coupled to a first power supply voltage, a second power line coupled to a second power supply voltage, a memory device coupled to the first power line, and a data input/output buffer coupled to the second power line. Each of the plurality of slave semiconductor dies includes third and fourth power lines and a memory device coupled to the third power line. The third power line is electrically connected to the first and fourth power lines, and the fourth power line is electrically disconnected from the second power line. The data input/output buffer buffers data communicated between an external device and the memory devices included in the master semiconductor die and the plurality of slave semiconductor dies.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: August 29, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seong-Min Seo
  • Patent number: 9564712
    Abstract: A connecting assembly for mounting a first expansion card and a second expansion card in a motherboard. The connecting assembly includes at least one fixing member, a first locking member and a second locking member. Each fixing member includes a first clamping portion and a second clamping portion, the fixing member is detachably assembled on the motherboard. The motherboard is held between the first clamping portion and the second clamping portion, the fixing member fixes the first expansion card and the second expansion card with the motherboard through the first locking member and the second locking member.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: February 7, 2017
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Tung-Ho Shih
  • Patent number: 9461015
    Abstract: A microelectronic assembly includes a dielectric element having first and second surfaces, first and second apertures extending between the first and second surfaces and defining a central region of the first surface between the first and second apertures, first and second microelectronic elements, and leads extending from contacts exposed at respective front surfaces of the first and second microelectronic elements to central terminals exposed at the central region. The front surface of the first microelectronic element can face the second surface of the dielectric element. The front surface of the second microelectronic element can face a rear surface of the first microelectronic element. The contacts of the second microelectronic element can project beyond an edge of the first microelectronic element. At least first and second ones of the leads can electrically interconnect a first central terminal of the central terminals with each of the first and second microelectronic elements.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: October 4, 2016
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Wael Zohni, Richard Dewitt Crisp
  • Patent number: 9443788
    Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: September 13, 2016
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventor: Takamasa Takano
  • Patent number: 9407021
    Abstract: A integrated mechanical and electrical connector and method for connecting printed circuit boards and an connected printed circuit board assembly is disclosed. The connector comprises an outer member defining a first bore, and an inner member at least partially disposed within the first bore wherein the inner member is in an interference fit relationship with the outer member at the periphery of the first bore and wherein the inner member is an electric conductor, the connector being configured to be mechanically and electrically connected to a printed circuit board by at least one of solder reflow, wave soldering and press fitting.
    Type: Grant
    Filed: December 29, 2013
    Date of Patent: August 2, 2016
    Assignee: Continental Automotive Systems, Inc.
    Inventor: Blendi Sullaj
  • Patent number: 9324582
    Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: April 26, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-Tang Lin, Yi-Che Lai
  • Patent number: 9302780
    Abstract: The invention concerns an aircraft including a cockpit comprising a viewing surface for piloting giving at least one pilot a view of an outside scene comprising the environment of the aircraft extending forward of the aircraft. At least part of said viewing surface for piloting is free of any glazed surface and is formed by display means for a digital image representing at least part of an outside scene comprising the environment of the aircraft extending forward of the aircraft.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: April 5, 2016
    Assignee: Airbus SAS
    Inventors: Jason Zaneboni, Bruno Saint-Jalmes
  • Patent number: 9269403
    Abstract: Various embodiments of apparatuses are disclosed to allow independent control of stacked modules. In one embodiment, an apparatus may include a plurality of stacked memory dice, with at least some of the plurality of stacked memory dice include a Chip Enable (CE) signal connection electrically accessible from a surface of a corresponding one of the dice. Each of the stacked dice having the CE signal connection is controllable individually by a unique CE signal applied to the CE signal connection. Other apparatuses are disclosed.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: February 23, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Robert N Schenck, Steven R. Eskildsen
  • Patent number: 9241406
    Abstract: An electronic assembly includes a first substrate, at least one first conductive pad and multiple second conductive pads. The first substrate comprises a base layer and at least one conductive circuit layer. The at least one conductive circuit layer is disposed on the base layer. The at least one first conductive pad is disposed on the first substrate. The first conductive pad is electrically insulated from the conductive circuit layer. The first conductive pad includes multiple first holes. The second conductive pads are disposed on the first substrate. The second conductive pads are electrically connected to the conductive circuit layer.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: January 19, 2016
    Assignee: AU OPTRONICS CORP.
    Inventors: Yan-Li Fang, Po-Fu Huang, Chun-Ming Lin
  • Patent number: 9190746
    Abstract: A circuit board connector is disclosed that has isolator ribs between contact tails, and slots in the edge of a circuit board between circuit pads that communicate with the ribs to avoid pad-to-pad current leakage and high-voltage breakdown. The slots may be between individual circuit board fingers that each include one of the conductor pads.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: November 17, 2015
    Assignee: Cardioinsight Technologies, Inc.
    Inventors: Larry Crofoot, John T. Venaleck
  • Patent number: 9101068
    Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 4, 2015
    Assignee: QUALCOMM INCORPORATED
    Inventors: Changhan Yun, Francesco Carobolante, Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Lawrence D. Smith, Matthew M. Nowak
  • Patent number: 9093396
    Abstract: A universal silicon interposer system and method to enabling the selective use of multiple proprietary microelectronic devices without the need to substantially alter the end-use application(s). The system may be used in the implementation of three-dimensional (stacked) microelectronics having proprietary contact pin patterns.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: July 28, 2015
    Inventor: Masahiro Lee
  • Publication number: 20150146395
    Abstract: An electrically conductive material includes a liquid gallium alloy mixed with multiple solid particles, so as to form an electrically conductive material in which solid and liquid coexist. The electrically conductive material is disposed between and electrically connecting a first conductor and a second conductor. The first conductor is disposed on a first electronic element, and the second conductor is disposed on a second electronic element.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 28, 2015
    Inventors: Ted Ju, Kai Tze Huang, Chien Chih Ho, Tien Chih Yu, Chin Chi Lin
  • Patent number: 9042115
    Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heung-Kyu Kwon, Min-Ok Na, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
  • Patent number: 9036365
    Abstract: A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: May 19, 2015
    Assignee: NEC Corporation
    Inventors: Manabu Kusumoto, Naoki Kobayashi, Noriaki Ando, Hiroshi Toyao
  • Publication number: 20150124420
    Abstract: An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Inventors: Alexander Heinrich, Peter Scherl, Magdalena Hoier, Hans-Joerg Timme
  • Patent number: 9025342
    Abstract: A wedge lock clamping assembly, system and method wherein the module to be clamped in a slot in a chassis has a pair of wedge surfaces oppositely inclined to spaced-apart side surfaces of the slot. The clamping assembly comprises a pair of wedge elements on opposite sides of a movement axis and each wedge element is configured to be disposed within the slot between a respective wedge surface of the module and a respective side surface of the slot. An actuator operates to forcibly urge the wedge elements along the movement axis for causing the wedge elements to be wedged between the respective wedge surfaces of the module and respective side surfaces of the slot for clamping the module in the slot.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: May 5, 2015
    Assignee: Parker-Hannifin Corporation
    Inventors: Rex J. Harvey, Robert A. Frindt, Jr.
  • Publication number: 20150115712
    Abstract: A power supply device includes a first body and a second body. The first body has an opening and an adapter module which is electrically connected to the first electronic device. The opening is divided into a first port and a second port via a first axis, and the shape of the first portion is asymmetrical with second port of the second portions. The second body has an energy storage unit. The energy storage unit is electrically connected to the adapter module to supply power to the first electronic device, when the second body is detached from the first body, the energy storage unit is adapted to supply power to the second electronic device.
    Type: Application
    Filed: October 29, 2014
    Publication date: April 30, 2015
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Ching-Hua Chen, Hung-Wei Lin
  • Publication number: 20150109751
    Abstract: Provided is an electronic device such as an electrochromic device or a liquid-crystal device in which a bus bar can be disposed with a simple structure for at least one electrode film and a width of a region that does not provide an intended function of the electronic device can be reduced. An electronic device is formed by integrating two substrates with spacers interposed therebetween, the substrates including respective electrode films on respective surfaces facing each other. At least one of the spacers is formed by a metal thin film-provided spacer obtained by forming a metal thin film on one surface of an insulating plate material. The electrode film of the substrate and the metal thin film of the metal thin film-provided spacer are conductively joined to each other. The electrode film is conductively connected to a terminal connected to an external circuit, via the metal thin film.
    Type: Application
    Filed: January 22, 2013
    Publication date: April 23, 2015
    Applicant: Murakami Corporation
    Inventor: Takuo Mochizuka
  • Patent number: 9013891
    Abstract: An electronics package includes one or more insulating layers and an electrically conductive transmission line. The electrically conductive transmission line includes a signal trace disposed substantially parallel to the one or more insulating layers. The electrically conductive transmission line further includes one or more signal vias electrically coupled to the signal trace. The one or more signal vias are configured to pass through at least a portion of the one or more insulating layers. The electronics package further includes one or more electrically conductive ground planes substantially parallel to the one or more insulating layers. The ground planes include one or more signal via ground cuts. The one or more signal via ground cuts provide clearance between the one or more signal vias and the one or more ground planes.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: April 21, 2015
    Assignee: Finisar Corporation
    Inventors: Yunpeng Song, Yongsheng Liu, Hongyu Deng
  • Patent number: 9007784
    Abstract: A device and/or method mount and affix a microchannel plate in a micro system. The device and/or method has at least one conductive spring structure, formed to accept a microchannel plate, for aligning, fixing and making electrical contact with the microchannel plate. The device and/or method also has at least one stop against which the microchannel plate is pushed or pressed when affixed by at least one conductive spring structure, wherein the at least one conductive spring structure and the at least one stop are being applied on a non-conductive substrate.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: April 14, 2015
    Assignees: Bayer Intellectual Property GmbH, Krohne Messtechnik GmbH
    Inventors: Jan-Peter Hauschild, Eric Wapelhorst, Jörg Müller
  • Patent number: 8995310
    Abstract: A communication module includes: a plurality of receiving filters that are connected between an antenna terminal and a receiving terminal and have a receive band different from each other; and a passive circuit that is commonly connected to at least two of the plurality of receiving filters and makes a receive band of one of said at least two of the plurality of receiving filters suppressed when making another receive band of said at least two of the plurality of receiving filters transitable, wherein receiving terminals of said at least two of the plurality of receiving filters are commonalized through the passive circuit.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 31, 2015
    Assignee: Taiyo Yuden Co., Ltd.
    Inventor: Jun Tsutsumi
  • Publication number: 20150085461
    Abstract: A method for manufacturing a combined wiring board includes preparing multiple wiring boards, preparing a metal frame having opening portions which accommodate the boards, respectively, positioning the boards in the opening portions of the frame, respectively, and forming multiple crimped portions in the frame by plastic deformation such that the sidewalls of the boards bond to sidewalls of the opening portions in the frame. The preparing of the boards includes forming the sidewalls of the boards such that when the boards are positioned in the opening portions of the frame, the sidewalls of the boards form wide-space portions and narrow-space portions with respect to the sidewalls of the opening portions in the frame, and the forming of the crimped portions includes generating the deformation such that the sidewalls of the opening portions in the frame abut the narrow-space portions of the boards before the wide-space portions of the boards.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 26, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Teruyuki ISHIHARA, Michimasa TAKAHASHI
  • Patent number: 8988895
    Abstract: An interconnection element is disclosed that includes a plurality of drawn metal conductors, a dielectric layer, and opposed surfaces having a plurality of wettable contacts thereon. The conductors may include grains having lengths oriented in a direction between the first and second ends of the conductors. A dielectric layer for insulating the conductors may have first and second opposed surfaces and a thickness less than 1 millimeter between the first and second surface. One or more conductors may be configured to carry a signal to or from a microelectronic element. First and second wettable contacts may be used to bond the interconnection element to at least one of a microelectronic element and a circuit panel. The wettable contacts may match a spatial distribution of element contacts at a face of a microelectronic element or of circuit contacts exposed at a face of component other than the microelectronic element.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: March 24, 2015
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba
  • Publication number: 20150077963
    Abstract: A printed wiring board includes a wiring board, and multiple posts formed on the wiring board and positioned to mount a second printed wiring board onto the wiring board. Each of the metal posts has a first surface connected to the wiring board, a second surface formed to connect the second printed wiring board, and a side surface between the first surface and the second surface, and the side surface of each of the metal posts forms a curved surface.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 19, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Takema ADACHI, Yuzo KAIDA
  • Patent number: 8982578
    Abstract: A system configured to protect a load within a vehicle includes a plug subassembly and a sensor connector subassembly. The sensor connector subassembly is selectively connectable to the plug subassembly. A circuit board is secured within the sensor connector subassembly. The circuit board includes at least one positive temperature coefficient (PTC) device electrically connected between an activation switch and a load. The circuit board includes at least one circuit to protect against over-voltage or over-current to the load, detect a fault condition of the load, and determine whether the plug subassembly is connected to the sensor connector subassembly.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: March 17, 2015
    Assignee: Tyco Electronics Corporation
    Inventors: Lyle Stanley Bryan, John Steven Cowan, Thomas Michael Banas, Ralph Melvin Cooper
  • Publication number: 20150062856
    Abstract: A connection port configuring method and a combined circuit board module mounted with multiple connection ports, characterized in that connection ports are mounted on a first circuit board and a second circuit board; the connection ports each comply with a communication port protocol and send a data at a transmission speed by the communication port protocol; the connection port configuring method involves assigning the connection ports to a high-speed connection port group and a low-speed connection port group according to the transmission speed of each connection port, mounting the connection ports of the high-speed connection port group on the first circuit board, and mounting the connection ports of the low-speed connection port group on the second circuit board. With a connection unit connecting the first circuit board and the second circuit board, the data can be transmitted between the first circuit board and the second circuit board.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: GOOD WAY TECHNOLOGY CO., LTD.
    Inventor: YI-CHENG CHANG
  • Patent number: 8971056
    Abstract: A hermetically sealed HF front end (e.g. a transmission/reception module) in a multilayer structure that includes electronic components is provided. The multilayer structure contains a plurality of substrates stacked one above the other and carrying the components. Grooves are formed in the substrates and sealing elements are provided between the substrates, which sealing elements engage in the grooves, and the substrates are soldered together.
    Type: Grant
    Filed: September 18, 2010
    Date of Patent: March 3, 2015
    Assignee: EADS Deutschland GmbH
    Inventors: Heinz-Peter Feldle, Bernhardt Schoenlinner, Ulrich Prechtel, Joerg Sander
  • Patent number: 8958214
    Abstract: Mechanisms for interconnecting and distributing signals and power between PCBs are provided. A first PCB having land grid arrays (LGAs) and a first wiring layer designed for interconnect components on the first PCB, and a second wiring layer for connecting the components to a second PCB, are provided. The second PCB has opposed parallel first and second surfaces, the first surface having a LGA. A wiring layer designed to interconnect components on the second PCB, and a layer for interconnecting the components on the second PCB with the components on the first PCB, are provided. A first interposer couples to a LGA of a first surface of the first PCB and connects a component to the first PCB. A second interposer is sandwiched between and couples to a LGA of a second surface of the first PCB and to the LGA of the first surface of the second PCB.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: John L. Colbert, Arvind K. Sinha, Roger D. Weekly
  • Patent number: 8958215
    Abstract: The present invention has an objective to provide a circuit board for a peripheral circuit which can transmit outside heat which generates from a high exothermic element, such as a power semiconductor element, while attaining reduction in size and weight, reduction in surge, and reduction in a loss, in high-capacity modules including power modules, such as an inverter. [Solution Means] In a high-capacity module, by laminating a peripheral circuit using a ceramic circuit board with electrode(s) constituted by thick conductor and embedded therein on a highly exothermic element, overheating of the module is prevented by effective heat dissipation via the circuit board while attaining reduction in size and weight, reduction in surge, and reduction in a loss in the module.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: February 17, 2015
    Assignee: NGK Insulators, Ltd.
    Inventors: Takami Hirai, Shinsuke Yano, Tsutomu Nanataki, Hirofumi Yamaguchi
  • Publication number: 20150043188
    Abstract: The invention relates to a method for manufacturing a printed circuit board (10) having a substrate (2) and an electric circuit (8), in particular for a rear view device of a motor vehicle, the method comprising the following steps: manufacturing a plurality of substrate parts (2a, 2b); and selecting at least two of the substrate parts (2a, 2b), and connecting the selected substrate parts (2a, 2b) and providing the connected substrate parts (2a, 2b) with the circuit (8).
    Type: Application
    Filed: August 6, 2014
    Publication date: February 12, 2015
    Applicant: SMR PATENTS S.A.R.L.
    Inventor: Andreas Herrmann
  • Publication number: 20150035433
    Abstract: An illustrative inventory of vehicle accessory control components includes a plurality of first circuit boards and a plurality of second circuit boards. The first circuit boards each have a substrate with a plurality of circuit elements supported on the substrate. The first circuit board substrates have an overall perimeter shape including an outer edge profile and a plurality of first deviations from the outer edge profile. The second circuit boards each have a substrate with a plurality of circuit elements supported on them. The second circuit board substrates have the overall perimeter shape including the same outer edge profile as the first circuit board substrates. The second circuit board substrates include a plurality of second deviations from the outer edge profile. At least one portion of the second deviations is different than the first deviations of the first circuit boards.
    Type: Application
    Filed: January 30, 2014
    Publication date: February 5, 2015
    Applicant: UUSI, LLC d/b/a NARTRON
    Inventors: David W. SHANK, John M. WASHELESKI, Edward J. COX, II
  • Patent number: 8941999
    Abstract: A microelectronic assembly includes a dielectric element that has oppositely-facing first and second surfaces and first and second apertures extending between the surfaces. The dielectric element further includes conductive elements. First and second microelectronic elements are stacked one on top of the another. The second microelectronic element has a plurality of contacts at a surface, which is spaced from the first surface of the dielectric element. Leads extend from contacts of the first and second microelectronic elements through respective apertures to at least some of the conductive elements. A heat spreader is thermally coupled to at least one of the first microelectronic element or the second microelectronic element.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 27, 2015
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Wael Zohni, Richard Dewitt Crisp
  • Patent number: 8942005
    Abstract: An electronics module is provided for utilization onboard an airborne object. In one embodiment, the electronics module includes a housing having a cavity therein, a first printed circuit board (PCB) disposed in the cavity, a second PCB disposed in the cavity above the first PCB, and a supportive interconnect structure. The supportive interconnect structure includes a substantially annular insulative body and a plurality of vias. The substantially annular insulative body extends around an inner circumferential portion of the housing between the first PCB and the second PCB to support the second PCB and to axially space the second PCB from the first PCB. The plurality of vias is formed through the substantially annular insulative body and electrically couples the first PCB to the second PCB.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: January 27, 2015
    Assignee: Raytheon Company
    Inventor: Chris E. Geswender
  • Patent number: 8942003
    Abstract: A multilayered printed wiring board includes a plurality of insulating layers; a plurality of wiring layers which are located between the corresponding adjacent insulating layers; and a plurality of interlayer connection conductors for electrically connecting the wiring layers through the insulating layers; wherein a cavity is formed through one or more of the insulating layers so as to insert a first electric/electronic component and an area for embedding a second electric/electronic component is defined for the insulating layers.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: January 27, 2015
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Takahiro Sahara, Atsushi Kobayashi, Kiyoshi Takeuchi, Masahiko Igaue
  • Publication number: 20150022978
    Abstract: A circuit assembly (1800) includes a first circuit substrate (1200) defining a first major face (1201) and a second circuit substrate (1500) defining a second major face (1502). A plurality of electrical components (1203,1204,1205) can be disposed on one or more of the first major face or the second major face. One or more substrate bridging members (1301,1302,1303,1304) are disposed between the first circuit substrate and the second circuit substrate. Each substrate bridging member can define a unitary structure having a first end bonded to the first major face and a second end bonded to the second major face to bridge the first circuit substrate and the second circuit substrate.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 22, 2015
    Applicant: Motorola Mobility LLC
    Inventors: Paul R. Steuer, Patrick J. Cauwels