Interconnection Details Patents (Class 361/803)
  • Patent number: 6817092
    Abstract: A method allowing for the inexpensive automated construction of interconnections between circuit boards is provided. According to the present invention, printed circuit pins are inserted in a circuit board from the top (component side). Provided the heads of the pins are thin enough to lie beneath a solder stencil, the pins may be pre-installed on the circuit board and solder applied to the pins at the same time solder is applied to other regions of the board. Thus, known surface mount techniques may be employed to form solder connections between the pins and conductive traces on the circuit board, which facilitates the automation of the previously manual operation of soldering the printed circuit pins separately.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: November 16, 2004
    Assignee: Powerwave Technologies, Inc.
    Inventors: James Keith Custer, James Hiram Roberson, William Kerr Veitschegger
  • Patent number: 6816387
    Abstract: In part, and in addition to apparatus and methods presented, an expansion board to be connected/disconnected to/from its mother board easily is provided. A face of a CDC (Communication Daughter Card), which is an expansion board to be connected to the mother board of a computer system is covered by an insulating sheet. In the CDC, an edge of one end of this insulating sheet is extended so as to form a projection. A user can take this projection with fingers, thereby carrying and connecting/disconnecting the CDC to/from the mother board easily.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Kazuo Fujii, Yoshihisa Ishihara, Aaron M. Stewart
  • Patent number: 6813162
    Abstract: A circuit board assembly has a circuit board and a column grid array (“CGA”) integrated circuit package. The CGA integrated circuit package has a substrate having an array of solder columns extending from a bottom surface. An oversized lid is affixed to the substrate. Support shims are disposed between a portion of the lid that extends beyond an outer periphery of the substrate and a circuit board to which the CGA integrated circuit package is mounted. The support shims are affixed to the lid with adhesive after the CGA integrated circuit package is mounted on the circuit board. The adhesive accommodates any variations in height in the CGA integrated circuit package.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: November 2, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Jeffrey L. Deeney
  • Patent number: 6813163
    Abstract: A plurality of converter circuits is connected in parallel while reducing conduction loss. A converter circuit is formed on each of a plurality of circuit boards, and a plurality of types of terminal connection patterns containing power input terminal connection patterns and power output terminal connection patterns are formed on the end portions of each of the circuit boards with the disposition positions substantially matching each other. The terminal connection patterns at the same position of each circuit board are sandwiched by each of clips of a common terminal member, each of the circuit boards is laminated and fixed, and the converter circuits of each of the circuit boards are connected in parallel. The conduction path for electrically connecting the converter circuit of each circuit board becomes short, making it possible to reduce conduction loss.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: November 2, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Keiji Inoue, Yosuo Ohashi
  • Patent number: 6813157
    Abstract: A mother board and a computer system capable of flexibly using the SDRAM and the DDRAM. The mother board has several memory module slots, a voltage comparator, a clock generator and a chip set. Each of the memory module slots comprises a reference voltage pin, and the reference voltage pins of the memory module slots are connected to each other in parallel. The voltage comparator is coupled to the reference voltage pins of the memory module slots to detect whether the voltage at the reference voltage pin is equivalent to a reference voltage. The clock generator is coupled to an output of the voltage comparator. When the voltage at the reference voltage pin is equal to the reference voltage, a differential clock signal is generated, and when the votlage is different from the reference voltage, a normal clock signal is generated. The chip set is coupled to the output of the voltage comparator. When the voltage is equal to the reference voltage, the chip set is operated under a double data rate mode.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: November 2, 2004
    Assignee: VIA Technologies, Inc.
    Inventor: Nai-Shung Chang
  • Patent number: 6807064
    Abstract: An electronic component having at least one semiconductor chip, a rewiring layer connected to the semiconductor chip, and a printed circuit board associated with the rewiring layer. The rewiring layer is provided with flexible contacts that correspond with contact faces of the printed circuit board, and the rewiring layer is solidly connected to the printed circuit board via a flat intermediate layer. A method for producing the electronic component is described.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: October 19, 2004
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Thorsten Meyer
  • Patent number: 6804120
    Abstract: A method and apparatus for connecting circuit boards together in a sensor assembly includes a connector that allows the circuit boards to be positioned generally perpendicular to each other. The connector includes a first end that is received within an opening formed at one edge of a main circuit board. A second end of the connector includes a resilient hook or clip that grippingly engages opposing sides of an auxiliary circuit board. The connector comprises an electrical contact between the main and auxiliary circuit boards. The perpendicular orientation of the auxiliary circuit board to the main circuit board allows for more compact packaging.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: October 12, 2004
    Assignee: Siemens VDO Automotive Corporation
    Inventors: Jeffrey A. Clark, Brian M. Curtis
  • Patent number: 6804123
    Abstract: A computer mainframe includes a housing, a motherboard, an intermediate circuit board, and a supporting bracket. A CD-ROM and a hard disk are attached to upper and lower sides, respectively, of the intermediate circuit board to sequentially superpose on and electrically connect to the motherboard via various connecting terminals provided at specific positions on the upper and the lower side of the intermediate circuit board. With the vertically superposed architecture of the mainframe, no space-occupying flat cable is needed for wiring the mainframe, enabling the mainframe to have a largely reduced volume.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: October 12, 2004
    Assignee: King Young Technology Co., Ltd.
    Inventor: Wan Chen Cheng
  • Patent number: 6801440
    Abstract: A plurality of module substrates have circuit boards, respectively. The circuit boards are stacked with a space therebetween, and are connected to first end portions of connecting members. The second end portions of the connecting members are connected to connecting pads disposed on a motherboard. The module substrates are thus stacked and mounted on the motherboard so as to increase the mounting density. By causing the connecting members for the upper circuit board to project further than the connecting members for the lower circuit board, the connecting members for the upper and lower circuit boards are prevented from touching each other.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: October 5, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Keiji Inoue, Yasuo Ohashi, Toru Yoshikawa
  • Patent number: 6799369
    Abstract: A printed circuit board of the present invention is formed of an electrical insulating base material with through holes that are formed in a thickness direction of the electrical insulating base material and are filled with an electrical conductor; the electrical insulating base material including a core layer formed by impregnating a holder with a resin and resin layers formed on both sides of the core layer; and wiring layers that are formed on both surfaces of the electrical insulating base material into a predetermined pattern and are electrically connected to each other by the electrical conductor. The wiring layer is embedded in at least one of the resin layers. The resin layers on the both sides have different thicknesses from each other, and a thinner layer out of the resin layers has a thickness equal to or smaller than a mean particle diameter of an electrically conductive filler contained in the electrical conductor.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: October 5, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shozo Ochi, Fumio Echigo, Yoji Ueda
  • Publication number: 20040190277
    Abstract: The invention relates to a mounting element (MON) for joining a component (BAU) to a circuit carrier (STR). Said mounting element (MON) comprises a receiving element (AUF) which enables it to be joined to a section (ABS) of the component (BAU) in a positive fit. Said mounting element (MON) comprises at least one snap hook (SH1, SH2) which can be engaged in a mounting opening (MOE) of the circuit carrier (STR).
    Type: Application
    Filed: January 26, 2004
    Publication date: September 30, 2004
    Inventors: Martin Petricek, Thomas Rothmayer
  • Patent number: 6798667
    Abstract: A solder ball collapse control apparatus and method thereof includes a plurality of first solder members, pieces of solder material in a shape capable of being used to properly create a solder joint. The first solder members have a first solder dimension and a first melting temperature and are disposed on a carrier substrate, wherein the first solder members include any piece of material capable of being disposed using a solder dispensing machine. The apparatus and method further includes a plurality of second members having a second dimension and a second melting temperature, disposed on the carrier substrate in relation to the plurality of first solder members. The second members include any piece of material capable of being disposed using the solder dispensing machine, wherein the first solder member dimension is greater than the second member dimension and the second melting temperature is greater than the first melting temperature.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: September 28, 2004
    Assignee: ATI Technologies, Inc.
    Inventor: Vincent K. Chan
  • Patent number: 6793500
    Abstract: A structure and associated method comprising contact pads on a surface of a substrate for coupling signal, power, and ground connections for an electrical device to a plurality of conductive wires on the substrate. The contact pads are formed in single lines along radial edges of sectors on the substrate. Each of the sectors comprise a predetermined angle between the radial edges of each of the sectors. The plurality of sectors collectively form a circular area. The contact pads comprise signal, power, and ground connections located at predetermined positions on the single lines along the radial edges of each of the sectors on the substrate.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: September 21, 2004
    Assignee: International Business Machines Corporation
    Inventors: Timothy W. Budell, Esmaeil Rahmati, David B. Stone, Jerzy M. Zalesinski
  • Patent number: 6794580
    Abstract: A system and method are provided for facilitating the interconnection of the conductors of a flat circuit. A flat circuit substrate is provided with a plurality of conductors thereon. A dielectric film on the substrate substantially covers the conductors. An opening is formed in the film to selectively expose the conductors. A layer of solder material is preapplied to the exposed conductors in the opening. Therefore, the opening can be juxtaposed with a mating conductor to facilitate interconnecting the conductors by an appropriate soldering process using the preapplied solder material.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: September 21, 2004
    Assignee: Molex Incorporated
    Inventors: Prashant P. Joshi, Robert M. Fuerst
  • Publication number: 20040179343
    Abstract: One embodiment of the present invention is a structure useful for testing circuits that includes: (a) a flexible substrate having contactors on a first side and pads on a second side; (b) a rigid substrate having vias aligned with the pads on the second side of the flexible substrate; (c) an adhesive layer comprised of a compliant adhesive material having vias aligned with the pads on the second side of the flexible substrate; the adhesive layer being affixed to the flexible substrate and the rigid substrate; (d) a card; (e) electrical connectors that are retained in the vias of the rigid substrate and the adhesive layer, which electrical connectors have first and second retractable ends, wherein the first retractable ends contact pads on the substrate, and the second retractable ends contact pads on the card; and (f) a clamp that is adapted to fit over the substrate and the adhesive layer, the clamp having an opening to provide access to the contactors, wherein the clamp is connected to the card.
    Type: Application
    Filed: April 16, 2003
    Publication date: September 16, 2004
    Applicant: Nexcleon, Inc.
    Inventors: Konstantine N. Karavakis, Tom T. Nguyen
  • Patent number: 6791046
    Abstract: A switch assembly is described having one or more switches and a holder. The switches are preferably of a pushbutton type having an outwardly extending flange. The holder includes a cover and base with a pair of upright arms. The cover includes a three-sided opening. As assembled, the upright arms receive a switch and the combination is received in the three-sided opening of the cover. A switch subassembly is further described having a circuit board and quick-disconnect unit. Such improved switch and switch subassembly allow a technician to quickly change out a defunct alarm system switch.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: September 14, 2004
    Inventor: Corey T. King
  • Patent number: 6791846
    Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: September 14, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Larry D. Smith, Istvan Novak, Michael C. Freda
  • Publication number: 20040174689
    Abstract: A planar board for attachment to a chassis and the resulting attachment structure and method of forming the resulting structure is provided. The planar board has components on one face thereof oriented toward one face of the chassis. The chassis has at least one standoff extending from the one face thereof and the planar board has a structure cooperating with each standoff on the chassis mounting the planar board in a standoff relationship at an installed distance. At least one spacer member is mounted on the one face of the planar board and extends from that one face a distance equal to the installed distance to engage the one face of the chassis in the installed condition.
    Type: Application
    Filed: March 3, 2003
    Publication date: September 9, 2004
    Applicant: International Business Machines Corporation
    Inventor: Alexander V. Verrigni
  • Patent number: 6785148
    Abstract: A socket for mounting a processor and/or a board has a substrate with a built in socket. The socket has conductive, elastically deformable terminals. The socket may be mounted to a processor and a board without using conventional surface mount technology, instead providing a mechanical contact mechanism between the socket and the board or processor. An adhesive layer may also be used to connect the socket to a processor and/or a board.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: August 31, 2004
    Assignee: Intel Corporation
    Inventors: Kenzo Ishida, Shuji Inoue, Kinya Ichikawa, Kenji Takahashi
  • Patent number: 6784375
    Abstract: An interconnection structure has a first printed circuit board including an insulating substrate made of a thermoplastic resin and a first board conductive pattern with a land, a second printed circuit board overlapped with the first printed circuit board, and including a second board conductive pattern with a land that is electrically interconnected with the land of the first printed circuit board to form an interconnection portion between the first board conductive pattern and the second board conductive pattern. A part of the thermoplastic resin constituting the insulating substrate of the first printed circuit board extends to seal the interconnection portion. The insulating substrate of the first printed circuit board is adhered to an insulating substrate of the second printed circuit through an adhesion enhancing layer in which a material for lowering a modulus of elasticity of the insulating substrate of the first printed circuit board is dispersed therein.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: August 31, 2004
    Assignee: Denso Corporation
    Inventors: Toshihiro Miyake, Katsuaki Kojima, Makoto Totani, Yoshitaro Yazaki
  • Patent number: 6785144
    Abstract: A flexible carrier substrate assembly or module that facilitates stacking of multiple carrier substrates bearing semiconductor dice for high density electronic systems. After the dice are placed on the flexible substrate, a flexible support frame may be applied to the flexible substrate. The support frame includes conductive paths therethrough to connect to circuit traces running from the dice on the substrate to the substrate perimeter to interconnect superimposed carrier substrates. The flexible carrier substrates may be bent to a radius of any given curvature to conform to various non-planar regular and irregular surfaces. Furthermore, since the frame as well as the substrate may be flexible, multiple, flexible substrate assemblies may be stacked one on top of another wherein an upper assembly has a different radius than a lower module and any intermediate assemblies have progressively differing radii from bottom to top position.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6781845
    Abstract: A parallel printed circuit board assembly includes a main circuit board (1) and an auxiliary circuit board (2). The main circuit board has a surface (14) with a plug connector (32) and a receptacle connector (44) mounted thereon. The auxiliary circuit board has a surface (22) with a plug connector (42) and a receptacle connector (34) mounted thereon. The plug and receptacle connectors of the main circuit board respectively mate with the receptacle and plug connectors of the auxiliary circuit board. Because of the arrangement of the plug and receptacle connectors on the main and auxiliary circuit boards, the circuit boards can only connect with one another in one correct way.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: August 24, 2004
    Assignee: Hon Hai Precision Ind. Co., Ltd.
    Inventor: Cheng Kuo Chang
  • Patent number: 6778404
    Abstract: A stackable package to create a 3-dimensional memory array using ball grid array technology. Specifically, memory chips are coupled to a pre-formed packages which have alignment features to allow for the stacking of the ball grid arrays. The alignment features are used to align and orient each package with respect to an adjacent package, substrate or printed circuit board. The alignment features also support the weight of the adjacent package during solder ball reflow to maintain stack height and parallelism between packages. Each memory device is serially connected to the adjacent memory device through the vias and solder balls on each package.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: August 17, 2004
    Inventors: Todd O. Bolken, Cary J. Baerlocher, Chad A. Cobbley, David J. Corisis
  • Patent number: 6778400
    Abstract: An electronic device, including a housing part having at least one closable opening and one plug-in part, the housing part accommodating a printed circuit board, which has at least one electrical and/or electronic component arranged thereon, and electrical contact elements, which are electrically connected to the plug-in part, and which have ends in the housing interior that run parallel to each other and protrude in the direction of the at least one opening, the ends being passed through contact openings of the printed circuit board and being connected conductively to the printed circuit board.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: August 17, 2004
    Assignee: Robert Bosch GmbH
    Inventors: Juergen Kurle, Kurt Weiblen, Stefan Pinter, Frieder Haag
  • Patent number: 6777794
    Abstract: This invention provides a circuit mounting method and a circuit mounted board which can mount semiconductor elements at a high density. A recessed portion is formed in a board, a memory IC packaged in a chip size package method (CSP) is mounted in the recessed portion, and a memory IC packaged in a thin small outline package method (TSOP) is mounted on the board to cover the recessed portion.
    Type: Grant
    Filed: July 20, 2001
    Date of Patent: August 17, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Takao Nakajima
  • Patent number: 6775151
    Abstract: A circuit board is provided with extending portions having terminal patterns formed thereon. A housing contains the circuit board while permitting the extending portions to protrude. A mother board has, formed therein, through holes in which the extending portions are to be inserted, having, formed thereon, wiring pattern that is to be electrically connected to the terminal patterns, and permitting the extending portions to be inserted in the through holes so that the housing is placed thereon. The circuit board is provided with a protruded portion which extends separately from the extending portions and pushes the terminal patterns onto the wiring pattern of the mother board. The mother board is provided with an insertion hole in which the protruded portion is to be inserted being slightly deviated from the positions of the through holes in which the extending portions are to be inserted.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: August 10, 2004
    Assignee: Alps Electric Co., Ltd.
    Inventor: Norio Suzuki
  • Patent number: 6775149
    Abstract: A multichip mounted structure has a substrate 11 provided with substrate-side terminals 16a and 16b and a plurality of IC chips 12a and 12b provided with bumps 14a and 14b, respectively, so that the substrate-side terminals 16a and 16b are conductively connected with the bumps 14a and 14b, respectively. The bumps 14a and 14b provided on the plurality of IC chips 12a and 12b, respectively, form pairs of terminal lines opposing each other. Since the plurality of IC chips 12a and 12b are mounted on the substrate 11 so that central lines L1 and L2 between the pairs of terminal lines which are individually formed approximately coincide with each other, it is not necessary to transport a position of a compressive head, and one piece of ACF 19 can be commonly used.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: August 10, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Kenji Uchiyama
  • Patent number: 6775153
    Abstract: A semiconductor device includes a plurality of semiconductor chips; and a plurality of substrates, each of the substrates having one of the semiconductor chips mounted thereon. The substrates are stacked each other. The upper and lower ones of the semiconductor chips mounted on a pair of the stacked substrates are electrically connected through first terminals provided in a region outside the region in which one of the semiconductor chips is mounted in each of the substrates. The lowest one of the substrates has second terminals provided in its region closer to its center than its region in which the first terminals are provided, the second terminals electrically connected to one of the semiconductor chips. A pitch of adjacent two of the second terminals is wider than a pitch of adjacent two of the first terminals.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: August 10, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 6771515
    Abstract: In some embodiments, the invention includes a system having first and second modules and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extends from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module. The first path couples to chips of the first and second modules, and each of the chips include on die terminations, but only some of the chips include on die terminations that are enabled.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: August 3, 2004
    Assignee: Intel Corporation
    Inventors: James A. McCall, Hing Y. To
  • Publication number: 20040145880
    Abstract: In order to suppress the occurrence of damage on a press-fit joining wiring board, a peak value of stress generated on the board in the case of a press-fitting a press-fit terminal into a through-hole is reduced so that it can not exceed the design standard value of the board. In the press-fit terminal in which a body part, retaining part, introducing part and forward end part are integrally formed, a cross-sectional area of the introducing part is reduced to be smaller than that of the retaining part, so that an intensity of the elastic force of the introducing part is decreased to be lower than that of the elastic force of the retaining part. Alternatively, on the wiring board, elastic material is filled into resin for combining sheet-like base material of the board so as to relieve an intensity of stress generated on the board itself.
    Type: Application
    Filed: September 29, 2003
    Publication date: July 29, 2004
    Inventors: Hiromichi Watanabe, Yoshifumi Fukatsu, Toshihiro Kasai, Naoki Sugita, Naofumi Saito, Hiroyuki Yamanaka
  • Patent number: 6765800
    Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: July 20, 2004
    Assignee: Rambus Inc.
    Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Jr., Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
  • Patent number: 6765805
    Abstract: A circuit component comprising a circuit board and a terminal for mounting the circuit board on a second circuit board. A length of the circuit board is 10 mm-80 mm, a difference in a coefficient of thermal expansion between the circuit board and the second circuit board is 0.2×10−5/° C. or greater. The terminal is made of an elastic material, and comprised of a first connection section, a second connection section and an elastic section disposed between the first and second connection sections, and the terminal separates the circuit board from the second circuit board by 0.3 mm-5 mm. In the circuit components of the present invention, deterioration in the conduction between the circuit board and the second circuit board due to heat cycles can be prevented. Thus, a circuit component having stable operating characteristics for a long period of time is obtained.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: July 20, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takumi Naruse, Kenichi Kozaki, Kazuhiro Eguchi, Katsumi Sasaki
  • Patent number: 6762366
    Abstract: A printed circuit board having contacts in a contact array of rows and columns. Groups of n columns of the contacts are electrically connected to n−1 columns of vias disposed interstitially in a via array between the n columns of the contacts. A major vertical routing channel is formed between adjacent groups of n columns of the contacts and the n−1 columns of vias. First electrical traces are electrically connected to a first number of the vias. The first electrical traces are routed to an outside edge of the via array through the major vertical routing channel.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: July 13, 2004
    Assignee: LSI Logic Corporation
    Inventors: Leah M. Miller, Farshad Ghahghahi, Edwin M. Fulcher
  • Patent number: 6762380
    Abstract: A membrane switch circuit layout and method for producing a membrane switch circuit layout are disclosed. The membrane switch circuit layout may have two or more membrane layers. Each membrane has a top surface and a bottom surface. A conductive circuit trace is printed on the top surface of each membrane. The membrane layers are placed in a stack with each top membrane having thru-holes selectively cut there through. Thus, for example, in a layout having two membrane layers, the first membrane is positioned beneath the second membrane and the second membrane has thru-holes cut there through. Conductive ink may be pressed through the thru-holes to provide electrical connection between the circuit traces printed on the membrane layers. An adhesive may be placed between the membrane layers as either adhesive printed on one of the membrane layers or as an additional layer.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: July 13, 2004
    Assignee: Icorp
    Inventors: Wayne Nelson, Joel Theisen, John Pesonen
  • Patent number: 6760231
    Abstract: A fastening assembly, used for fixedly fastening a first and a second structure (1100, 1200) of a device together, comprises an anchoring block (1500), an insert plate (1400), and a screw (1300). The first structure is provided with a hole (1110). The anchoring block, fixedly arranged on the second structure, includes two parallel holding flanges (1510, 1512) and two parallel protruding ribs (1520), wherein the holding flange (1510) further includes a slot (15101). The protruding ribs extend approximately perpendicular to the two holding flanges on two sides thereof. The insert plate is held between the holding flanges, and is provided with a threaded hole (1410) and a pair of hooked clamping members (1420) that respectively tightly clamp the protruding ribs. The screw extends through the hole of the first structure and engages in the threaded hole of the insert plate to fixedly fasten the first and second structures of the device together.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: July 6, 2004
    Assignee: High Tech Computer, Corp.
    Inventors: Weicheng Hung, Sheng-Ming Lou, James Wu, Yente Chiang
  • Patent number: 6760232
    Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide core power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors. In one embodiment, the power laminate may include a plurality of apertures which allow for the passing of connections between the integrated circuit and the PCB.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: July 6, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Larry D. Smith, Michael C. Freda, Ali Hassanzadeh
  • Patent number: 6756663
    Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsukasa Shiraishi, Tsutomu Mitani, Kazuyoshi Amami, Yoshihiro Bessho
  • Patent number: 6757177
    Abstract: A stacked backplane assembly, including two or more backplanes or midplanes having different functionality and combined together so as to form an integral unit, is provided. The backplanes forming the assembly are manufactured with prime and secondary manufacturing holes to enable alignment, so that the resulting tolerance build-up of the assembly is similar to that of a single backplane. Connectors can be arranged on the backplanes of the assembly so that an electronic or optical card can be simultaneously plugged in to one or more of the backplanes that comprise the stacked backplane assembly. The stacked backplane assembly of the embodiments of the invention is illustrated by having power and signal backplanes and midplanes, but can be equally applied to backplanes that provide other types of functionality.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: June 29, 2004
    Assignee: Tropic Networks Inc.
    Inventors: Mark Roy Harris, Rodney Stephen Batterton
  • Patent number: 6754085
    Abstract: A mounting apparatus having first and second blocks securable within a housing. The first block has first and second grooves for respectively receiving a first edge of a first circuit board and a first edge of a second circuit board such that the first and second circuit boards are aligned with each other and are spaced apart. The second block has a groove for receiving a second edge of the first circuit board that is perpendicular to the first edge of the first circuit board and a surface to which the second circuit board is attached adjacent a second edge of the second circuit board that is perpendicular to the first edge of the second circuit board.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: June 22, 2004
    Assignee: ADC Broadband Access Systems, Inc.
    Inventor: Peter R. Kalkbrenner
  • Patent number: 6754087
    Abstract: A power supply structure for high density servers bridging a system end and a power supply end includes a power receiving unit located on the system end, a power transmission unit located on the power supply end, and a conductive connection element connecting the power receiving unit and the power transmission unit through fasteners. The conductive connection element establishes electric connection with the power receiving unit and the power transmission unit through the fasteners so that power supply provided by the power supply end is transmitted from the power transmission unit to the conductive connection element which in turn transmits the power to the system end through the power receiving unit. The power supply structure of the invention may be assembled and installed quickly.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: June 22, 2004
    Assignee: Shin Jiuh Corp.
    Inventors: Tzung-Han Lee, Edy Sung
  • Patent number: 6750396
    Abstract: A low impedance surface-mount connector includes a length of cylindrical rod having an I-shaped cross section. The device permits interconnection by pick-and-place techniques, and the interconnection has advantageous qualities of low resistance, low inductance, mechanical compliance and ease of manufacture. A first circuit device having one or more circuit components is interconnected with a second circuit device by surface mounting such connectors on the first circuit device, providing corresponding solder pads on the second circuit device, and mounting the connectors of the first circuit device onto the pads of the second.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: June 15, 2004
    Assignee: di/dt, Inc.
    Inventor: Apurba Roy
  • Patent number: 6747875
    Abstract: This improved surface mount power supply can withstand the rigors of the manufacturing process and still create sturdy and robust connection to a user's circuit card. The open frame power module uses a U-shaped or T-shaped interconnect rather than a spherical interconnect. In one embodiment, the U-shaped interconnect can have a hole through one surface to allow the wicking of solder. The wicked solder provides a sturdier connection that is more likely to survive subsequent reflow processes. The power module is also built on a thicker FR4 board. The thicker board is less likely to warp during subsequent heating.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: June 8, 2004
    Assignee: Innoveta Technologies
    Inventors: Carl Milton Wildrick, Gordon K. Y. Lee
  • Patent number: 6744638
    Abstract: A wiring board is arranged on the back side of a tape carrier package (TCP), the upper edge of a notch in the leftmost TCP and an outer edge of a branch of the leftmost terminal of the leftmost output terminal portion of the wiring board are arranged on the same plane, the lower edge and the outer edge of the branch are arranged on the same plane, and a terminal and the corresponding terminal of the output terminal portion are superposed on each other without a shift therebetween. Similarly, the upper end of a notch in the rightmost TCP and an outer edge of a branch of the rightmost terminal of the rightmost output terminal portion are arranged on the same plane, the lower edge and the outer edge of the branch are arranged on the same plane, and a terminal and the corresponding terminal of the output terminal portion are superposed on each other without a shift.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: June 1, 2004
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Shinji Terasaka
  • Patent number: 6741480
    Abstract: A method and apparatus for electrically interconnecting a first circuit board having a power conditioning circuit and a second circuit board having a power dissipating component disposed therebelow along a z (vertical) axis is disclosed. In an illustrative embodiment, the apparatus comprises a first flexible circuit having a first set of raised conductive contacts, the first flexible circuit disposed on a first side of the second circuit board; and a second flexible circuit having a second set of raised conductive contacts, the second flexible circuit disposed on a second side of the second circuit board opposing the first side of the second circuit board.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: May 25, 2004
    Assignee: Incep Technologies, Inc.
    Inventors: David H. Hartke, Joseph Ted DiBene, II
  • Publication number: 20040095736
    Abstract: A stack type multi-chip package with an increased reliability is provided. The stack type multi-chip package comprises a first semiconductor chip which shows good results when tested for reliability after being assembled at the package level, at least one second semiconductor chip which is in the wafer level and is stacked on the first semiconductor chip via stacking means, a first connecting unit for electrically connecting the first semiconductor chip to an external system, and a second connecting unit for electrically connecting the second semiconductor chip to the external system. The first connecting unit is different from the second connecting unit. Since the stack type multi-chip package comprises the semiconductor chip which shows good results when tested for reliability after being assembled at the package level, the reliability of the stack type multi-chip package can be effectively increased.
    Type: Application
    Filed: November 17, 2003
    Publication date: May 20, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yun-Ho Choi, Kyung-Ho Kim
  • Patent number: 6738263
    Abstract: A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: May 18, 2004
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Jerry M. Brooks, Walter L. Moden
  • Publication number: 20040090760
    Abstract: The electrical connecting element includes an essentially stiff core, essentially mechanically stiff and printed circuit boards and/or high density interconnects with conductor paths serving as interconnects. The core includes two parts (1, 3) that can be fixed to each other. Between the two parts, a cavity (101) can be formed. Components (103) producing a lot of heat or requiring protection from environmental influences can be placed in the cavity.
    Type: Application
    Filed: November 13, 2002
    Publication date: May 13, 2004
    Inventor: Walter Schmidt
  • Publication number: 20040090761
    Abstract: A circuit board assembly includes first and second circuit board devices. The first circuit board device includes a printed circuit board, a first controller mounted on the first printed circuit board, and a first communications unit mounted on the first printed circuit board and that is connected electrically to the first controller. The second circuit board device includes a second printed circuit board separate from the first printed circuit board, a second controller mounted on the second printed circuit board, and a second communications unit mounted on the second printed circuit board and connected electrically to the second controller. The second communications unit cooperates with the first communications unit to establish a communications link between the first and second controllers while maintaining separability between the first and second printed circuit boards.
    Type: Application
    Filed: December 31, 2002
    Publication date: May 13, 2004
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Pin Chuang, Chih-Chuan Cheng
  • Publication number: 20040085741
    Abstract: According to one embodiment, a printed circuit board (PCB) is disclosed. The PCB includes a first functional unit block (FUB) and differential traces coupled to the first FUB. The first FUB transmits high-speed serial data. The differential traces carry the high-speed serial data from the first FUB. In addition, the differential traces crossover on the same layer of the PCB while maintaining a constant impedance.
    Type: Application
    Filed: April 7, 2003
    Publication date: May 6, 2004
    Inventor: Dennis J. Miller
  • Patent number: 6731511
    Abstract: A wiring board includes a wiring pattern having a lands and a line connected to the land, a substrate supporting the wiring pattern, and a protective film provided over the substrate and having an opening. The land has a first portion which includes a connecting portion connected to the line and is covered by the protective film, and a second portion exposed by the opening. A hole for exposing the substrate is formed at least in the first portion of the land.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: May 4, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Hideki Yuzawa