Interconnection Details Patents (Class 361/803)
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Patent number: 7522428Abstract: Electric device, designed to be attached to a mounting rail, comprising a body fitted with means for locking onto the rail comprising at least one lug that can be moved between a locked position and an unlocked position, designed to interact with a first edge of the rail, the lug being subjected to the action of an elastic element placed in a housing of the body and pressing on the latter and on the movable lug, wherein the elastic element is of elongated shape, substantially rectilinear in a rest position, the housing comprising an opening for the insertion of the elastic element, placed substantially along the same axis as that of the elastic element in the rest position and leading to the outside of the body, on the lateral face of the body perpendicular to the longitudinal axis of the rail.Type: GrantFiled: September 12, 2007Date of Patent: April 21, 2009Assignee: ABB FranceInventor: Eric Nguyen
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Patent number: 7522425Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.Type: GrantFiled: October 9, 2007Date of Patent: April 21, 2009Assignee: Entorian Technologies, LPInventor: Paul Goodwin
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Publication number: 20090097803Abstract: An optical interconnect assembly provides board to board interconnect in an electronic system. The optical interconnect assembly can include a plurality of optical fibers, having a connector disposed at the first ends, and a rigid optical mount disposed at the second ends. The rigid optical mount holds the optical fibers in alignment and in optical communication with a plurality of optical transducers mounted on the optical mount. Electrical contacts coupled to the optical transducers enable solder-attachment of one end of the optical interconnect assembly to a circuit board.Type: ApplicationFiled: October 15, 2007Publication date: April 16, 2009Inventor: Jong-Souk Yeo
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Publication number: 20090097213Abstract: A daisy-chain optical interconnection technique provides connectivity among a plurality of circuit boards. A plurality of optical cables is connected between pairs of the circuit boards to form a ring. Optical connection matrices disposed on each circuit board accept the ends of the optical cables. The optical connection matrices include optical vias to connect selected ones of the optical paths between ends of the optical cables. Unselected ones of the optical paths are coupled to optical transmitters and optical receivers on each board.Type: ApplicationFiled: October 15, 2007Publication date: April 16, 2009Inventors: Robert Newton Bicknell, Pavel Kornilovich, Jong-Souk Yeo
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Patent number: 7518883Abstract: A multi-service network element is configurable for use in various types of communications networks. The network element has a service interface card, a service interface electrical connector for receiving the service interface card, an I/O electrical connector for receiving an I/O module, and a backplane. The backplane has a first side, an opposite side, a first means for electrically connecting the service interface electrical connector to the first side, and a second means for electrically connecting the I/O electrical connector to either side of the backplane. The backplane is partitioned into columns and rows of electrical connectors. Each column corresponds to a card slot for receiving a circuit pack and each row corresponds to a section of the backplane having traces for carrying a particular type of electrical signals between circuit packs.Type: GrantFiled: October 8, 2004Date of Patent: April 14, 2009Assignee: Nortel Networks LimitedInventors: Craig Suitor, Balwantrai Mistry, Doug Wong, Christopher Brown
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Patent number: 7518881Abstract: One embodiment of the present invention provides an apparatus that reduces voltage noise for an integrated circuit (IC) device. This apparatus includes an interposer, which is configured to be sandwiched between the IC device and a circuit board. This interposer has a bottom surface, which is configured to receive electrical connections for power, ground and other signals from the circuit board, and a top surface, which is configured to provide electrical connections for power, ground and the other signals to the IC device. A plurality of bypass capacitors are integrated into the interposer and are coupled between the power and ground connections for the IC device, so that the plurality of bypass capacitors reduce voltage noise between the power and ground connections for the IC device.Type: GrantFiled: July 20, 2007Date of Patent: April 14, 2009Assignee: Apple Inc.Inventor: William P. Cornelius
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Patent number: 7511965Abstract: In a circuit board device having an electronic component mounted on an electrode land on a board by reflow soldering, voids that adversely affect the solder joint in various ways are prevented from forming. The electrode land corresponding to a component electrode for the electronic component is divided into a plurality of land regions by solder resist having a prescribed width. The component electrode is laid above the solder resist so as to form a clearance communicating with the outside of the component electrode, so that gas generated by vaporization of a flux component contained in the solder during reflow-heating is passed through the clearances and let out of the component electrode. In this way, voids in the solder part can more readily be prevented from forming without increasing the number of person hours as compared to the conventional method.Type: GrantFiled: April 7, 2006Date of Patent: March 31, 2009Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takayasu Fujii, Isao Sonoda
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Patent number: 7511969Abstract: A circuit module is provided in which at least one secondary substrate and preferably two such secondary substrates are populated with integrated circuits (ICs). A rigid core substrate for the circuit module is comprised of a structural member and a connective member. In a preferred embodiment, the structural member is comprised of thermally conductive material while the connective member is comprised of conventional PWB material. The secondary substrate(s) are connected to the connective member with a variety of techniques and materials while, in a preferred embodiment, the connective member exhibits, in a preferred embodiment, traditional module contacts which provide an edge connector capability to allow the module to supplant traditional DIMMs.Type: GrantFiled: February 2, 2006Date of Patent: March 31, 2009Assignee: Entorian Technologies, LPInventor: James Douglas Wehrly, Jr.
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Patent number: 7511968Abstract: Multiple fully buffered DIMM circuits or instantiations are presented in a single module. In a preferred embodiment, memory integrated circuits (preferably CSPs) and accompanying AMBs are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete FB-DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.Type: GrantFiled: December 8, 2004Date of Patent: March 31, 2009Assignee: Entorian Technologies, LPInventor: Paul Goodwin
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Patent number: 7508063Abstract: Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the top surfaces of the top substrate and package substrate. The device can be a semiconductor device, a microstructure such as a microelectromechanical device, or other devices.Type: GrantFiled: April 5, 2005Date of Patent: March 24, 2009Assignee: Texas Instruments IncorporatedInventors: Robert M. Duboc, Terry Tarn
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Publication number: 20090073655Abstract: An electronic apparatus includes: a housing; a motherboard that is accommodated in the housing; a first daughterboard that is accommodated in the housing; a second daughterboard that is accommodated in the housing; a host controller that is mounted on the motherboard; a bridge controller that is mounted on the first daughterboard and electrically connected to the host controller; a first chip that is mounted on the first daughterboard and electrically connected to the bridge controller; and a second chip that is mounted on the second daughterboard and electrically connected to the bridge controller.Type: ApplicationFiled: May 12, 2008Publication date: March 19, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Masahiko Takakusaki, Minoru Enomoto
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Patent number: 7504668Abstract: A transponder assembly for use with fiber optic digital communication cables having multiple parallel optic fiber elements. The transponder assembly features a transmitter port and receiver port for connection with separate parallel optic cables for separately transmitting and receiving data and an electrical connector for connecting with computer or communication systems. The transponder assembly includes a parallel optic transmitter module and a parallel optic receiver module having pluggable edge connectors. The assembly also includes a circuit board on which a semiconductor chip useful for signal processing and the electrical connector are mounted. A flex circuit is used in connecting the circuit board to the parallel optic modules. The semiconductor chip and electrical connector are mounted directly across from one another on opposite surfaces of the circuit board.Type: GrantFiled: February 9, 2006Date of Patent: March 17, 2009Assignee: Stratos International, Inc.Inventors: William Wang, Hengju Cheng, WeiZen Lo
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Patent number: 7489524Abstract: An assembly is provided which includes a first circuit panel having a top surface, a first dielectric element and first conductive traces disposed on the first dielectric element. In addition, a second circuit panel has a bottom surface, a second dielectric element and second conductive traces disposed on the second dielectric element, where at least a portion of the second circuit panel overlies at least a portion of the first circuit panel. The assembly further includes an interconnect circuit panel having a third dielectric element which has a front surface, a rear surface opposite the front surface, a top end extending between the front and rear surfaces, a bottom end extending between the front and rear surfaces, and a plurality of interconnect traces disposed on the dielectric element.Type: GrantFiled: June 2, 2005Date of Patent: February 10, 2009Assignee: Tessera, Inc.Inventors: Ronald Green, Sridhar Krishnan, Stuart E. Wilson, James Gill Shook, Ming Tsai, Andy Stavros
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Patent number: 7489521Abstract: A multilayer printed wiring board (10) includes: a build-up layer (30) that is formed on a core substrate (20) and has a conductor pattern (32) disposed on an upper surface; a low elastic modulus layer (40) that is formed on the build-up layer (30); lands (52) that are disposed on an upper surface of the low elastic modulus layer (40) and connected via solder bumps (66) to a IC chip (70); and conductor posts (50) that pass through the low elastic modulus layer (40) and electrically connect lands (52) with conductor patterns (32). The conductor posts (50) have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 ?m, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer (40), is greater than or equal to the aspect ratio Rasp of internal conductor posts (50b), which are positioned at internal portions of the low elastic modulus layer (40).Type: GrantFiled: July 17, 2007Date of Patent: February 10, 2009Assignee: Ibiden Co., Ltd.Inventors: Takashi Kariya, Toshiki Furutani
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Publication number: 20090034222Abstract: A printed circuit board assembly includes a first printed circuit board having a plurality of electrical traces that is attached to a second printed circuit board having a plurality of electrical traces in a substantially perpendicular fashion. The first printed circuit board has a plurality of male terminal tabs that fit into a plurality of female terminal slots of the second printed circuit board to make a plurality of electrical connections between the electrical traces of the first printed circuit board and the electrical traces of the second printed circuit board. The assembly has at least two mechanical connections between the first printed circuit board and the second printed circuit board comprising connector blades that are substantially perpendicular to the first printed circuit board and to the second printed circuit board. The connector blades may also make electrical connections between electrical traces of the first and second printed circuit boards.Type: ApplicationFiled: August 1, 2007Publication date: February 5, 2009Inventors: Mark W. Smith, Christopher A. Brandon
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Patent number: 7483276Abstract: Disclosed is a semiconductor package adapted to be light, slim, compact, and suitable for high-density mounting and a method for manufacturing the same. The semiconductor package includes a semiconductor chip; a plurality of active/passive devices; a first PCB acting as a main board, the semiconductor chip and devices selected from the plurality of active/passive devices being mounted on the first PCB, the devices including a highest device; and at least one sub-PCB, remaining devices of the plurality of active/passive devices being mounted on the sub-PCB, the sub-PCB having a through-hole, at least the highest device on the first PCB extending through the through-hole, so that the sub-PCB is connected to the first PCB and positioned in a space above the first PCB while overlapping the first PCB.Type: GrantFiled: June 20, 2006Date of Patent: January 27, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Kweun Kim, Ho-Seong Seo, Seok-Myong Kang, Youn-Kyoung Gil
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Publication number: 20090020332Abstract: An interconnection structure for circuit board and terminal members improves a configuration of a terminal member to be soldered to conductors on boards, and relaxes a stress applied to soldered portions, thereby preventing the soldered portions from a problem, such as cracking. An interconnection structure for circuit boards and terminal members includes two boards positioned away from each other.Type: ApplicationFiled: June 20, 2008Publication date: January 22, 2009Applicant: SUMITOMO WIRING SYSTEMS, LTD.Inventor: Takayuki Sano
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Patent number: 7480152Abstract: A flexible circuit is populated with integrated circuits. Integrated circuits populated on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. In a preferred embodiment, the overall module profile does not, consequently, include the thickness of the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flex circuit may be aligned using tooling holes in the flex circuit and substrate. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs.Type: GrantFiled: December 7, 2004Date of Patent: January 20, 2009Assignee: Entorian Technologies, LPInventor: Paul Goodwin
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Patent number: 7477526Abstract: A branching fully-buffered memory module has one uplink port and two downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the two downlink ports to two branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory module has re-timing and re-synchronizing buffers that repeat frames to the two downlink ports. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin count. Sync patterns are added to the start of frames to detect any collisions on bidirectional lines. Point-to-point bus segments have only two endpoints despite branching by the branching AMB. Latency from the host processor to the last memory module is reduced by branching compared with a serial daisy-chain of memory modules.Type: GrantFiled: December 29, 2005Date of Patent: January 13, 2009Inventor: Ramon S. Co
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Patent number: 7474540Abstract: A silicon carrier package includes a multi-layer member having at least a first layer and a second layer. A first electronic component includes a plurality of connector members that establish a first bond electrically interconnecting the first electronic component to the multi-layer member. A second electronic component includes a plurality of connector members that establish a second bond electrically interconnecting the second electronic component to the multi-layer member. At least one heating element is integrated into one of the first and second layers of the multi-layer member. The at least one heating element is selectively activated to loosen only one of the first and second bonds to facilitate removal of only one of the first and second electronic components from the multi-layer member. The other of the first and second bonds remains intact.Type: GrantFiled: January 10, 2008Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Bing Dang, Steven L. Wright
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Toolless method for alignment, retention, connection, termination and test on printed circuit boards
Patent number: 7466562Abstract: Embodiments of the present invention provide a system for testing and mounting a PCB in a device. A PCB may be placed on one or more standoffs so that a head portion of the standoff protrudes from one or more apertures of the PCB. A push-pin type standoff cap may then be placed on the protruding heads to mechanically restrain the PCB to the standoffs. Furthermore, one or more cables may be coupled with the standoff caps to provide power or test signals to one or more connector pads on the PCB. Therefore, the standoff caps provide a system for aligning, retaining, connecting, terminating, and testing printed circuit boards.Type: GrantFiled: July 20, 2006Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Don A. Gilliland, Guy A. Thompson -
Publication number: 20080298037Abstract: A mounting panel arrangement having a plurality of mounting panels for optoelectronic components. Two adjacent mounting panels (1, 2) are connected to one another, in a mechanically stable manner, a connection body (3). Each of the two mounting panels has a connection area (110, 210), each of which is associated with an attachment section (31, 32) of the connection body. For each connection area, a plug connection is formed between the connection area and the associated attachment section.Type: ApplicationFiled: February 19, 2008Publication date: December 4, 2008Applicant: Patent-Treuhand-Gesellschaft fur elektrischeInventors: Robert Kraus, Wolfgang Georg Pabst, Harald Stoyan
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Patent number: 7458821Abstract: According to some embodiments, a connector to receive a memory module includes a first row of a first plurality of interconnect ends, a second row of a second plurality of interconnect ends adjacent to the first row, and a third row of a third plurality of interconnect ends adjacent to the second row. An interconnect end of the first plurality of interconnect ends, an interconnect end of the second plurality of interconnect ends, and an interconnect end of the third plurality of interconnect ends may be substantially aligned.Type: GrantFiled: December 7, 2005Date of Patent: December 2, 2008Assignee: Intel CorporationInventors: Dan Willis, David Kraus
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Patent number: 7453699Abstract: A digital electronic apparatus includes a plurality of units and a cable. The plurality of units have metallic housings and are combined such that surfaces of the metallic housings are opposed to each other. The cable is laid on a surface of the metallic housing of at least one of the units. The surface on which the cable is laid is other than the surfaces of the metallic housings that are opposed to each other.Type: GrantFiled: January 19, 2007Date of Patent: November 18, 2008Assignee: Canon Kabushiki KaishaInventors: Hideho Inagawa, Hiroyuki Yamaguchi, Shin'ichi Nishimura, Daishiro Sekijima, Tsunao Hombo, Masafumi Kamei
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Publication number: 20080278924Abstract: A flex circuit is populated on one or both sides with plural integrated circuit die. In a preferred mode, the flex circuit is populated with flip-chip die. One side of the flex circuit has a connective facility implemented in a preferred mode with edge connector contacts. The flex circuit is disposed about a substrate to form a circuit module that may be inserted into an edge connector such as ones typically found on a computer board.Type: ApplicationFiled: June 26, 2008Publication date: November 13, 2008Inventors: James W. Cady, Paul Goodwin
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Publication number: 20080278923Abstract: An electronic system adapted to perform a corresponding function and including at least a first subsystem and a second subsystem, the first subsystem and the second subsystem being operatively couplable to each other through a plurality of electric connections to perform the function of the system, in which the first subsystem and the second subsystem are respectively integrated on a first material chip and on a second material chip, the plurality of electric connections including a plurality of conductive through holes formed in at least one of the first and second chips and adapted to form a corresponding plurality of inter-chip electric connections when the first and the second chips are superimposed.Type: ApplicationFiled: May 7, 2008Publication date: November 13, 2008Applicant: STMicroelectronics S.R.L.Inventors: Aldo Losavio, Giovanni Campardo, Stefano Ricciardi
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Patent number: 7447044Abstract: A fixing mechanism for securing a printed circuit board (10) to a computer chassis, includes a fixing board (20), a tray (60) for securing the printed circuit board, and a driving device (40). The fixing board forms a number of fastening portions (21) to engage in fastening holes (65) of the tray. The driving device includes a sliding board (41) slidably attached to the fixing board, a pull handle (47) pivotally connected to the fixing board, a connecting block (43) arranged to the pull handle, and a linking element (45). The linking element connects the connecting block to the sliding board, the tray is connected to the sliding board. The pull handle is rotated to move the tray between a locked position and an unlocked position.Type: GrantFiled: August 22, 2005Date of Patent: November 4, 2008Assignees: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventor: Ji-Guo Xu
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Patent number: 7446421Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.Type: GrantFiled: January 4, 2007Date of Patent: November 4, 2008Assignee: Industrial Technology Research InstituteInventors: Su-Tsai Lu, Shu-Ming Chang, Shyh-Ming Chang, Yao-Sheng Lin, Yuan-Chang Huang
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Patent number: 7445156Abstract: A data management device and library are provided for organizing, holding, and providing electrical connectivity to multiple memory cards. The data management device can comprise a device body, a plurality of sockets to accommodate the data storage media, an electrical connector, and a power management circuit. Data can be retrieved from or transferred to the selected memory cards utilizing the device. The data management library can be utilized to interconnect multiple devices and can be daisy chained to other libraries.Type: GrantFiled: October 3, 2006Date of Patent: November 4, 2008Inventor: James A. McDonald
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Publication number: 20080266823Abstract: A circuit board assembly (100) includes a circuit board (10) and at least one electrical element (20). The circuit board includes a dielectric substrate (12) including a supporting surface (13), and at least one connecting part (14) formed on the supporting surface. The at least one electrical element is electrically connected to the at least one connecting part via a connecting media (28). At least one air-exhaust hole (16) extends through the connecting part and the dielectric substrate. The at least one air-exhaust hole is configured for exhausting air from the connecting media.Type: ApplicationFiled: September 26, 2007Publication date: October 30, 2008Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: FU-YEN TSENG
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Patent number: 7442879Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a binder component and at least one metallic component including microparticles. In another embodiment, the paste includes the binder and a plurality of nano-wires. Selected ones of the microparticles or nano-wires include a layer of solder thereon. A method of making such a substrate is also provided, as are an electrical assembly and information handling system adapter for having such a substrate as part thereof.Type: GrantFiled: October 6, 2005Date of Patent: October 28, 2008Assignee: Endicott Interconect Technologies, Inc.Inventors: Rabindra N. Das, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich
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Patent number: 7443844Abstract: A switched fabric mezzanine storage module (560) includes a storage module (562) and a switched fabric connector (563) coupled to the storage module. The storage module is coupled to directly communicate with a switched fabric (506), where the switched fabric storage mezzanine module is coupled to a payload module (502) having one of a 3U form factor, a 6U form factor and a 9U form factor. The payload module can include at least one multi-gigabit connector (518) coupled to a rear edge (519) of the payload module, where the at least one multi-gigabit connector is coupled to communicatively interface with a backplane (504).Type: GrantFiled: September 23, 2004Date of Patent: October 28, 2008Assignee: Emerson Network Power - Embedded Computing, Inc.Inventors: Douglas L. Sandy, Jeffrey M. Harris, Robert C. Tufford
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Patent number: 7443692Abstract: A power converter utilizes a high frequency capacitor and a bulk capacitor coupled across the DC terminals to reduce high frequency effect and voltage overshoot, leading to space and cost savings in power converter design. Each capacitor may be physically coupled adjacent the gate driver board via clips, clamps, and/or fasteners.Type: GrantFiled: September 17, 2003Date of Patent: October 28, 2008Assignee: Continental Automotive Systems US, Inc.Inventors: Ajay V. Patwardhan, Douglas K. Maly, Sayeed Ahmed, Fred Flett
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Patent number: 7443696Abstract: A connecting apparatus comprises a riser card (10) and a slot (20). The riser card comprises a PCI-X slot (13), a PCI-E slot (11), a first connector (15), a second connector (17) and a third connector (19). The first connector set a serial of PCI-X signal pads (151) on one side thereof. The second connector is adapted to provide power and ground signals. The third connector set a serial of PCI-E signal pads (191) on the same side thereof as the first connector. The slot is defined on a circuit board for the riser card inserted therein. The slot comprises a first portion (21) and a second portion (23) coupling to the second connector. The first portion comprises a first side with a series of PCI-X signal pins (211) coupling to the serial of PCI-X signal pads of the first connector, when the riser card is inserted into the slot in a first direction with the first connector inserted into the first portion.Type: GrantFiled: October 27, 2005Date of Patent: October 28, 2008Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Jun Lin, Thomas Duane Wright
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Patent number: 7440450Abstract: A multi-service platform system, includes a backplane (104), a switched fabric (106) on the backplane, and at least one of a VMEbus network and a PCI network coincident with the switched fabric on the backplane. A payload module (102) has one of a 3U form factor, a 6U form factor and a 9U form factor, where the payload module is communicatively coupled with the backplane using the switched fabric and at least one of the VMEbus network and the PCI network. At least one multi-gigabit connector (118) is coupled to a rear edge (119) of the payload module, where the at least one multi-gigabit connector is coupled to communicatively interface the payload module to the backplane, and where the switched fabric and at least one of the VMEbus network and the PCI network are communicatively coupled with the payload module through the at least one multi-gigabit connector.Type: GrantFiled: September 23, 2004Date of Patent: October 21, 2008Assignee: Emerson Network Power-Embedded Computing, Inc.Inventors: Jeffrey M. Harris, Douglas L. Sandy, Robert C. Tufford
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Publication number: 20080253102Abstract: Electronic devices are disclosed that allow for surface-mounting using solder while preventing solder from overflowing between external terminals of the electronic device, or between pads on a circuit board to which the external terminals are soldered. An exemplary electronic device has a base board made of an insulating material and having an outer surface comprising at least one external terminal for surface mounting of the device to the circuit board. A groove is defined at least part way around the external terminal on the outer surface. The groove accommodates overflowed solder and thus prevents unintended spread flow of the solder to locations that otherwise could cause short circuits and the like. The electronic device can include a resin board containing a thermoset resin, wherein the groove is formed by thermal or mechanical processing.Type: ApplicationFiled: April 10, 2008Publication date: October 16, 2008Inventor: Tomotaka Kuroda
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Publication number: 20080253101Abstract: The present invention provides a liquid crystal display device which can establish the reliable connection between a printed circuit board and a semiconductor device in spite of the simple constitution thereof. The liquid crystal display device includes a liquid crystal display panel, a printed circuit board arranged close to the liquid crystal display panel, and a semiconductor device arranged between the liquid crystal display panel and the printed circuit board in a striding manner. The semiconductor device includes a flexible printed circuit board and a semiconductor chip. The flexible printed circuit board includes a plurality of first terminals connected to the printed circuit board and a plurality of second terminals connected to a liquid-crystal-display-panel side.Type: ApplicationFiled: March 12, 2008Publication date: October 16, 2008Inventors: Yuuichi Takenaka, Hiromitsu Sato, Takanori Sato, Kazumi Akiba, Yoshihiro Kazuma
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Patent number: 7433192Abstract: An electronic module has a non-conducting substrate having at least one opening and a die/carrier assembly mounted within the opening in the substrate. The assembly has a conducting carrier and one or more integrated circuit (IC) dies mounted to the carrier. The invention may be implemented as an electronic system comprising a circuit board (CB) and at least one such electronic module mounted to the CB.Type: GrantFiled: February 10, 2005Date of Patent: October 7, 2008Assignee: Agere Systems Inc.Inventors: Timothy B. Bambridge, Juan A. Herbsommer, Osvaldo Lopez, Joel M. Lott, Hugo F. Safar, Thomas H. Shilling
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Publication number: 20080232076Abstract: The invention comprises a unit part 3 that is attachable/detachable to/from a frame 100; and an engagement device that enables the unit part 3 to be attachable/detachable to/from the frame 100 and comprises; an engagement pin 90 diposed at one of the frame 100 and the unit part 3; and an engagement member 51 disposed at the other of the frame and the unit part, having a recess engaged with the engagement pin 90. The engagement member 51 is pivotably supported and, when the recess 54 is pivoted to separate from the engagement pin 90, moves the unit part 3 in a direction of separating from the frame 100 by the pivoting.Type: ApplicationFiled: March 20, 2008Publication date: September 25, 2008Applicants: Aruze Corp., Seta Corp.Inventor: Kazuei YOSHIOKA
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Patent number: 7426118Abstract: To cancel a magnetic field in an interconnection pattern of a printed wiring board. A first interconnection pattern 3a is formed on a surface 1a of an insulating substrate 1. A second interconnection pattern 5a is formed on a bottom surface 1b of the insulating substrate 1 so as to be superposed on a meandering part of the first interconnection pattern 3a when viewed from the upper surface side. An end part 5b of the second interconnection pattern 5a is electrically connected to an end part 3d of the first interconnection pattern 3a via through holes 7a. The first interconnection pattern 3a and the second interconnection pattern 5a form a single interconnection line via the through holes 7a. Accordingly, the first interconnection pattern 3a and the second interconnection pattern 5a are 180° different from each other in the direction in which current flows.Type: GrantFiled: May 11, 2005Date of Patent: September 16, 2008Assignee: Ricoh Company, LtdInventor: Kunihiro Tan
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Cable assemblies for connecting data storage chassis to a cable conduit within a data storage system
Patent number: 7425685Abstract: A chassis housing disk drives has an electrical plug and an electrical signal connector at its back end. A rack has a compartment for receiving the chassis. A cable conduit mounted to a rack sidewall adjacent the compartment abuts the back end of the chassis. A first cable assembly coupled to the cable conduit includes an electrical plug receptacle and a first cable extending through the cable conduit for conducting power to the electrical plug receptacle. A second cable assembly coupled to the cable conduit includes a data signal connector and a second cable extending through the cable conduit for conducting data signals to and from the data signal connector. The electrical plug receptacle receives the electrical plug and the data signal connector receives the electrical signal connector of the chassis, concurrently, when the chassis slides into the compartment fully, to supply power to and establish communications with the chassis.Type: GrantFiled: September 28, 2006Date of Patent: September 16, 2008Assignee: EMC CorporationInventors: C. Ilhan Gundogan, W. Brian Cunningham, Joseph P. King, Jr. -
Patent number: 7423885Abstract: A flex circuit is populated on one or both sides with plural integrated circuit die. In a preferred mode, the flex circuit is populated with flip-chip die. One side of the flex circuit has a connective facility implemented in a preferred mode with edge connector contacts. The flex circuit is disposed about a substrate to form a circuit module that may be inserted into an edge connector such as ones typically found on a computer board.Type: GrantFiled: June 21, 2005Date of Patent: September 9, 2008Assignee: Entorian Technologies, LPInventors: James W. Cady, Paul Goodwin
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Patent number: 7420813Abstract: A fastening structure for stacking a plurality of electronic modules on a mainboard is provided. The fastening structure includes a locking member and a plurality of supporting members. The locking member is disposed on a first electronic module for locking the first electronic module onto the mainboard by locking elements. The supporting members are connected to the locking member and are used to carry a second electronic module above the first electronic module. Therefore, under a limited space for disposing the first/second electronic modules, the fastening structure of the present invention increases the space utilization, thereby enhancing the strength of the structure for the first/second electronic modules.Type: GrantFiled: February 16, 2007Date of Patent: September 2, 2008Assignee: Inventec CorporationInventor: Chu-Hsin Yang
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Patent number: 7420127Abstract: The present invention provides a method of manufacturing a multilayer wiring substrate, which can preserve the dimensional stability of a conductor pattern at a fine pitch, solve the restriction on a process from the viewpoint of material selection, and further reduce a manufacturing cost, and a multilayer wiring substrate. A second wiring substrate formed on a supporting sheet made of metal and an adhesive layer are partially stacked on a predetermined region of a first wiring substrate by using the supporting sheet. After the lamination of the second wiring substrate, the supporting sheet is finally etched and removed. The second wiring substrate is stacked only on the portion required to be multilayered on the first wiring substrate to thereby reduce the amount of the construction material of the second wiring substrate.Type: GrantFiled: December 22, 2006Date of Patent: September 2, 2008Assignee: Sony CorporationInventors: Hiroshi Asami, Hidetoshi Kusano, Yuji Nishitani, Ken Orui
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Patent number: 7420821Abstract: An electronic module includes an electronic circuit substrate, and a plurality of driving circuit boards attached to a terminal region of the electronic circuit substrate while being arranged adjacent to one another in the x direction. The driving circuit boards are electrically connected to one another. Adjacent driving circuit boards are electrically connected to each other by only substrate terminals provided on the electronic circuit substrate, with the connection resistance therebetween being about 10 ? or less.Type: GrantFiled: September 2, 2003Date of Patent: September 2, 2008Assignee: Sharp Kabushiki KaishaInventor: Yoichiro Sakaki
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Patent number: 7419381Abstract: A hybrid circuit board includes a first circuit board and a second circuit boards. The first circuit board includes a first body having a slot, and a first circuit pattern formed on the first body and extended to the slot. The second circuit board includes a second body, a protruding portion, a second circuit pattern, and a separating member. The protruding portion extends from the second body. The protruding portion is inserted into the slot of the first circuit board to combine the second circuit board to the first circuit board. The second circuit pattern is formed on the second body to be extended to the protruding portion, so that the second circuit pattern is electrically connected to the first circuit pattern of the first circuit board. The separating member is disposed between the second body and the protruding portion to separate the protruding portion from the second body.Type: GrantFiled: August 27, 2007Date of Patent: September 2, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyeon-Yong Jang, Cheol-Jin Park
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Publication number: 20080205019Abstract: A method for connecting circuit boards, comprising: (i) preparing a first circuit board having connection parts assigned to end parts of a plurality of conductor wirings, and a second circuit board having connection parts assigned to corresponding end parts of a plurality of conductor wirings; (ii) disposing the connection parts of the first circuit board to face the connection parts of the second circuit board with a thermosetting adhesive film between the connection parts of the circuit boards; and (iii) applying heat and pressure to the connection parts and to the thermosetting adhesive film sufficiently high to thoroughly push away the adhesive film so as to establish electrical contact between connection parts of the circuit boards facing each other and to allow for curing of the adhesive; wherein the conductor wirings constituting the connection parts of at least one of the first and second circuit boards contain non-linear wirings.Type: ApplicationFiled: June 21, 2006Publication date: August 28, 2008Inventors: Yoshiaki Sato, Kohichiro Kawate, James R. White
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Patent number: 7414312Abstract: A memory module substrate printed-circuit board (PCB) has multi-type footprints and an edge connector for mating with a memory module socket on a motherboard. Two or more kinds of dynamic-random-access memory (DRAM) chips with different data I/O widths can be soldered to solder pads around the multi-type footprints. When ×4 DRAM chips with 4 data I/O pins are soldered over the multi-type footprints, the memory module has a rank-select signal that drives chip-select inputs to all DRAM chips. When ×8 DRAM chips with 8 data I/O pins are soldered over the multi-type footprints, the memory module has two rank-select signals. One rank-select drives chip-select inputs to front-side DRAM chips while the second rank-select drives chip-select inputs to back-side DRAM chips. Wiring traces on the PCB cross-over data nibbles between the solder pads and the connector to allow two ×4 chips to drive a byte driven by only one ×8 chip.Type: GrantFiled: May 24, 2005Date of Patent: August 19, 2008Assignee: Kingston Technology Corp.Inventors: Henry H. D. Nguyen, Mark Burlington
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Patent number: 7408782Abstract: A mechanical set of plates is able to simultaneously and quickly removably secure and remove one or more printed circuit boards (PCBs) in an enclosure in one single motion, and act as a heat sink to conduct heat away from the PCBs. The PCBs are removably secured through a clamping mechanism that may be a screw type or cam lever action by clamping down on the exposed card edges, thus allowing thermal transfer to begin on all cards. The apparatus may be used with any enclosure requiring thermal transfer from PCBs to the enclosure, including cages and enclosures that may or may not use forced airflow (fans or blowers) for heat dissipation.Type: GrantFiled: January 4, 2007Date of Patent: August 5, 2008Assignee: Tellabs Bedford, Inc.Inventors: David M. Austin, Daniel J. Calanni, Lawrence M. Giacoma, Jay H. Dorval
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Patent number: 7404250Abstract: A method of fabricating a printed circuit board having a coaxial via, includes. The method includes assembling a plurality of layers configured in a stack so that the plurality of layers has a top signal layer and a bottom signal layer; forming a hollow via through the plurality of layers to connect GND layers in the printed circuit board, forming or inserting into the hollow via a conductor coated with non-conductive material, covering the top layer and bottom layer with dielectric and patterned signal layers, covering the top layer and bottom layer with a masking agent, plating the top layer and bottom layer with a conductive material that connects signal traces within via, and removing the masking agent from the top layer and bottom layer.Type: GrantFiled: December 2, 2005Date of Patent: July 29, 2008Assignee: Cisco Technology, Inc.Inventors: Wheling Cheng, Roger Karam, Sergio Camerlo