Abstract: A power conversion device includes a cooler, a terminal block and a case. The cooler defines an internal space through which a refrigerant flows. The terminal block covers a conducive part. The case accommodates the cooler and the terminal block therein. The case has an opening on its lateral wall portion for allowing connection between the conductive part of the terminal block inside the case and an external load disposed outside the case. At least a part of the terminal block is located closer to the opening than the cooler in a first direction to which an inner surface and an outer surface of the lateral wall portion of the case defining the opening are opposed, and is located between the cooler and an upper end of the opening in a second direction orthogonal to the first direction.

Abstract: A power distribution unit including a plurality of outlet cores arranged along an outlet panel of a housing and mounted to one or more circuit boards with an unobstructed space between adjacent pairs of the plurality of outlet cores. The outlet cores each extend a portion of the distance between the circuit boards and the outlet panel, and the outlet panel includes a plurality of apertures each corresponding to an associated one of the plurality of outlet cores. One or more overcurrent protection devices are mounted in a non-outlet panel aligned along the length of the housing.

Abstract: A flexible electronic structure includes a first film, made of a first polymer or glass, and a second film, made of a second polymer, in which at least one electronic component is arranged. The second film covers the first film. The flexible electronic structure also includes at least one electrically conductive track arranged between the first film and the second film, and each electrically connected to one of the electronic components, by a respective interconnection element. Optionally, the flexible electronic structure includes a third film, made of a third polymer or glass, covering the second film. The interconnection element is arranged near the neutral plane of the structure, and the structure includes at least one compensation layer, so as to position the neutral plane at a desired location.

Abstract: A display device includes: a display module having a first non-foldable region, a second non-foldable region, and a foldable region disposed between the first non-foldable region and the second non-foldable region and being foldable about a folding axis extending in a first direction; and a barrier layer disposed adjacent the display module and including: a first portion having a first region overlapping the first non-foldable region, a second region overlapping the foldable region, and a third region overlapping the second non-foldable region; and a second portion extending from at least a portion of the second region of the first portion in the first direction.

Abstract: Semiconductor assemblies including thermal management configurations for reducing heat transfer between overlapping devices and associated systems and methods are disclosed herein. A semiconductor assembly may comprise a first device and a second device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the first and second devices. The thermally conductive layer and/or the thermal-insulator interposer may be configured to reduce heat transfer between the first and second devices.

Abstract: The semiconductor device according to the present invention includes a semiconductor module, a cooling member, and a heat transfer member. The semiconductor module includes a switching element and a diode connected in antiparallel to each other. The heat transfer member is disposed between the semiconductor module and the cooling member so as to transfer heat generated by the switching element and the diode to the cooling member. The heat transfer member has a mounting surface on which the switching element and the diode are mounted side by side and a surface which is opposite to the mounting surface and is disposed in contact with the cooling member. In the heat transfer member, the thermal conductivity in a first direction parallel to the mounting surface is higher than the thermal conductivity in a second direction perpendicular to the mounting surface.

Abstract: In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive.

Abstract: Provided is a display device, including a body structure, a flexible display panel arranged on the body structure, a primary adhesive layer, and an elastic connection structure, wherein the body structure comprises at least two unfoldable portions and a first foldable portion between the two adjacent unfoldable portions, and the first foldable portion comprises a hinge structure. The primary adhesive layer is arranged between the flexible display panel and the unfoldable portions, and the elastic connection structure is arranged between the body structure and the flexible display panel, and the elastic connection structure is configured to enable a second foldable portion of the flexible display panel to be switched between a folded state and a flattened state.

Abstract: Transistor structures including a fin structure having multiple graded III-N material layers with polarization layers therebetween, integrated circuits including such transistor structures, and methods for forming the transistor structures are discussed. The transistor structures further include a source, a drain, and a gate coupled to the fin structure. The fin structure provides a multi-gate multi-nanowire confined transistor architecture.

Abstract: Disclosed are a triode packaging method and a triode. The method includes: providing a carrier, and covering at least one surface of the carrier with a surface metal layer; covering a circuit pattern region of the surface metal layer with a resist film; electroplating a non-circuit pattern region of the surface metal layer, to form at least one first bonding pad; welding a chip on the at least one first bonding pad; welding a second bonding pad on the chip to form a triode template; performing plastic packaging on the triode template by using a composite material; drilling blind holes in vertical directions of the second bonding pad and the at least one first bonding pad, and processing the blind holes into metallic blind holes; and performing pattern fabrication on the metallic blind holes to form a closed-circuit loop or a non-closed-circuit loop, and obtaining a triode through packaging.

Abstract: A power semiconductor module arrangement includes a semiconductor substrate arranged in a housing, and a mounting arrangement including a frame or body, and at least one terminal element coupled to the frame or body. The mounting arrangement is inserted in and coupled to the housing. The mounting arrangement has a lower surface which, when the mounting arrangement is inserted in and coupled to the housing, rests on at least one contact surface of the housing. When the mounting arrangement is inserted in and coupled to the housing, the at least one terminal element mechanically and electrically contacts the semiconductor substrate with a first end, and a distance between an upper surface of the semiconductor substrate and the at least one contact surface in a vertical direction equals a length of the first end between the upper surface of the semiconductor substrate and the lower surface of the mounting arrangement.

Abstract: A semiconductor device includes an insulating layer, a conductive member provided inside the insulating layer, a chip disposed on a first surface of the insulating layer and connected to the conductive member, and an electrode connected to the conductive member via a barrier layer. A resistivity of the barrier layer is higher than a resistivity of the conductive member. At least a portion of the electrode protrudes from a second surface of the insulating layer.

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

Abstract: Systems and methods for producing individualized processing chips, each individualized processing chip being arranged to carry out a common processing operation are disclosed. A processing chip design is received, wherein the common processing operation is specified, at least in part, by the processing chip design. For each individualized processing chip the processing chip design is individualized to produce an individualized processing chip design, in accordance with an individualized set of transformations for the individualized processing chip, by including a respective set of modifications as part of the individualized processing chip design that implement the individualized set of transformations. Each transformation of the individualized set of transformations is a transform for an interconnect, specified in the processing chip design, of at least two logic cells specified in the processing chip design.

Abstract: Techniques and mechanisms for operating transistors that are in a stacked configuration. In an embodiment, an integrated circuit (IC) device includes transistors arranged along a line of direction which is orthogonal to a surface of a semiconductor substrate. A first epitaxial structure and a second epitaxial structure are coupled, respectively, to a first channel structure of a first transistor and a second channel structure of a second transistor. The first epitaxial structure and the second epitaxial structure are at different respective levels relative to the surface of the semiconductor substrate. A dielectric material is disposed between the first epitaxial structure and the second epitaxial structure to facilitate electrical insulation of the channels from each other. In another embodiment, the stacked transistors are coupled to provide a complementary metal-oxide-semiconductor (CMOS) inverter circuit.

Abstract: A method and an apparatus for welding a first object to a second object, wherein the first object is produced from a thermoset and comprises a thermoplastic material outer layer, wherein the second object comprises at least one thermoplastic material outer layer. In addition, a layer of carbon nanotubes is applied to the thermoplastic material outer layer of the first object, and the second object is placed onto the first object. At least some of the thermoplastic material outer layer of the second object lies atop the applied layer of carbon nanotubes. In addition, a potential is applied to the layer of carbon nanotubes, such that an electrical current flows through the carbon nanotubes, wherein the thermoplastic material outer layer of the first object and the thermoplastic material outer layer of the second object are heated and are welded to one another.

Abstract: This inverter, for electrical connection to a DC voltage source to supply an electric charge with three-phase current, includes a capacitive filter and a switching cell including, for each phase, a switching mode power supply circuit formed by two sets of controlled switches. Each set of controlled switches supplies a separate terminal of the switching cell, which also includes a sealed housing containing the switching mode power supply circuits. The housing is provided, on two opposite surfaces, with heat exchange means with a heat transfer fluid. A distributor is mounted, upstream from the housing, in a heat transfer fluid circulation circuit, to steer the heat transfer fluid toward the two opposite surfaces of the housing. The capacitive filter is cooled using at least one heat pipe. Part of this heat pipe, where the condensation of a fluid contained in the heat pipe occurs, is in thermal contact with the distributor.

Abstract: A slot module and an electronic device using the same are provided. The slot module includes a base, a slot member, a heat sink and a position limiting member. One end of the slot member is pivotally connected to the base, such that the slot member is adapted to rotate relative to the base, and a functional element is adapted to be inserted into the slot member. The heat sink and the position limiting member are all disposed on the base, wherein the position limiting member is adapted to be rotated from a first position to a second position to buckle the slot member, such that the functional component inserted into the slot member contacts the heat sink.

Abstract: A motor drive apparatus driving a motor as a three-phase motor converting direct power into three-phase alternating power, includes: inverter modules equivalent in number to phases of the motor; and a control unit generating PWM signals used to drive the inverter modules with PWM. The inverter modules each include a plurality of switching element pairs connected in parallel, each of the switching element pairs including two switching elements connected in series.

Abstract: An electronic device includes a package substrate, a circuit assembly, and a housing. The circuit assembly is mounted on the package substrate. The circuit assembly includes a first sealed cavity formed in a device substrate. The housing is mounted on the package substrate to form a second sealed cavity about the circuit assembly.

Abstract: A power module which comprises a semiconductor chip, at least one cooling plate with at least one cooling channel thermally coupled to the semiconductor chip and being configured so that a coolant is guidable through the at least one cooling channel, and an encapsulant encapsulating at least part of the semiconductor chip and part of the at least one cooling channel, wherein at least part of a main surface of the cooling plate forms part of an external surface of the power module.

Abstract: A process for thermoforming a circuit onto a three-dimensional part comprises applying electrically conductive lines on a substrate to form a flexible circuit. The flexible circuit is heated to a temperature sufficient to thermoform the substrate into a shape that conforms to said three-dimensional part and attached to the three-dimensional part.

Abstract: An Omedia panel may be provided that includes an at least one network interface device, a housing, and a front panel. The at least one network interface device might be in communication with a service provider network. The housing may be integrated into a wall of a customer premises and positioned within a wall cavity of the wall. The housing might be configured to support the at least one network interface device. The front panel may be communicatively interfaced with the at least one network interface device such that a user can access one or more ports of the at least one network interface device via the front panel.

Abstract: A digital podium apparatus includes: a frame; an extended handle disposed on the digital podium frame with which change of direction of movement is actuated, wherein a user can change direction by rotating the handle; a plurality of computer tablets disposed on the digital podium frame in a multi-tablet podium top; a five-wheel base configured to move the digital podium; a framework having four pedals, wherein the two front pedals are configured to move the podium forward and the two back pedals are configured to move the podium backward; and a divider to prevent the pressure of the standing person, so that to move forward a user uses toes simultaneously by standing on the divider; and wherein the digital podium is configured to project and relay teaching material through a multi-tablet podium into classroom projectors or mini laser projector, and into a dual tablet notebook of each child in classroom.

Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

Abstract: A display module includes a display panel which includes a substrate and a periphery circuit. The substrate has a display area and a strip region beside the display area. The substrate is bent with respect to an axis to form a curved shape. The maximum value of the curvature of the display area in a direction perpendicular to the axis is a first curvature. The periphery circuit is disposed on the strip region. The strip region in a direction perpendicular to the axis has a second curvature smaller than the first curvature.

Abstract: A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

Abstract: A technology is described for a non-intrusive power detection system. An example system may include a non-intrusive power detector configured to be electrically coupled to an alternating current (AC) power line to non-intrusively detect at least one of an alternating current or a voltage in the AC power line. A power change trigger may be coupled to the non-intrusive power detector and configured to detect a change in power in the AC power line. An indicator may be coupled to the power change trigger. The indicator may be configured to indicate when a power change occurs based on an output of the power change trigger.

Abstract: Embodiments herein describe techniques for wafer to wafer stacking of integrated circuit chips (e.g., dice) to form stacked IC devices. In one example, a stacked IC device is provided that includes a first wafer, a second wafer, and first conductive bridge. The second wafer is stacked on and secured to the first wafer. The second wafer has a plurality of IC dice that are communicatively coupled to a plurality of IC dice formed on the first wafer. The first conductive bridge has a first end that is sandwiched between the first and second wafers. The first conductive bridge shorts exposed pads of dice formed in the exclusion zones of the first and second wafers.

Abstract: Electronic devices and methods for fabricating electronic devices are provided. In one example, an electronic device includes an electronic device body structure having a substantially hermetically sealed cavity formed therein. A getter film is in fluid communication with the substantially hermetically sealed cavity. Conductive features are accessible from outside the substantially hermetically sealed cavity and are operatively coupled to the getter film for electrical communication with the getter film.

Abstract: The Invention discloses and provides a kind of dimmer holding current control circuit for phase cut dimming power supply, which comprises phase cut dimming power supply circuit and LED lamp (1) and dimmer holding current control circuit (2). The dimmer holding current control circuit (2) is composed of rectifier diode I (D1), rectifier diode II (D2), field-effect transistor (Q1), triode (Q2), current-limiting resistance I (R1), current-limiting resistance II (R2), sampling resistance I (R4), sampling resistance II (R5), diode (D3), capacitance (C1) and resistance (R3). The anodes of the rectifier diode I (D1) and the rectifier diode II (D2) are respectively connected to L terminal and N terminal of main supply input. The Invention makes the current small and stable through current limitation. The Invention can be widely used in the field of phase cut dimming power supply.

Abstract: A slide switch includes a case forming an accommodation space, a first contact disposed in the accommodation space, a second contact disposed in the accommodation space, a third contact disposed in the accommodation space, and a slider fixed to the third contact. The slider is movable between a first position in which the first contact and the second contact are electrically insulated from each other and a second position in which the first contact and the second contact are electrically connected to each other via the third contact. The case includes a projection supporting the third contact in a normal direction of a plane which includes a moving path of the slider in the accommodation space.

Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.

Abstract: A communication module includes a circuit substrate having a first high-frequency processing section related to mobile phone communication, a second high-frequency processing section that processes reception signals related to satellite positioning systems, a system section having a baseband processing section and application processing section, and a power circuit section, a sealing member covering the electronic components mounted on the circuit substrate, a conductive shield layer formed on a surface of the sealing member, and a shield wall formed in the sealing member so as to demarcate a mounting area of the first high-frequency processing section and a mounting area of the second high-frequency processing section.

Abstract: An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.

Abstract: A micro-fabricated atomic clock structure is thermally insulated so that the atomic clock structure can operate with very little power in an environment where the external temperature can drop to ?40° C., while at the same time maintaining the temperature required for the proper operation of the VCSEL and the gas within the vapor cell.

Abstract: An Omedia panel may be provided that includes an at least one network interface device, a housing, and a front panel. The at least one network interface device might be in communication with a service provider network. The housing may be integrated into a wall of a customer premises and positioned within a wall cavity of the wall. The housing might be configured to support the at least one network interface device. The front panel may be communicatively interfaced with the at least one network interface device such that a user can access one or more ports of the at least one network interface device via the front panel.

Abstract: A modified TO-can assembly is provided that has greater versatility with respect to spatial constraints than known TO-can assemblies and that is suitable for use in a wider range of applications than known TO-can assemblies. The modified TO-can assembly has a receptacle that has been modified to receive an optical fiber through its side instead of through its end. Within the TO-can assembly, the optical path is folded in order to couple the light between the optoelectronic component of the TOSA or ROSA and the end of the optical fiber. The combination of these features provides the modified TO-can assembly with a compact profile that makes it more versatile with respect to spatial constraints and therefore suitable for use in a wider range of applications.

Abstract: A method of testing a packaged semiconductor device under test (DUT) including a leadframe having a plurality of pins and at least one thermal pad with a semiconductor die having topside bond pads wire-bonded by bond wires to the plurality of pins and secured to the thermal pad. A leadframe sheet is provided including a plurality of packaged DUTs including support members that connect to the packaged DUTs. The thermal pads are shorted to one another, and the leadframe sheet is trimmed for electrically isolating the pins from one another. A first electrical contact is provided to the thermal pad. Active pins of the plurality of pins are electrically contacted with a contactor. Automatic testing identifies shorts between the active pins and the thermal pad.

Abstract: A semiconductor device component includes a first portion having a first hole usable as a nut insertion hole, and a second portion having a second hole adjacent to the first hole with a wall interposed therebetween. The first hole includes a first surface facing the wall, a second surface adjacent to the first surface, a third surface adjacent to the second surface, a fourth surface adjacent to the third surface and facing the first surface, a fifth surface adjacent to the fourth surface and facing the second surface, and a sixth surface adjacent to the fifth surface and the first surface and facing the third surface. A distance between the first and fourth surfaces is greater than a distance between the second and fifth surfaces, and greater than a distance between the third and sixth surfaces.

Abstract: A stacked module includes a first multilayer substrate including an opening having a stepwise wall face, and a first transmission line including a first grounding conductor layer, a second multilayer substrate supported on a stepped portion of the stepwise wall face and including a second transmission line including a second grounding conductor layer, a first chip mounted on a bottom of the opening and coupled to a third transmission line provided on the first multilayer substrate, and a second chip mounted on the front face of the second multilayer substrate and coupled to the second transmission line. A face to which the second grounding conductor layer or a fourth grounding conductor layer coupled thereto is exposed is joined to the stepped portion to which the first grounding conductor layer or a third grounding conductor layer coupled thereto is exposed, and the first and second grounding conductor layers are coupled.

Abstract: Contactless differential coupling structures can be used to communicate signals between circuits located on separate chips or from one chip to a probing device. The contactless coupling structures avoid problems (breaks, erosion, corrosion) that can degrade the performance of ohmic-type contact pads. The contactless coupling structures comprise pairs of conductive pads placed in close proximity. Differential signals are applied across a first pair of differential pads, and the signals are coupled wirelessly to a mating pair of conductive pads. Circuitry for generating and receiving differential signals is described.

Abstract: Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.

Abstract: Microelectronic assemblies and methods of making the same are disclosed.

Abstract: A power module and a power converter device including the power module include: two base plates with their main surfaces facing each other; a semiconductor circuit unit disposed between the two base plates; a connecting member that is connected to the two base plates and forms a housing region in which the semiconductor circuit unit is housed; and an insulating member that is placed between the base plate and the semiconductor circuit unit and secures electrical insulation of the base plate and the semiconductor circuit unit. A rigidity or thickness of the connecting member is less than a rigidity or thickness of the base plate.

Abstract: A multi-layer aluminum nitride ceramic, multi-heating element substrate is provided for forming electrical bonds between integrated circuits and an interposer structure using a thermocompression bonding process. The individually energizable heater element traces can be run through common regions of the heater surface platform. A network of cooling vias can be run through other parts of the substrate. The traces are then separately controlled and energized during a predetermined routine resulting in a temperature profile that maintains a substantially constant temperature plateau phase near a reflow temperature, and a more uniform temperature across the spaced apart surface regions of the heater substrate, thus imparting a more precisely uniform heating to the parts being bonded.

Abstract: An energy storage device includes an electrode made from an active material in which a plurality of channels have been etched. The channels are coated with an electrically functional substance selected from a conductor and an electrolyte.

Abstract: A power supply module and a method for manufacturing the same are disclosed. The power supply module includes a coil including a coil body and a connecting terminal; electronic components at least including an integrated circuit chip; a connector configured to be electrically connected with the coil and the electronic component; and a magnetic conductor configured to enclose in and around the coil body and the electronic component, wherein the connector is integrally formed with the integrated circuit chip when manufacturing the latter. The present disclosure can make the structure of the power supply module be more compact to further meet the needs of miniaturization design, reduce material consumption, simplify procedure, and therefore reduce the production costs.

Abstract: An example embodiment includes a TO can including a header, an RF pin opening, an internal volume, an RF pin, a submount, and a flex circuit. The header defines the RF pin opening. The internal volume is defined by a TO can housing and an interior header surface. The RF pin extends through the RF pin opening such that a first surface connection is located in the internal volume and a second surface connection is located outside of the internal volume and extends past an exterior header surface. The submount is located in the internal volume and the submount includes a submount trace. The submount trace includes a pin connection portion in-line with the RF pin and electrically coupled to the first surface connection. The flex circuit includes a flex trace further including a flex trace connection in-line with the RF pin and electrically coupled to the second surface connection.

Abstract: A power transducer is downsized by reducing the size of a power source board and highly reliable. The power source board is provided in the power transducer and for a large-current circuit. The power transducer includes a power semiconductor module having lead terminals. Of the lead terminals provided for the power semiconductor module and connected with the main circuit board, predetermined one or ones of the lead terminals is or are connected with the main circuit board in the vicinity of a main circuit terminal stage and at a position or positions lower than the main circuit terminal stage. Alternatively, predetermined one or ones of the lead terminals is or are connected with the main circuit board at a position or positions lower than a position at which the main circuit terminal stage is provided.