Abstract: According to one embodiment, a semiconductor switch includes a main element including a switching element and an antiparallel diode, and a reverse voltage application circuit. The reverse voltage application circuit includes an auxiliary electric-power supply, a high-speed free wheeling diode, an auxiliary element, and a capacitor. The high-speed free wheeling diode comprises a plurality of diodes connected in series.

Abstract: A power module includes one or more semiconductor power devices bonded to an insulated metal substrate (IMS). A plurality of cooling fluid channels is integrated into the IMS.

Abstract: A crystal oscillator is configured by accommodating a crystal blank that functions as a crystal unit and an IC chip that includes at least an oscillator circuit using the crystal blank into a container in an integrated manner. In the IC chip, the oscillator circuit is connected to the crystal unit via a pair of crystal connecting terminals, an output from the oscillator circuit is supplied to a plurality of output buffers. In relation to the crystal connecting terminal having a phase opposite to that of an output from the on/off controllable output buffer, an output terminal of this output buffer is disposed farther than an output terminal of the output buffer that is not subjected to the on/off control.

Abstract: The invention relates to a method for generating an electronic system for application to freeform surfaces, a method for producing freeform surfaces having an electronic system, and an electronic system and a combination of a freeform surface having at least one such system. According to the invention, an elastic interconnect device having an elastic substrate and an elastic, fanned-out contact structure with contact surfaces comprised of conductor lines is generated first. Then, electronic components are mounted on the interconnect device. Finally, the interconnect device is encapsulated. If a freeform surface with an electronic system is to be generated, the electronic system produced in this way is then mounted on the previously provided freeform surface.

Abstract: A substrate for mounting a preamp chip thereupon, fabricated using a stiffener layer made of a conductive material; an insulating layer provided over the circuitry area of the substrate; a circuitry made of a conductive material provided over the insulating layer; and a flap which is an extension of the stiffener layer having no insulating layer provided thereupon. The flap is fabricated to fold over the preamp chip to remove heat therefrom.

Abstract: A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Abstract: Provided is a semiconductor photodetector element which is reduced in manufacturing cost and improved in precision. The semiconductor photodetector element includes: a first photodiode formed in a P-type silicon substrate; a second photodiode formed in the P-type silicon substrate and has the same structure as that of the first photodiode; a color filter layer formed above the first photodiode from a green filter; a color filter layer formed of a black filter above the second photodiode; and an arithmetic circuit portion which subtracts a detection signal of the second photodiode from a detection signal of the first photodiode.

Abstract: An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode. The first electrode and/or the second electrode has a corrugated surface facing the dielectric material.

Abstract: A clip interconnect comprises a columnar part, a bridge part, and a locking feature. The bridge part has a plurality of sides. The columnar part and the bridge part are configured to form an angle at an interface between the columnar part and the bridge part. The locking feature is located in at least one of the plurality of sides of the bridge part. The locking feature comprises an alternating pattern of teeth and valleys.

Abstract: The present disclosure relates to an improved integrated circuit package and method with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.

Abstract: Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assists in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assists in impedance matching.

Abstract: A transmission line formed in a device including a stack of first and second chips having their front surfaces facing each other and wherein a layer of a filling material separates the front surface of the first chip from the front surface of the second chip, this line including: a conductive strip formed on the front surface side of the first chip in at least one metallization level of the first chip; and a ground plane made of a conductive material formed in at least one metallization level of the second chip.

Abstract: According to one embodiment, a ceramic substrate for mounting a device is provided. The ceramic substrate includes a through-hole and a recessed portion provided on at least one edge surface thereof.

Abstract: A high frequency package in which the resonance frequency of a metal seal ring is high, a reflection loss and a insertion loss of an input terminal and an output terminal are reduced in working frequency, and which has an excellent RF (radio frequency) characteristic in such as a millimeter wave, and a manufacturing method for the same are provided. The high frequency package has a minimum of an conductor base plate, a ceramic frame, the metal seal ring arranged on the ceramic frame, a solder metal layer arranged on the metal seal ring, a resonance frequency adjustment conductor formed of a conductor having an opening arranged on the solder metal layer, and a ceramic cap arranged on the resonance frequency adjustment conductor. The resonance frequency adjustment conductor is arranged so that an opening may correspond to a high portion of a loop of bonding wire.

Abstract: The present invention relates to a self-cooled thyistor device for ultra-high voltage fault current limiter. a self-cooled thyristor valve, it adopts horizontal structure consisted by frames, frames is divided into upper and below two spaces by crossbeams, the bottom of frames is supported by insulators. There is a cross plate between two vertical said frames, the cross plate mounts resistors connect with a high potential plate and capacitor through two wires. There is a thyistor string in said frame upper space, which is constituted of thyistors and cooler series. The thyistor string is compressed tightly by press-fit mechanism, thyistor string crosses current transformers. There are high potential plates on both sides of the thyistor, the number of the potential plates is equal to that of thyistor. One side of the high potential plates links frames, said current transformers connects with high potential plates.

Abstract: An IC device includes a base plate, a plurality of terminal pins, a functional component such as an IC chip, and a resin package for protection of the functional component. The base plate is generally flat and formed with a plurality of through-holes into which the terminal pins are inserted. The functional component, disposed away from the base plate, is mounted on a printed circuit board to be electrically connected to at least one of the terminal pins. While enclosing the functional component, the resin package is held in contact with the upper surface of the base plate.

Abstract: A two-beam semiconductor laser device 10 includes: a two-beam semiconductor element LDC having a first and a second semiconductor laser elements LD1 and LD2 that can be driven independently and that are formed integrally on a substrate; and a submount 63 having, mounted on a front part thereof, the two-beam semiconductor laser element LDC with the light-emitting face thereof directed forward and having a first and a second electrode pads 64 and 65 connected to electrodes 61 and 62 of the first and second semiconductor laser element LD1 and LD2 by being kept in contact therewith. The first and second electrode pads 64 and 65 are formed to extend farther behind the two-beam semiconductor laser element LDC, and wires 14 and 16 are wire-bonded behind the two-beam semiconductor laser element LDC.

Abstract: A method for manufacturing a power module substrate, includes: preparing a ceramics substrate and a metal plate made of pure aluminum; a fusion step in which the ceramics substrate and the metal plate are stacked in layers with a brazing filler metal interposed therebetween, and a fused aluminum layer is formed at an interface between the ceramics substrate and the metal plate by fusing the brazing filler metal which is caused by heating; and a solidifying step in which the fused aluminum layer is solidified by cooling, and a crystal is grown so as to be arranged in a crystal orientation of the metal plate when the fused aluminum layer is solidified.

Abstract: A package assembly comprises an electronic device; a package body; at least a first plurality of leads having a first geometrical shape and a second plurality of leads having a second geometrical shape, protruding from the package body; each of the first plurality of leads being located in corners of the package body; or the first and the second plurality of leads arranged in at least a first row and a second row located in parallel to the first row; each of the rows comprising at least two leads; the first row being transformable into the second row by mirroring the first row along a symmetry plane of the package body; each of the first plurality of leads having the first geometrical shape different from the second geometrical shape.

Abstract: One aspect is a circuit arrangement including a first semiconductor switching element, a second semiconductor switching element connected in series with the first semiconductor switching element and a freewheeling element connected in parallel with the second semiconductor switching element.

Abstract: A fan system includes a motor control module external to a motor housing of a fan assembly. The motor control module includes a speed control module. The fan assembly includes a fan and the motor housing. One or more first conductors are configured to connect the motor control module to a motor in the motor housing. One or more second conductors are configured to connect the motor control module to a host device control module. The host device control module is separate from the motor control module and is configured to generate a control signal. The speed control module is configured to control speed of the fan based on the control signal.

Abstract: Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.

Abstract: A power semiconductor device includes a plurality of power semiconductor elements constituting upper and lower arms of an inverter circuit, a first sealing member sealing the plurality of power semiconductor elements, a positive electrode-side terminal and a negative electrode-side terminal each connected with any of the plurality of power semiconductor elements and protruding from the first sealing member, a second sealing member sealing at least a part of the positive electrode-side terminal and at least a part of the negative electrode-side terminal, and a case in which the power semiconductor elements sealed with the first sealing member are housed.

Abstract: An RF-coupled digital isolator includes a first leadframe portion and a second leadframe portion, electrically isolated from one another. The first leadframe portion includes a first main body and a first finger. The second leadframe portion includes a second main body and a second finger. The first main body is connected to a first ground, and the second main body is connected to a second ground that is electrically isolated from the first ground. The first finger and the second finger are electrically isolated from one another, e.g., by a plastic molding compound that forms a package for the digital isolator. The first finger acts as a primary of a transformer, and the second finger acts as a secondary of a transformer, when an RF signal drives to the first finger. The first finger and the second finger can be substantially parallel or anti-parallel to one another.

Abstract: A power module and a power converter device including the power module include: two base plates with their main surfaces facing each other; a semiconductor circuit unit disposed between the two base plates; a connecting member that is connected to the two base plates and forms a housing region in which the semiconductor circuit unit is housed; and an insulating member that is placed between the base plate and the semiconductor circuit unit and secures electrical insulation of the base plate and the semiconductor circuit unit. A rigidity or thickness of the connecting member is less than a rigidity or thickness of the base plate.

Abstract: Embodiments described herein may include devices and methods of manufacturing devices for sensing and monitoring physiological parameters of a patient. Specifically, certain embodiments disclose the use of conductive and nonconductive overmold materials to protect the device, increase reliability, increase comfort, and increase accuracy of the parameters measured.

Abstract: A fabrication method for metallized a ceramics substrate including the steps of: forming a first conductive paste layer containing metallic powder on a sintered ceramics substrate; forming a second conductive paste layer containing metallic powder of which average particle diameter is different from that of metallic powder constituting the first conductive paste layer; and forming a first conductive layer and a second conductive paste layer. The surface roughness of the first conductive layer and the second conductive layer is different. By this method, it is possible to secure airtightness of the metallized ceramics substrate even if it is a multilayered substrate having a plurality of metallized layers.

Abstract: A package enclosing at least one microelectronic element (60) such as a sensor die and having electrically conductive connection pads (31) for electric connection of the package to another device is manufactured by providing a sacrificial carrier; applying an electrically conductive pattern (30) to one side of the carrier; bending the carrier in order to create a shape of the carrier in which the carrier has an elevated portion and recessed portions; forming a body member (45) on the carrier at the side where the electrically conductive pattern (30) is present; removing the sacrificial carrier; and placing a microelectronic element (60) in a recess (47) which has been created in the body member (45) at the position where the elevated portion of the carrier has been, and connecting the microelectronic element (60) to the electrically conductive pattern (30). Furthermore, a hole (41) is arranged in the package for providing access to a sensitive surface of the microelectronic element (60).

Abstract: A semiconductor component and a method of manufacturing the semiconductor component that reduces parasitic elements. A semiconductor chip is coupled to a semiconductor chip receiving area of a support structure. The semiconductor chip has at least two power semiconductor devices. A drain contact of a first power semiconductor device is coupled to a source contact of a second power semiconductor device and the drain and source contacts of the first and second power semiconductor devices are joined to the semiconductor chip receiving area. Another semiconductor chip may be bonded to a second semiconductor chip receiving area of the support structure. An energy storage element may be coupled between the source contact of the first power semiconductor device and the drain contact of the second semiconductor device. A protective structure may be formed over the semiconductor chips and the energy storage element.

Abstract: A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.

Abstract: A multilayer wiring board is inhibited from being warped when flip-chip bonding a semiconductor device to the multilayer wiring board, thereby increasing the reliability of connecting the semiconductor assembly to a motherboard. A heat-insulating layer 10 is provided between a core board 1 and a flip-chip bonding-side insulating layer 3 in a multilayer wiring board MB1, thereby preventing thermal conduction from a heat tool, so that the amounts of thermal expansion of the core board 1 and an insulating layer 4 are minimized, resulting in reduced warpage of the multilayer wiring board MB1.

Abstract: An electromagnetic shielding device includes a metal frame mounted on a circuit board and having a looped surrounding wall configured with an inner space divided into first and second space portions by a partition wall unit. A cover is mounted fittingly into the inner space in the metal frame, and includes a dielectric cover body, and a conductive material layer attached to an outer surface of the cover body. The cover body has a looped surrounding wall extending downwardly from a periphery of a top wall and disposed in proximity to the looped surrounding wall of the metal frame such that the conductive material layer is in electrical contact with the looped surrounding wall of the metal frame. The cover cooperates with the metal frame to define first and second cavities having different depths and corresponding respectively to the first and second space portions.

Abstract: A semiconductor device includes a semiconductor mounting substrate, a mother case having an opening and housing the semiconductor mounting substrate, a plurality of securing members provided along a rim of the mother case, a screw terminal, and a lid member. The screw terminal has a flat plate portion, an insertion portion extending from the flat plate portion, and a terminal bottom portion, is secured to the securing members by insertion of the insertion portion between adjacent securing members, and is electrically connected to the semiconductor mounting substrate on the terminal bottom portion side. The lid member closes the opening with the screw terminal secured to the securing members. The screw terminal is bent such that the flat plate portion faces an upper surface of the lid member closing the opening. The semiconductor device that can achieve reduction in size of the entire device is obtained.

Abstract: A power supply assembly includes an enclosure body, a cover panel mounted to the enclosure body, a power supply, and a positioning element mounted to the cover panel. The enclosure body includes a bottom panel, a rear panel substantially perpendicular to the bottom panel, and a side panel substantially perpendicular to the bottom panel and the rear panel. The power supply assembly is mounted in the enclosure body and is prevented from moving in a first direction, that is substantially perpendicular to the rear panel, and a second direction, that is substantially perpendicular to the side panel, and disposed between the bottom panel and the cover panel. The positioning element includes a first ladder-shaped positioning tab abutting two adjacent surfaces of the power supply and preventing the power supply assembly from moving in a third direction, that is substantially perpendicular to the cover panel and the second direction.

Abstract: According to one embodiment, a semiconductor device includes a matrix and a semiconductor element bonded to the matrix via a bonding layer. The bonding layer includes a first layer and a second layer having a viscosity lower than a viscosity of the first layer at a bonding temperature. The first layer has a portion in which an end of the first layer is set further back to an inside than an end of the semiconductor element. At least a part of the portion set back to the inside is filled with a part of the second layer extruded from a periphery of the first layer to an outside.

Abstract: An arrangement for the equipping of electronic packages with elliptical C4 connects possessing optimal orientation for enhanced reliability. Furthermore, disclosed is a method providing elliptical C4 connects which possesses optimal orientation for enhanced reliability, as implemented in connection with their installation in electronic packages. Employed are essentially elliptical solder pads or elliptical C4 pad configurations at various preferably corner locations on a semiconductor chip.

Abstract: An exemplary enclosure for housing electronics useful with an elevator system includes a first sidewall and a second sidewall adjacent the first sidewall. A third sidewall is at an oblique angle relative to the first sidewall. The third sidewall provides a support surface for supporting electronics inside the enclosure. The first and second sidewalls are moveable relative to the third sidewall to provide a single opening facing the support surface.

Abstract: Various exemplary embodiments relate to a stiffener for use with and integrated circuit (IC). The stiffener can be attached to the IC, and can utilize a planar portion and one or more beam portions that project from the planar portion at a non-zero angle. The stiffener can alternatively include a frame formed of beam portions that are adjacent the sides of the IC. The stiffener can provide added stiffness to the IC package to resist warping of the IC during soldering.

Abstract: Flip chip packages having warpage control and methods for fabricating such packages are described. In one embodiment, the flip chip package comprises a package substrate; a chip coupled to the package substrate; and a ring structure coupled to the package substrate and positioned laterally around the periphery of the chip so that a surface of the chip is exposed, wherein the ring structure comprises one or more compressive members, each of the one or more compressive members compressively opposed to a surface of the package substrate to counter or absorb stresses in the package substrate.

Abstract: The present invention relates to a self-cooled thyistor device for ultra-high voltage fault current limiter. a self-cooled thyristor valve, it adopts horizontal structure consisted by frames, frames is divided into upper and below two spaces by crossbeams, the bottom of frames is supported by insulators. There is a cross plate between two vertical said frames, the cross plate mounts resistors connect with a high potential plate and capacitor through two wires. There is a thyistor string in said frame upper space, which is constituted of thyistors and cooler series. The thyistor string is compressed tightly by press-fit mechanism, thyistor string crosses current transformers. There are high potential plates on both sides of the thyistor, the number of the potential plates is equal to that of thyistor. One side of the high potential plates links frames, said current transformers connects with high potential plates.

Abstract: Provided is a simple and low-cost method for manufacturing, in a short time, many light emitting devices wherein adhesiveness between a leadframe and a thermosetting resin composition is high. The method for manufacturing the light emitting device having a resin package (20) wherein the optical reflectivity at a wavelength of 350-800 nm after thermal curing is 70% or more and a resin section (25) and a lead (22) are formed on substantially a same surface on an outer surface (20b) has: a step of sandwiching a leadframe (21) provided with a notched section (21a) by an upper molding die (61) and a lower molding die (62); a step of transfer-molding a thermosetting resin (23) containing a light-reflecting substance (26), in a molding die (60) sandwiched by the upper molding die (61) and the lower molding die (62) and forming a resin-molded body (24) on the leadframe (21); and a step of cutting the resin-molded body (24) and the leadframe (21) along the notched section (21a).

Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate and a die, and coupling the die to the substrate, wherein a gap remains between the die and the substrate. The method also includes placing an underfill material on the substrate and delivering at least part of the underfill material into the gap. The method also includes controlling the flow of the underfill material in the gap using magnetic force. Other embodiments are described and claimed.

Abstract: A power semiconductor module is disclosed including a housing for receiving at least one essentially board-type circuit carrier, the circuit carrier being provided with a metallization on at least one part of its surface and being populated with and electrically connected to at least one power semiconductor, rigid, integral and essentially straight load connection elements being applied on the metallized part of the metallized surface of the circuit carrier, which load connection elements are electrically and mechanically fixedly connected to the circuit carrier by one of their ends and project essentially perpendicularly into the housing interior, separate connection terminal elements for electrical conduct-making being placed onto the free end of the load connection elements.

Abstract: The invention discloses a device comprising a stack of at least two layers, which may comprise active or passive discrete components, TSOP and/or ball grid array packages, flip chip or wire bonded bare die or the like, which layers are stacked and interconnected to define an integral module. A first and second layer comprise an electrically conductive trace with one or more electronic components in electrical connection therewith. The electrically conductive traces terminate at a lateral surface of each of the layers to define an access lead. An interposer structure is disposed between the layers and provides an interposer lateral surface upon which a conductive layer interconnect trace is defined to create an electrical connection between predetermined access leads on each of the layers.

Abstract: An electronic assembly has at least one conductor substrate carrying components, which conductor substrate is surrounded by a mechanical protection. The conductor substrate is encased using a molding compound as a mechanical protection and is contacted by at least one intrinsically stiff, spring-elastic electrical connection conductor, the connection conductor being embedded in the molding compound, at least in sections.

Abstract: The adhesive composition of the invention comprises a thermoplastic resin, a radical polymerizing compound, a radical polymerization initiator and a radical polymerization regulator. According to the present invention it is possible to provide an adhesive composition, a circuit connecting material, a connection structure for a circuit member and a semiconductor device whereby curing treatment can be carried out with sufficient speed at low temperature, curing treatment can be carried out with a wide process margin, and adequately stable adhesive strength can be obtained.

Abstract: A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.

Abstract: Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by conductive paths.

Abstract: An electronic device such as a media player may be formed from electrical components such as integrated circuits, buttons, and a battery. Electrical input-output port contacts may be used to play audio and to convey digital signals. Electrical components for the device may be mounted to a substrate. The components may be encapsulated in an encapsulant and covered with an optional housing structure. The electrical input-output port contacts and portions of components such as buttons may remain uncovered by encapsulant during the encapsulation process. Integrated circuits may be entirely encapsulated with encapsulant. The integrated circuits may be packaged or unpackaged integrated circuit die. The substrate may be a printed circuit board or may be an integrated circuit to which components are directly connected without interposed printed circuit board materials.

Abstract: To provide a composite semiconductor device capable of preventing malfunction of preventing electrical circuits and contributing to miniaturization of a power converter. A composite semiconductor device 10 has a structure in which a first power semiconductor element 13 that passes current from a second terminal C1 to a third terminal E1 according to a signal input from a first terminal G1 and a second power semiconductor element 16 that passes current from a second terminal C2 to a third terminal E2 according to a signal input from a first terminal G2 are formed in a single substrate (chip) 20. The third terminal E2 of the second power semiconductor element 16 is electrically connected to the first terminal G1 of the first power semiconductor element 13.