Abstract: An electronic chip includes a plurality of conducting pins and a plurality of insulating blocks. The conducting pins are disposed on an outer side of the electronic chip to provide electrical connections between the electronic chip and an external circuit. Each of the insulating blocks is disposed between two adjacent conducting pins.

Abstract: An electronic package structure including at least one first electronic element, a second electronic element and a lead frame is provided. The second electronic element includes a body having a cavity. The first electronic element is disposed in the cavity. The lead frame has a plurality of leads. Each of the leads has a first end and a second end. The first end of at least one of the leads extends to the cavity to electrically connect the first electronic element.

Abstract: An improved integrated circuit (IC) layout is described that provides conductive pads on opposite sides of a substrate. The conductive pads provide for connectivity to the chip in different chip orientations. Accordingly, multiple chips having the same layout can be provided in a package, instead of providing each chip with a different layout. Since the same layout may be used for each chip, manufacturing costs are reduced.

Abstract: An integrated circuit structure includes a bottom die; a top die bonded to the bottom die with the top die having a size smaller than the bottom die; and a molding compound over the bottom die and the top die. The molding compound contacts edges of the top die. The edges of the bottom die are vertically aligned to respective edges of the molding compound.

Abstract: A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.

Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.

Abstract: A nano-scale compliant mechanism includes a coupler and a plurality of nanotubes disposed for nano-scale motion relative to a grounded component. The nanotubes are fastened at one end to the coupler and at the other end to ground, to guide motion of the coupler relative to the ground. Particular embodiments include a plurality of parallel carbon nanotubes. An exemplary embodiment exhibits first and second regions of mechanical behavior; a first region governed by bulk elastic deformation of the nanotubes and a second region governed by compliant, hinge-like bending of the buckled nanotubes.

Abstract: Disclosed is a glass laminate comprising a thin glass substrate having a first main surface and a second main surface, a supporting glass substrate having a first main surface and a second main surface, and a resin layer and an outer frame layer arranged between the thin glass substrate and the supporting glass substrate. The resin layer is fixed to the first main surface of the supporting glass substrate and is in close contact with the first main surface of the thin glass substrate, while having easy releasability from the first main surface of the thin glass substrate. The outer frame layer surrounds the resin layer on the first main surface of the supporting glass substrate so that the outside air does not come into contact with the resin layer.

Abstract: A multimode system with at least two end points may include a multimode signaling path that, in some embodiments, is a multimode cable or a multimode board and is pluggably connectable to packages at each end point. Each end point may include a processor die package coupled to a socket. The socket may also receive a connector that couples the cable to the package. Power supply signals and input/output signals may be decoupled at each end point.

Abstract: A chip card holder, for securing a chip card in an electronic device, includes a housing, an elastic member and a strip member. The housing defines a receiving chamber. The elastic member is secured in the receiving chamber and has an elastic foldable resisting section. The strip member connects with the resisting section and an end of the strip exposes from the receiving chamber. A chip card is assembled in the receiving chamber, the resisting section of the elastic member resists against the chip card, the resisting section is folded elastically by pulling the strip member and the chip card is withdrawn by the pushing of the resisting section.

Abstract: A camera includes a first substrate having top and bottom surfaces, a second substrate having top and bottom surfaces, a spacer substrate between a substantially planar portion of the top surface of the second substrate and a substantially planar of the bottom surface of the first substrate, at least two of the first substrate, the second substrate and the spacer substrate sealing an interior space, a detector within the interior space, and an electrical interconnection extending from the detector to outside the interior space.

Abstract: A method providing elliptical C4 connects which possesses optimal orientation for enhanced reliability, as implemented in connection with their installation in electronic packages. Employed are essentially elliptical solder pads or elliptical C4 pad configurations at various preferably corner locations on a semiconductor chip.

Abstract: Packaged optoelectronic device include a first barrier layer having a plurality of feedthrough apertures communicating with at least one electrode layer of the device, and a plurality of conductive patches disposed on at least one of the plurality of feedthrough apertures for electrically connecting the device to a power supply. Each conductive patch includes a conductive metal surface layer and a non-conducting surface layer having an opening exposing the metal surface layer.

Abstract: This invention patent is a utility type of car fan controller. The controller has a housing and inside the housing is a circuit. The housing has a top cover forming a cavity and flat bottom plate. The circuit has a circuit board and an adjustment device with other electronic components. The circuit board has a socket connector and a wire harness connector. The top cover has socket connector aligned with socket connector opening. The top cover also has a wire harness connector aligned to wire harness connector socket. The modular practical new type of invention design facilitates faster assembly and more convenient flexible use.

Abstract: An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode. The first electrode and/or the second electrode has a corrugated surface facing the dielectric material.

Abstract: Embodiments of the present invention provide a system for distributing a thermal interface material. The system includes: an integrated circuit chip; a heat sink; and a compliant thermal interface material (TIM) between the integrated circuit chip and the heat sink. During assembly of the system, a mating surface of the heat sink and a mating surface of the integrated circuit chip are shaped to distribute the TIM in the predetermined pattern as the TIM is pressed between the mating surface of heat sink and a corresponding mating surface of the integrated circuit chip.

Abstract: An integrated circuit for accessing a universal serial bus (USB) device via a USB 3.0 receptacle is provided. The integrated circuit includes a plurality of pins and a controlling unit. The pins include a first group for receiving and transmitting a first pair of differential signals of the USB device, a second group for receiving a second pair of differential signals from the USB device, and a third group for transmitting a third pair of differential signals to the USB device. The second group is disposed between the first and third groups. The controlling unit controls the plurality of pins to receive or transmit the first, second or third pair of differential signals.

Abstract: A mount structure includes a wiring board and a semiconductor device composed of a light-emitting device or a light-receiving device mounted on one surface side of the wiring board such that an optical axis thereof is oriented in a direction that extends along a board surface of the wiring board. On the one surface side of the wiring board, a first pad on which a first terminal of the semiconductor device is mounted, a second pad on which a second terminal of the semiconductor device is mounted, and a light-shielding conductive layer are formed using the same conductive layer. The first pad and the second pad are arranged on respective sides of an imaginary center line along which the optical axis of the semiconductor device extends and the light-shielding conductive layer is provided at a position beneath a light emission center or a light reception center of the semiconductor device in plan view.

Abstract: Provided is a power module capable of welding a snubber capacitor without causing melting damage to a resin housing by welding heat. When leads of a snubber capacitor are respectively welded to upper surfaces of the specific portions of a P-pole bus bar and an N-pole bus bar, the welding heat generated at the specific portions of the P-pole bus bar and the N-pole bus bar is respectively radiated from openings, through which the lower surfaces of the specific portions of the P-pole bus bar and the N-pole bus bar are exposed. As a result, the snubber capacitor can be later appended by welding without causing melting damage to the resin housing due to the welding heat. During welding, a separate cooling head is inserted into the openings to forcibly cool the lower surfaces of the specific portions of the P-pole bus bar and the N-pole bus bar respectively, so that the melting damage to a resin housing can be more reliably avoided.

Abstract: One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices.

Abstract: A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming an indent, having a flange and an indent side, from a peripheral region of the active side; and forming a conformal interconnect, having an elevated segment, a slope segment, and a flange segment, over the indent.

Abstract: A motor controller which eliminates a positioning operation between a power semiconductor element and a base plate to improve the assembly process is provided. The motor controller has a power semiconductor element closely contacted with a heatsink and mounted in a first base plate, wherein a spacer having an engaging section formed therein as a hole for the power semiconductor element is interposed between the heatsink and the base plate, and the power semiconductor element is positioned in the spacer. Further, the peripheral wall of the hole is arranged so as to shut off a space between a terminal projecting from the side of the power semiconductor element and the heatsink.

Abstract: A clamp includes a base, a limiting member, a positioning assembly, and a pressing assembly. The base defines a gap. The limiting member defines a limiting slot corresponding to the gap. The positioning assembly is positioned at a first side of the limiting member. The positioning assembly includes a positioning handle and a pushing member. The pushing member extends in the limiting slot, and the positioning handle runs through the limiting member and is connected to the pushing member. The pressing assembly is positioned at a second side opposite to the first side. The pressing assembly runs through the limiting member and extends in the limiting slot. A chip is capable of being pushed to the position of the gap by the pushing member with operating the positioning handle and resists against the pressing assembly, thus being clamped. The present disclosure also provides a mounting method using the clamp.

Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Abstract: A semiconductor device that reduces the size and cost of functional macro chips used in a chip-on-chip configuration. Functional macro chips each include a macro region. The macro regions are formed adjacent to one another. A pad region for testing the functional macro chips is formed surrounding the macro regions.

Abstract: A package includes a conductive base plate; a ceramic wall configured to house a semiconductor device and a circuit board disposed adjoining of the semiconductor device, the ceramic wall configured to be disposed on the conductive base plate, the ceramic wall configured to include a frame shape having a screw hole in four corners; a metal seal ring configured to include a framed shape and be disposed on the ceramic wall; and a ceramic cap configured to be disposed on the metal seal ring, and the ceramic wall is screwed to the conductive base plate through the screw hole, and the package can radiate heat satisfactory in the heat generation from the semiconductor device, and can improve reliability, and can be applied to the high frequency of the microwave/millimeter wave/sub-millimeter wave band.

Abstract: The field of the invention is that of the wiring of electromechanical micro-systems also called MEMS (the acronym standing for Micro Electro Mechanical Systems) and more particularly micro-systems carrying out measurements of physical quantities such as for example micro-gyrometers, micro-accelerometers or pressure micro-sensors. More precisely the subject of the invention is a wiring relay for an electromechanical micro-system enclosed in a protective package. A first end of a wire bond of electrically conducting material is fixed to the micro-system electrical contact. The relay is fixed to at least one internal wall. The relay consists of an electrically insulating material. According to the invention, it comprises tracks of electrically conducting material, and one track is linked electrically with at least one internal electrical contact and with a second end of a wire bond.

Abstract: A semiconductor device according to a preferred embodiment of the present invention is a semiconductor device including a main substrate and one or more sub substrates, and the semiconductor device includes first heat generating devices mounted on the sub substrates, sub-substrate heatsinks mounted to the first heat generating devices, and a main-substrate heatsink mounted to the main substrate, wherein the sub-substrate heatsinks and the main-substrate heatsink are secured to each other, such that there is a predetermined positional relationship between the sub substrates and the main substrate.

Abstract: A wiring substrate includes: an insulating layer; a wiring formed on the insulating layer; and a solder resist layer formed on the insulating layer so as to cover at least a portion of the wiring, the solder resist layer being constituted by a plurality of layers, wherein the plurality of layers contain fillers of different grain diameters, a layer thickness of an innermost layer for constituting the plurality of layers is thicker than a layer thickness of the wiring, and a grain diameter of the filler contained in the innermost layer is smaller than a shortest interval between adjacent lines of the wiring.

Abstract: Embodiments of an apparatus and methods of forming interconnect between a workpiece and substrate and its application to packaging of microelectronic devices are described herein. Other embodiments may be described and claimed.

Abstract: One aspect is a circuit arrangement including a first semiconductor switching element, a second semiconductor switching element connected in series with the first semiconductor switching element and a freewheeling element connected in parallel with the second semiconductor switching element.

Abstract: Disclosed herein are a disc varistor having a capability to absorb a double amount of surge and a method of manufacturing the varistor. The varistor includes a disc-shaped first ceramic body having first and second electrodes on opposite surfaces thereof, and a disc-shaped second ceramic body having third and fourth electrodes on opposite surfaces thereof. A first lead wire is in interposed between the second and third electrodes and electrically connected to the second and third electrodes. The varistor also includes a second lead wire. The second lead wire has a body portion electrically connected to the first electrode of the first ceramic body, a first extension extending from the body portion to the second ceramic body, and a second extension extending from the first extension to the fourth electrode.

Abstract: A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die.

Abstract: An electric power converter has a main circuit section including a semiconductor module and a cooling device; a control circuit substrate section electrically connected to a signal terminal of the semiconductor module, and having a control circuit; and a power wiring section connected to a main electrode terminal of the semiconductor module. The main circuit section is interposed between the control circuit substrate section and the power wiring section.

Abstract: Microelectronic dies are thinned according to a variety of approaches, which may include bonding the dies to a substrate under vacuum, disposing a film over the dies and the substrate, and/or changing a center of pressure during thinning.

Abstract: An electronic assembly includes: a circuit substrate with a first mounting surface that has a plurality of spaced apart first mounting regions and at least one second mounting region spaced apart from the first mounting regions; a plurality of first electronic components mounted on the first mounting regions, respectively; and at least one dummy of a non-electronic component mounted on the second mounting region and having dimensions simulating those of the first electronic components. A method for making electronic devices is also disclosed.

Abstract: A carrier wafer for wafer level fabrication of imager structures comprising a substrate with trenches corresponding to locations of imager arrays on an imager wafer. A method of fabricating such a carrier wafer and a method of fabricating an imager module employing such a carrier wafer are also provided.

Abstract: An interposer and a method of manufacturing the same are provided. The interposer includes a substrate and a conductor portion formed inside the substrate. At least one insulating layer is formed on the substrate and on the conductor portion. A signal wiring portion is formed inside the insulating layer or on the insulating layer. A first pad is configured to receive an electronic part, and is formed on an outermost insulating layer of the at least one insulating layer. A connection conductor is formed in the at least one insulating layer so as to electrically connect the conductor portion to the first pad.

Abstract: A submount with an electrode layer having excellent wettability in soldering and method of manufacturing the same are disclosed. A submount (1) for having a semiconductor device mounted thereon comprises a submount substrate (2), a substrate protective layer (3) formed on a surface of the submount substrate (2), an electrode layer (4) formed on the substrate protective layer (3) and a solder layer (5) formed on the electrode layer (3) wherein the electrode layer (4) is made having an average surface roughness of less than 1 ?m. The reduced average surface roughness of the electrode layer (4) improves wettability of the solder layer (5), allowing the solder layer (5) and a semiconductor device to be firmly bonded together without any flux therebetween. A submount (1) is thus obtained which with the semiconductor device mounted thereon is reduced in heat resistance, reducing its temperature rise and improving its performance and service life.

Abstract: A device mounting board includes: an insulating resin layer; a wiring layer disposed on one main surface of the insulating resin layer; and a bump electrode connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A side surface of the bump electrode is curved inwardly toward the center axis of the bump electrode as viewed in a cross section including the center axis of the bump electrode, and the radius of curvature of the side surface changes continuously from a wiring layer end to a head end of the bump electrode.

Abstract: A semiconductor module includes a plurality of rectangular shaped semiconductor devices which are arranged in two rows such that each pair of adjacent semiconductor devices is in orientations differed by 90 degrees from each other. A plurality of wirings connect the semiconductor devices included in one of the two rows to the semiconductor devices included in the other row such that the semiconductor devices arranged in the same orientations are connected to each other.

Abstract: A device mounting board includes: an insulating resin layer; a wiring layer provided on one main surface of the insulating resin layer; and a bump electrode, electrically connected to the wiring layer, which is protruded from the wiring layer toward the insulating resin layer. Asperities are formed on the side surface of the bump electrode and the surface roughness of the side surface of the bump electrode is greater than that of the top surface of the bump electrode.

Abstract: An LED holder has a housing, a disc mounted in a lower end of the housing, a seat formed on the disc, a pair of sockets formed in the seat and a bracket mounted detachably on the seat to hole the LED. Hence, the LED is assembled and disassembled easily.

Abstract: An interposer includes an inorganic insulating layer, a first wiring formed in or on a surface of the inorganic insulating layer, an organic insulating layer formed over the inorganic insulating layer and on the first wiring, a second wiring formed on the organic insulating layer, and a conductor portion connecting the first wiring and the second wiring.

Abstract: A method for allowing an easier electric connection between layers of a multi-layer package structure using a metal pin fabricated based on semiconductor device processes is provided. A metal pin having a high aspect ratio is formed on a lower substrate, while a via hole is formed in an upper substrate. The metal pin is inserted into the via hole and adhered together to make an electric connection between the lower and upper substrates. The metal pin is obtained by patterning a thick photoresist material and plating a material thereon. The metal pin may have a core member obtained by performing a plating process on the surface of a patterned polymer based pin. Solder or gold is used for adhesion and electric connection between the signal line and the metal pin. The above electric connection method can be simpler and have improved structural stability compared with the typical connection method.

Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate and a die, and coupling the die to the substrate, wherein a gap remains between the die and the substrate. The method also includes placing an underfill material on the substrate and delivering at least part of the underfill material into the gap. The method also includes controlling the flow of the underfill material in the gap using magnetic force. Other embodiments are described and claimed.

Abstract: A substrate for mounting a device comprises: an insulating resin layer; a plurality of projected electrodes that are connected electrically to a wiring layer provided on one major surface of the insulating resin layer, and that project toward the insulating resin layer from the wiring layer; and a counter electrode provided at a position corresponding to each of the plurality of projected electrodes on the other major surface of the insulating resin layer. Among the projected electrodes, a projected length of part of the projected electrodes is smaller than that of the other projected electrodes; and the projected electrode and the counter electrode corresponding thereto are capacitively-coupled, and the projected electrode and the counter electrode are connected electrically.

Abstract: A two-beam semiconductor laser device 10 includes: a two-beam semiconductor element LDC having a first and a second semiconductor laser elements LD1 and LD2 that can be driven independently and that are formed integrally on a substrate; and a submount 63 having, mounted on a front part thereof, the two-beam semiconductor laser element LDC with the light-emitting face thereof directed forward and having a first and a second electrode pads 64 and 65 connected to electrodes 61 and 62 of the first and second semiconductor laser element LD1 and LD2 by being kept in contact therewith. The first and second electrode pads 64 and 65 are formed to extend farther behind the two-beam semiconductor laser element LDC, and wires 14 and 16 are wire-bonded behind the two-beam semiconductor laser element LDC.

Abstract: A two-beam semiconductor laser device 10 includes: a two-beam semiconductor element LDC having a first and a second semiconductor laser elements LD1 and LD2 that can be driven independently and that are formed integrally on a substrate; and a submount 63 having, mounted on a front part thereof, the two-beam semiconductor laser element LDC with the light-emitting face thereof directed forward and having a first and a second electrode pads 64 and 65 connected to electrodes 61 and 62 of the first and second semiconductor laser element LD1 and LD2 by being kept in contact therewith. The first and second electrode pads 64 and 65 are formed to extend farther behind the two-beam semiconductor laser element LDC, and wires 14 and 16 are wire-bonded behind the two-beam semiconductor laser element LDC.

Abstract: A disclosed semiconductor integrated circuit device includes a digital circuit and an analog circuit formed on one semiconductor substrate; a guard band configured to prevent noise generated in the digital circuit from being transmitted to the analog circuit; a first power supply terminal configured to supply a power-supply voltage to the analog circuit; a first ground terminal configured to supply a ground potential to the analog circuit; a second power supply terminal configured to supply the power-supply voltage to the digital circuit; a second ground terminal configured to supply the ground potential to the digital circuit; and a filter circuit positioned between the second power supply terminal, the second ground terminal, and the digital circuit and configured to remove the noise transmitted from the digital circuit.